MMDP-67204E-40QM [TEMIC]
FIFO, 4KX9, 40ns, Asynchronous, CMOS, PDFP28, 400 MIL, FLAT PACK, 28 PIN;
| 型号： | MMDP-67204E-40QM |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | FIFO, 4KX9, 40ns, Asynchronous, CMOS, PDFP28, 400 MIL, FLAT PACK, 28 PIN 先进先出芯片 光电二极管 |
| 文件： | 总15页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M67204E
4 K ꢀ 9 CMOS Parallel FIFO Rad Tolerant
Introduction
The M67204E implement a first-in first-out algorithm, Using an array of eigh transistors (8 T) memory cell, the
featuring asynchronous read/write operations. The FULL M67204E combine an extremely low standby supply
and EMPTY flags prevent data overflow and underflow. current (typ = 1.0 µA) with a fast access time at 40 ns
The Expansion logic allows unlimited expansion in word over the full temperature range. All versions offer battery
size and depth with no timing penalties. Twin address backup data retention capability with a typical power
pointers automatically generate internal read and write consumption at less than 2 µW.
addresses, and no external address information are
The M67204E is processed according to the methods of
required for the TEMIC FIFOs. Address pointers are
the latest revision of the MIL STD 883 (class B or S), ESA
automatically incremented with the write pin and read
SCC 9000 and QML.
pin. The 9 bits wide data are used in data communications
applications where a parity bit for error checking is
necessary. The Retransmit pin resets the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Features
D First-in first-out dual port memory
D 4096 × 9 organisation
D Fully expandable by word width or depth
D Asynchronous read/write operations
D Empty, full and half flags in single device mode
D Retransmit capability
D Fast access time: 40, 50 ns
D Wide temperature range : – 55 °C to + 125 °C
D Bi-directional applications
D Battery back-up operation 2 V data retention
D TTL compatible
D Single 5 V ± 10 % power supply
D High performance SCMOS technology
1
Rev. F – June 30, 1999
M67204E
Interface
Block Diagram
Pin Configuration
DIL ceramic 28 pin 600 mils
FP 28 pin 400 mils (Preview)
(top view)
W
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
I
8
I
3
I
2
I
1
I
0
2
I
I
I
I
4
3
5
6
7
4
5
6
FL/RT
RS
XI
7
FF
8
EF
Q
Q
Q
Q
Q
9
XO/HF
0
1
2
3
8
10
11
12
13
14
Q
Q
Q
Q
R
7
6
5
4
GND
2
Rev. F – June 30, 1999
M67204E
Pin Names
NAMES
DESCRIPTION
NAMES
FF
DESCRIPTION
I0–8
Q0–8
W
Inputs
Full Flag
Outputs
XO/HF
XI
Expansion Out/Half-Full Flag
Expansion IN
Write Enable
Read Enable
Reset
R
FL/RT
VCC
First Load/Retransmit
Power Supply
RS
EF
Empty Flag
GND
Ground
Signal Description
pointers to the first location. A reset is required after
power-up before a write operation can be enabled. Both
the Read Enable (R) and Write Enable (W) inputs must be
in the high state during the period shown in figure 1 (i.e.
Data In (I0 - I8)
Data inputs for 9-bit data
t
before the rising edge of RS) and should not change
RSS
Reset (RS)
until t
after the rising edge of RS. The Half-Full Flag
RSR
(HF) will be reset to high after Reset (RS).
Reset occurs whenever the Reset (RS) input is taken to a
low state. Reset returns both internal read and write
Figure 1. Reset.
Notes : 1. EF, FF and HF may change status during reset, but flags will be valid at t
.
RSC
2. W and R = V around the rising edge of RS.
IH
or equal to half of the total available memory in the
device. The Half-Full Flag (HF) is then reset by the rising
edge of the read operation.
Write Enable (W)
A write cycle is initiated on the falling edge of this input
if the Full Flag (FF) is not set. Data set-up and hold times
must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the
Ram array, regardless of any current read operation.
To prevent data overflow, the Full Flag (FF) will go low,
inhibiting further write operations. On completion of a
valid read operation, the Full Flag (FF) will go high after
TRFF, allowing a valid write to begin. When the FIFO
stack is full, the internal write pointer is blocked from W,
so that external changes to W will have no effect on the
full FIFO stack.
Once half of the memory is filled, and during the falling
edge of the next write operation, the Half-Full Flag (HF)
will be set to low and remain in this state until the
difference between the write and read pointers is less than
3
Rev. F – June 30, 1999
M67204E
Read Enable (R)
Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI )is
connected to GND to indicate an operation in the single
device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth
Expansion or Daisy Chain modes.
A read cycle is initiated on the falling edge of the Read
Enable (R) provided that the Empty Flag (EF) is not set.
The data is accessed on a first in/first out basis, not with
standing any current write operations. After Read Enable
(R) goes high, the Data Outputs (Q0 – Q8) will return to
a high impedance state until the next Read operation.
When all the data in the FIFO stack has been read, the
Empty Flag (EF) will go low, allowing the “final” read
cycle, but inhibiting further read operations whilst the
data outputs remain in a high impedance state. Once a
valid write operation has been completed, the Empty Flag
(EF) will go high after tWEF and a valid read may then
be initiated. When the FIFO stack is empty, the internal
read pointer is blocked from R, so that external changes
to R will have no effect on the empty FIFO stack.
Full Flag (FF)
The Full Flag (FF) will go low, inhibiting further write
operations when the write pointer is one location less than
the read pointer, indicating that the device is full. If the
read pointer is not moved after Reset (RS), the Full Flag
(FF) will go low after 4096 writes.
Empty Flag (EF)
The Empty Flag (EF) will go low, inhibiting further read
operations when the read pointer is equal to the write
pointer, indicating that the device is empty.
First Load/Retransmit (FL/RT)
Expansion Out/Half-full Flag (XO/HF)
This is a dual-purpose input. In the Depth Expansion
Mode, this pin is connected to ground to indicate that it
is the first loaded (see Operating Modes). In the Single
Device Mode, this pin acts as the retransmit input. The
Single Device Mode is initiated by connecting the
Expansion In (XI) to ground.
This is a dual-purpose output. In the single device mode,
when Expansion In (XI) is connected to ground, this
output acts as an indication of a half-full memory.
After half the memory is filled and on the falling edge of
the next write operation, the Half-Full Flag (HF) will be
set to low and will remain set until the difference between
the write and read pointers is less than or equal to half of
the total memory of the device. The Half-Full Flag (HF)
is then reset by the rising edge of the read operation.
The M67204E can be made to retransmit data when the
Retransmit Enable Control (RT) input is pulsed low. A
retransmit operation will set the internal read point to the
first location and will not affect the write pointer. Read
Enable (R) and Write Enable (W) must be in the high state
during retransmit. The retransmit feature is intended for
use when a number of writes equals to or less than the
depth of the FIFO have occured since the last RS cycle.
The retransmit feature is not compatible with the Depth
Expansion Mode and will affect the Half-Full Flag (HF),
in accordance with the relative locations of the read and
write pointers.
In the Depth Expansion Mode, Expansion In (XI) is
connected to Expansion Out (XO) of the previous device.
This output acts as a signal to the next device in the Daisy
Chain by providing a pulse to the next device when the
previous device reaches the last memory location.
Data Output (Q0 – Q8)
DATA output for 9-bit wide data. This data is in a high
impedance condition whenever Read (R) is in a high state.
4
Rev. F – June 30, 1999
M67204E
Functional Description
Operating Modes
in a Single Device Configuration when the Expansion In
(XI) control input is grounded (see Figure 2). In this mode
Single Device Mode
A single M67204E may be used when the application the Half-Full Flag (HF), which is an active low output, is
requirements are for 4096 words or less. The M67204E is shared with Expansion Out (XO).
Figure 2. Block Diagram of Single 4K × 9 FIFO.
HF
(HALF–FULL FLAG)
(W)
9
(R)
(Q)
READ
WRITE
9
DATA
DATA
OUT
IN
(I)
M
67204E
(EF)
(RT)
EMPTY FLAG
RETRANSMIT
FULL FLAG (FF)
(RS)
RESET
EXPANSION IN (XI)
Status flags (EF, FF and HF) can be detected from any
device. Figure 3 demonstrates an 18-bit word width by
Width Expansion Mode
Word width may be increased simply by connecting the using two M67204E. Any word width can be attained by
corresponding input control signals of multiple devices. adding additional M67204E.
Figure 3. Block Diagram of 4096 × 18 FIFO Memory Used in Width Expansion Mode.
HF
HF
18
9
9
DATA (I)
IN
(R) READ
(EF) EMPTY FLAG
(RT) RETRANSMIT
WRITE
(W)
M
M
FULL FLAG
RESET
(FF)
67204E
67204E
9
(RS)
9
XI
XI
18
(Q) DATA
OUT
Note : 3. Flag detection is accomplished by monitoring the FF, EF and the HF signals on either (any) device used in the width
expansion configuration. Do not connect any output control signals together.
5
Rev. F – June 30, 1999
M67204E
Table 1 : Reset and retransmit
Single Device Configuration/Width Expansion Mode
INPUTS
INTERNAL STATUS
Read Pointer Write Pointer
OUTPUTS
MODE
RS
0
RT
X
XI
0
EF
0
FF
1
HF
1
Reset
Location Zero
Location Zero
Location Zero
Unchanged
Retransmit
Read/Write
1
0
0
X
X
X
(4)
(4)
1
1
0
Increment
Increment
X
X
X
Note : 4. Pointer will increment if flag is high.
Table 2 : Reset and First Load Truth Table
Depth Expansion/Compound Expansion Mode
INPUTS
INTERNAL STATUS
OUTPUTS
MODE
RS
0
FL
0
XI
(5)
(5)
(5)
Read Pointer
Write Pointer
Location Zero
Location Zero
X
EF
FF
1
Reset First Device
Reset All Other Devices
Read/Write
Location Zero
Location Zero
X
0
0
0
1
1
1
X
X
X
Note : 5. XI is connected to XO of previous device.
See fig. 5.
Depth Expansion (Daisy Chain) Mode
Compound Expansion Module
It is quite simple to apply the two expansion techniques
described above together to create large FIFO arrays (see
figure 5).
The M67204E can be easily adapted for applications
which require more than 4096 words. Figure 4
demonstrates Depth Expansion using three M67204E.
Any depth can be achieved by adding additional
M67204E.
Bidirectional Mode
The M67204E operate in the Depth Expansion
configuration if the following conditions are met :
Applications which require data buffering between two
systems (each system being capable of Read and Write
operations) can be created by coupling M67204E as
shown in figure 6. Care must be taken to ensure that the
appropriate flag is monitored by each system (i.e. FF is
monitored on the device on which W is in use ; EF is
monitored on the device on which R is in use). Both Depth
Expansion and Width Expansion may be used in this
mode.
1. The first device must be designated by connecting the
First Load (FL) control input to ground.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be
connected to the Expansion In (XI) pin of the next
device. See figure 4.
4. External logic is needed to generate a composite Full
Flag (FF) and Empty Flag (EF). This requires that all
EF’s and all FFs be ØRed (i.e. all must be set to
generate the correct composite FF or EF). See figure 4.
Data Flow - Through Modes
Two types of flow-through modes are permitted : a read
5. The Retransmit (RT) function and Half-Full Flag (HF) flow-through and a write flow-through mode. In the read
are not available in the Depth Expansion Mode. flow-through mode (figure 17) the FIFO stack allows a
6
Rev. F – June 30, 1999
M67204E
single word to be read after one word has been written to In the write flow-through mode (figure 18), the FIFO
an empty FIFO stack. The data is enabled on the bus at stack allows a single word of data to be written
(tWEF + tA) ns after the leading edge of W which is immediately after a single word of data has been read
known as the first write edge and remains on the bus until from a full FIFO stack. The R line causes the FF to be
the R line is raised from low to high, after which the bus reset, but the W line, being low, causes it to be set again
will go into a three-state mode after tRHZ ns. The EF line in anticipation of a new data word. The new word is
will show a pulse indicating temporary reset and then will loaded into the FIFO stack on the leading edge of W. The
be set. In the interval in which R is low, more words may W line must be toggled when FF is not set in order to write
be written to the FIFO stack (the subsequent writes after new data into the FIFO stack and to increment the write
the first write edge will reset the Empty Flag) ; however, pointer.
the same word (written on the first write edge) presented
to the output bus as the read pointer will not be
incremented if R is low. On toggling R, the remaining
words written to the FIFO will appear on the output bus
in accordance with the read cycle timings.
Figure 4. Block Diagram of 12288 × 9 FIFO Memory (Depth expansion).
XO
W
R
FF
9
EF
FL
6
9
M
9
67204E
Q
V
CC
FULL
EMPTY
FF
9
EF
FL
M
67204E
EF
FL
FF
9
M
67204E
RS
XI
Figure 5. Compound FIFO Expansion.
Q
0
– Q
Q
Q
– Q
– Q
Q
Q
– Q
– Q
8
9
17
17
(N–8)
N
N
Q
0
– Q
8
9
(N–8)
M67204E
M67204E
DEPTH
EXPANSION
BLOCK
M67204E
R . W . RS
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
I
0
– I
I
9
– I
8
17
I
– I
N
(N–8)
I
0
– I
I
9
– I
I – I
(N–8) N
8
17
Notes : 6. For depth expansion block see section on Depth Expansion and Figure 4.
7. For Flag detection see section on Width Expansion and Figure 3.
7
Rev. F – June 30, 1999
M67204E
Figure 6. Bidirectional FIFO Mode.
R
B
W
A
M
EF
B
FF
A
HF
B
67204
I
Q
B 0–8
A 0–8
SYSTEM A
SYSTEM B
Q
A 0–8
I
B 0–8
M
67204
R
W
A
A
A
B
HF
EF
FF
B
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC – GND) . . . . . . . . . . . . . . . . . . – 0.3 V to 7.0 V
Input or Output voltage applied : . . . . (GND – 0.3 V) to (Vcc + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . – 65 °C to + 150 °C
OPERATING RANGE
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
Military
Vcc = 5 V ± 10 %
– 55 °C to + 125 °C
8
Rev. F – June 30, 1999
M67204E
DC Parameters
M M67204E
– 40
M M67204E
– 50
Parameter
Description
UNIT
VALUE
I
Operating
supply current
135
125
mA
mA
µA
Max
CCOP (8)
I
Standby
supply current
1.5
1.5
Max
Max
CCSB (9)
I
Power down
current
200
200
CCPD (10)
Notes : 8. Icc measurements are made with outputs open. F = F max
9. R = W = RS = FL/RT = VIH.
10. All input = Vcc.
PARAMETER
DESCRIPTION
M67204E
UNIT
µA
µA
V
VALUE
ILI (11)
Input leakage current
± 1
± 10
0.8
2.2
0.4
2.4
8
Max
Max
Max
Min
Max
Min
Max
Max
ILO (12)
Output leakage current
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input capacitance
Output capacitance
VIL (13)
VIH (13)
VOL (14)
VOH (14)
C IN (15)
C OUT (15)
V
V
V
pF
pF
8
Notes : 11. 0.4 ≤ Vin ≤ Vcc.
12. R = VIH, 0.4 ≤ VOUT ≤ VCC.
13. VIH max = Vcc + 0.3 V. VIL min = –0.3 V or –1 V pulse width 50 ns.
Figure 7. Output Load.
AC Test Conditions
5 V
Input pulse levels
Input rise/Fall times
Input timing reference levels
Output reference levels
Output load
: Gnd to 3.0 V
500 Ω
: 5 ns
TO
OUTPUT
PIN
: 1.5 V
: 1.5 V
: See figure 7
30 pF*
333 Ω
or equivalent circuit
* includes jig and scope capacitance
9
Rev. F – June 30, 1999
M67204E
M M67204E
– 40
M67204E
– 50
SYMBOL (16) SYMBOL (17)
PARAMETER (18) (22)
UNIT
MIN.
MAX.
MIN.
MAX.
READ CYCLE
TRLRL
tRC
Read cycle time
50
–
65
–
–
50
–
ns
ns
ns
ns
ns
ns
ns
ns
TRLQV
tA
Access time
–
10
40
5
40
–
TRHRL
tRR
Read recovery time
15
50
10
15
5
TRLRH
tRPW
tRLZ
tWLZ
tDV
Read pulse width (19)
Read low to data low Z (20)
Write low to data low Z (20, 21)
Data valid from read high
Read high to data high Z (20)
–
–
TRLQX
–
–
TWHQX
TRHQX
10
5
–
–
–
–
TRHQZ
tRHZ
–
25
–
30
WRITE CYCLE
TWLWL
tWC
tWPW
tWR
tDS
Write cycle time
Write pulse width (19)
Write recovery time
Data set-up time
Data hold time
50
40
10
20
0
–
–
–
–
–
65
50
15
30
0
–
–
–
–
–
ns
ns
ns
ns
ns
TWLWH
TWHWL
TDVWH
TWHDX
RESET CYCLE
TRSLWL
TRSLRSH
TWHRSH
TRSHWL
tDH
tRSC
tRS
Reset cycle time
50
40
40
10
–
–
–
–
65
50
50
15
–
–
–
–
ns
ns
ns
ns
Reset pulse width (19)
Reset set-up time
tRSS
tRSR
Reset recovery time
RETRANSMIT CYCLE
TRTLWL
TRTLRTH
TWHRTH
TRTHWL
FLAGS
tRTC
tRT
Retransmit cycle time
50
40
40
10
–
–
–
–
65
50
50
15
–
–
–
–
ns
ns
ns
ns
Retransmit pulse width (19)
Retransmit set-up time (20)
Retransmit recovery time
tRTS
tRTR
TRSLEFL
TRSLFFH
TRLEFL
TRHFFH
TEFHRH
TWHEFH
TWLFFL
TWLHFL
TRHHFH
TFFHWH
tEFL
Reset to EF low
–
–
50
50
30
35
–
–
–
60
60
45
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHFH, tFFH
tREF
Reset to HF/FF high
Read low to EF low
Read high to FF high
Read width after EF high
Write high to EF high
Write low to FF low
Write low to HF low
Read high to HF high
Write width after FF high
–
–
tRFF
–
–
tRPE
40
–
50
–
tWEF
tWFF
tWHF
tRHF
35
35
50
50
–
45
45
60
60
–
–
–
–
–
–
–
tWPF
40
50
10
Rev. F – June 30, 1999
M67204E
M M67204E
– 40
M67204E
– 50
SYMBOL (16) SYMBOL (17)
EXPANSION
PARAMETER (18) (22)
UNIT
MIN.
MAX.
MIN.
MAX.
PREVIEW
TWLXOL
TWHXOH
TXILXIH
TXIHXIL
TXILRL
tXOL
tXOH
tXI
Read/Write to XO low
–
40
40
–
–
50
50
–
ns
ns
ns
ns
ns
Read/Write to XO high
XI pulse width
–
–
40
10
10
50
10
15
tXIR
tXIS
XI recovery time
XI set-up time
–
–
–
–
Notes : 16. STD symbol.
17. ALT symbol.
18. Timings referenced as in ac test conditions.
19. Pulse widths less than minimam value are not allowed.
20. Values guaranteed by design, not currently tested.
21. Only applies to read data flow-through mode.
22. All parameters tested only.
Figure 8. Asynchronous Write and Read Operation.
11
Rev. F – June 30, 1999
M67204E
Figure 9. Full Flag from Last Write to First Read.
Figure 10. Empty Flag from Last Read to First Write.
Figure 11. Retransmit.
Notes : 23. EF, FF and HF may change status during Retransmit, but flags will be valid at t
.
RTC
12
Rev. F – June 30, 1999
M67204E
Figure 12. Empty Flag Timing
Figure 13. Full Flag Timing
Figure 14. Half-Full Flag Timing.
13
Rev. F – June 30, 1999
M67204E
Figure 15. Expansion Out.
Figure 16. Expansion In.
Figure 17. Read Data Flow – Through Mode.
14
Rev. F – June 30, 1999
M67204E
Figure 18. Write Data Flow – Through Mode.
Ordering Information
TEMPERATURE RANGE
PACKAGE
DP
DEVICE
67204EV
SPEED
40
FLOW
/883
M
M
M = 5 V version
40 ns
50 ns
blank
= MHS standards
/883
SB/SC
QM
= MIL STD 883 Class B or S
= SCC 9000 level B/C
= QML–Q
DP = 28 pin FP 400 mils
CP = Side brazed 28 pins 300 mils
0 = Dice form
SV
= QML–V
67204E = 4096 × 9 FIFO
EV = Very low power Rad Tolerant
M = Military
S = Space
–55° to +125°C
–55° to +125°C
* On request only
The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits
described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
15
Rev. F – June 30, 1999
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