SMCP-672061FV-15SB [TEMIC]
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28,;型号: | SMCP-672061FV-15SB |
厂家: | TEMIC SEMICONDUCTORS |
描述: | FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 先进先出芯片 CD |
文件: | 总22页 (文件大小:382K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• First-in first-out dual port memory
• 16384 x 9 organisation
• Fast Flag and access times: 15, 30 ns
• Wide temperature range: - 55 °C to + 125 °C
• Programmable Half Full Flag
• Fully expandable by word width or depth
• Asynchronous read/write operations
• Empty, full and half flags in single device mode
• Retransmit capability
• Bi-directional applications
• Battery back-up operation: 2V data retention
• TTL compatible
• Single 5V + 10% power supply
• QML Q and V with SMD 5962-93177
Rad Tolerant
High Speed
16 x 9
Description
The M672061F implements a first-in first-out algorithm, featuring asynchronous
read/write operations. The FULL and EMPTY flags prevent data overflow and under-
flow. The Expansion logic allows unlimited expansion in word size and depth with no
timing penalties. Twin address pointers automatically generate internal read and write
addresses, and no external address information are required for the Atmel FIFOs.
Address pointers are automatically incremented with the write pin and read pin. The 9
bits wide data are used in data communications applications where a parity bit for
error checking is necessary. The Retransmit pin resets the Read pointer to zero with-
out affecting the write pointer. This is very useful for retransmitting data when an error
is detected in the system.
Parallel FIFO +
Programmable
Flag
M672061F
Using an array of eight transistors (8 T) memory cell, the M672061F combines an
extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns
over the full temperature range. All versions offer battery backup data retention capa-
bility with a typical power consumption at less than 2 µW.
For military/space applications that demand superior levels of performance and reli-
ability the M672061F is processed according to the methods of the latest revision of
the MIL PRF 38535 (Q and V) or ESA SCC 9000.
Rev. E–20-Aug-01
1
M672061F
Interface
Block Diagram
Pin Configuration
2
Rev. E–20-Aug-01
Pin Names
NAMES
DESCRIPTION
I0-8
Q0-8
W
Inputs
Outputs
Write Enable
Read Enable
Reset
R
RS
EF
Empty Flag
Full Flag
FF
XO/HF
XI
Expansion Out/Half-Full Flag
Expansion IN
FL/RT
VCC
GND
First Load/Retransmit
Power Supply
Ground
3
M672061F
Rev. E–20-Aug-01
M672061F
Signal Description
Data In (I0 - I8)
Data inputs for 9 - bit data
Reset (RS)
Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both
internal read and write pointers to the first location. A reset is required after power-up
before a write operation can be enabled. Both the Read Enable (R) and Write Enable
(W) inputs must be in the high state during the period shown in Figure 2 (i.e. tRSS before
the rising edge of RS) and should not change until tRSR after the rising edge of RS.
Otherwise, pulse write (or read) low during the reset operation loads the Programmable
Half Full Flag register from the data Inputs I0-I8 (or data outputs Q0-Q8) (shown in fig-
ure 2). In these two cases the Full Flag and the Programmable Half Full Flag are
reseted to high and the Empty Flag to low.
Figure 1. Reset (no write to Programmable Half Full Flag register)
Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at tRSC
2. W and R = VIH around the rising edge of RS.
.
Figure 2. Reset (write (read) to Programmable Half Full Flag register)
Write Enable (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.
Data set-up and hold times must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any
current read operation.
4
Rev. E–20-Aug-01
Once half the memory is filled, and during the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to low and remain in this state until the difference
between the write and read pointers is less than or equal to half of the total available
memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the
read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-
tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,
allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is
blocked from W, so that external changes to W will have no effect on the full FIFO stack.
Read Enable (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided that the
Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including
any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0 -
Q8) will return to a high impedance state until the next Read operation. When all the
data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the
“final” read cycle, but inhibiting further read operations while the data outputs remain in
a high impedance state. Once a valid write operation has been completed, the Empty
Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO
stack is empty, the internal read pointer is blocked from R, so that external changes to R
will have no effect on the empty FIFO stack.
First Load/Retransmit
(FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to
ground to indicate that it is the first loaded (see Operating Modes). In the Single Device
Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-
necting the Expansion In (XI) to ground.
The M672061F can be set to retransmit data when the Retransmit Enable Control (RT)
input is pulsed low. A retransmit operation will set the internal read point to the first loca-
tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be
in the high state during retransmit. The retransmit feature is intended for use when a
number of writes are equal to or less than the depth of the FIFO has occured since the
last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (HF), in accordance with the relative locations of the
read and write pointers.
Expansion In (XI)
Full Flag (FF)
This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an
operation in the single device mode. Expansion In (XI) is connected to Expansion Out
(XO) of the previous device in the Depth Expansion or Daisy Chain modes.
The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is
one location less than the read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.
Empty Flag (EF)
The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer
is equal to the write pointer, indicating that the device is empty.
Expansion Out/Half-Full
Flag (XO/HF)
This is a dual-purpose output. In the single device mode, when Expansion In (XI) is con-
nected to ground, this output acts as an indication of a half-full memory.
The M672061F offers a variable offset for the Half Full condition. The offset is loaded
into a register during a reset cycle. When RS is low, the Programmable Half Full Flag
(PHF) can be loaded from the DATA inputs I0-I8 by pulsing W low or from the DATA out-
5
M672061F
Rev. E–20-Aug-01
M672061F
puts Q0-Q8 by pulsing R low. The offset options are listed in table 1. If PHF is not loaded
during the reset cycle, the default offset will be the half of the total memory of the device.
The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the
difference between the write and read pointers is less than or equal to the Programma-
ble offset (if the Half Full Flag register has been loaded during the reset cycle) or the half
of the total memory (if the Half Full register has not been loaded during the reset cycle).
After half the memory is filled and on the falling edge of the next write operation, the
Half-Full Flag (HF) will be set to low and will remain set until the difference between the
write and read pointers is less than or equal to half of the total memory of the device.
The Half-Full Flag (HF) is then reset by the rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of
the previous device. This output acts as a signal to the next device in the Daisy Chain by
providing a pulse to the next device when the previous device reaches the last memory
location.
Data Output (Q0 - Q8)
DATA output for 9-bit wide data. This data is in a high impedance condition whenever
Read (R) is in a high state.
6
Rev. E–20-Aug-01
Functional Description
Operating Modes
Single Device Mode
A single M672061F may be used when the application requirements are for 16384
words or less. The M672061F is in a Single Device Configuration when the Expansion In (XI)
control input is grounded (see Figure 3.). In this mode the Half-Full Flag (HF), which is an active
low output, is shared with Expansion Out (XO).
Figure 3. Block Diagram of Single 16384 × 9
HF
(HALF-FULL FLAG)
(W)
(R)
(Q)
READ
WRITE
HF
9
9
DATAOUT
DATAIN
(I)
(EF)
(RT)
EMPTY FLAG
RETRANSMIT
FULL FLAG (FF)
(RS)
RESET
EXPANSIONIN(XI)
M672061F
Width Expansion Mode
Word width may be increased simply by connecting the corresponding input control sig-
nals of multiple devices. Status flags (EF, FF and HF) can be detected from any device.
Figure 4 demonstrates an 18-bit word width by using two M672061F. Any word width can be
attained by adding additional M672061F.
Figure 4. Block Diagram of 16384 X 18 FIFO Memory Used in Width Expansion Mode
Note:
Flag detection is accomplished by monitoring the FF, EF and the HF signals on either
(any) device used in the width expansion configuration. Do not connect any output con-
trol signals together.
7
M672061F
Rev. E–20-Aug-01
M672061F
Table 1. Programmable Half Full Flag Offset
I8
0
I7
0
0
0
I6
0
0
0
I5
0
0
0
I4
0
0
0
I3
0
0
0
I2
0
0
0
I1
0
0
1
I0
0
1
0
OFFSET
0
0
32
64
0
...
8192 (Half Full)
Default Offset
1
0
0
0
0
0
0
0
0
...
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
16384-64
16384-32
1
Table 2. Reset and retransmit
Single Device Configuration/Width Expansion Mode
MODE
INPUTS
INTERNAL STATUS
Read Pointer Write Pointer
Location Zero
OUTPUTS
RS
0
RT
X
XI
0
EF
0
FF
1
HF
1
Reset
Location Zero
Location Zero
Increment (1)
Retransmit
Read/Write
1
0
0
Unchanged
Increment(1)
X
X
X
1
1
0
X
X
X
1.
Pointer will increment if flag is high.
Table 3. Reset and First Load Truth Table
Depth Expansion/Compound Expansion Mode
MODE
INPUTS
INTERNAL STATUS
Read Pointer Write Pointer
Location Zero Location Zero
OUTPUTS
RS
0
FL
0
XI
EF
0
FF
(1)
Reset First Device
Reset All Other Devices
Read/Write
1
1
X
(1)
(1)
0
1
Location Zero
X
Location Zero
X
0
1
X
X
1.
XI is connected to XO of previous device.
See Figure 5
8
Rev. E–20-Aug-01
Depth Expansion (Daisy The M672061F can be easily adapted for applications which require more than 16384
words. Figure 5 demonstrates Depth Expansion using three M672061F. Any depth can
be achieved by adding additional 672061F.
Chain) Mode
The M672061F operates in the Depth Expansion configuration if the following conditions
are met:
1. The first device must be designated by connecting the First Load (FL) control
input to ground.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be connected to the Expansion In
(XI) pin of the next device. See Figure 5
4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag
(EF). This requires that all EF’s and all FFs be ØRed (i.e. all must be set to generate the
correct composite FF or EF). See Figure 5
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth
Expansion Mode.
Compound Expansion
Module
It is quite simple to apply the two expansion techniques described above together to cre-
ate large FIFO arrays (see Figure 6).
Bidirectional Mode
Applications which require data buffering between two systems (each system being
capable of Read and Write operations) can be created by coupling M672061F as shown
in Figure 7 Care must be taken to ensure that the appropriate flag is monitored by each
system (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device
on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.
Data Flow - Through
Modes
Two types of flow-through modes are permitted : a read flow-through and a write flow-
through mode. In the read flow-through mode (Figure 18) the FIFO stack allows a single
word to be read after one word has been written to an empty FIFO stack. The data is
enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the
first write edge and remains on the bus until the R line is raised from low to high, after which the
bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating tem-
porary reset and then will be set. In the interval in which R is low, more words may be written to
the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag) ; how-
ever, the same word (written on the first write edge) presented to the output bus as the read
pointer will not be incremented if R is low. On toggling R, the remaining words written to the
FIFO will appear on the output bus in accordance with the read cycle timings.
In the write flow-through mode (Figure 19), the FIFO stack allows a single word of data
to be written immediately after a single word of data has been read from a full FIFO
stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again
in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading
edge of W. The W line must be toggled when FF is not set in order to write new data into the
FIFO stack and to increment the write pointer.
9
M672061F
Rev. E–20-Aug-01
M672061F
Figure 5. Block Diagram of 49152 x 9 FIFO Memory (Depth Expansion)
Figure 6. Compound FIFO Expansion
Notes: 1. For depth expansion block see section on Depth Expansion and Figure 4.
2. For Flag detection see section on Width Expansion and Figure 3
Figure 7. Bidirectional FIFO Mode
10
Rev. E–20-Aug-01
11
M672061F
Rev. E–20-Aug-01
M672061F
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC - GND):..................... 0.3V to 7.0V
Input or Output voltage applied: ................(GND - 0.3V) to (Vcc + 0.3V)
Storage temperature: ................................- 65 °C to + 150 °C
OPERATING RANGE
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
Military
Vcc = 5V ± 10%
– 55 °C to + 125°C
DC Parameters
Parameter
Description
M672061F-30
M672061F-15
UNIT
VALUE
Max
(1)
ICCOP
Operating supply current
Standby supply current
Power down current
110
5
120
5
mA
mA
µA
(2)
ICCSB
Max
(3)
ICCPD
400
400
Max
1.
2.
3.
Icc measurements are made with outputs open.
R = W = RS = FL/RT = VIH.
All input = Vcc.
PARAMETER
DESCRIPTION
Input leakage current
M672061F
UNIT
µA
µA
V
VALUE
(1)
ILI
± 1
± 1
0.8
2.2
0.4
2.4
8
Max
Max
Max
Min
(2)
ILO
Output leakage current
Input low voltage
(3)
VIL
VIH (3)
Input high voltage
Output low voltage
Output high voltage
Input capacitance
Output capacitance
V
(4)
VOL
V
Max
Min
VOH (4)
V
(5)
C IN
pF
pF
Max
Max
C OUT (5)
8
1.
2.
3.
4.
5.
0.4 ≤ Vin ≤ Vcc.
R = VIH, 0.4 ≤ VOUT ≤ VCC.
VIH max = Vcc + 0.3 V. VIL min = -0.3 V or -1 V pulse width 50 ns. For XI input, VIH= 2.8V
Vcc min, IOL = 8 mA, IOH = -2 mA
Guaranteed but not tested.
12
Rev. E–20-Aug-01
AC Test Conditions
Input pulse levels:
................................Gnd to 3.0V
Input rise/Fall times: ................................5 ns
Input timing reference levels: .....................1.5V
Output reference levels: .............................1.5V
Output load:
................................See Figure 8.
Figure 8. Output Load
13
M672061F
Rev. E–20-Aug-01
M672061F
M672061F- 30
M672061F- 15
(1)
(2)
(3) (4)
SYMBOL
SYMBOL
PARAMETER
UNIT
Min
Max
Min
Max
READ CYCLE
TRLRL
READ CYCLE
tRC
tA
Read cycle time
40
-
-
30
-
25
-
-
15
-
ns
ns
ns
ns
ns
ns
ns
ns
TRLQV
Access time
TRHRL
tRR
Read recovery time
10
30
5
10
15
0
(5)
TRLRH
tRPW
tRLZ
tWLZ
tDV
Read pulse width
-
-
(6)
TRLQX
Read low to data low Z
-
-
TWHQX
Write low to data low Z (6) (7)
Data valid from read high
Read high to data high Z (6)
5
-
3
-
TRHQX
5
-
5
-
TRHQZ
tRHZ
-
20
-
15
WRITE CYCLE
TWLWL
WRITE CYCLE
tWC
tWPW
tWR
tDS
Write cycle time
Write pulse width (5)
Write recovery time
Data set-up time
Data hold time
40
-
-
-
-
-
25
15
10
9
-
-
-
-
-
ns
ns
ns
ns
ns
TWLWH
30
TWHWL
10
TDVWH
18
TWHDX
tDH
0
0
RESET CYCLE
TRSLWL
TRSLRSH
TWHRSH
TRSHWL
RESET CYCLE
tRSC
tRS
Reset cycle time
40
30
30
10
-
-
-
-
25
15
20
10
-
-
-
-
ns
ns
ns
ns
Reset pulse width (5)
Reset set-up time
Reset recovery time
tRSS
tRSR
RETRANSMIT CYCLE
TRTLWL
RETRANSMIT CYCLE
tRTC
tRT
Retransmit cycle time
40
30
30
10
-
-
-
-
25
15
15
10
-
-
-
-
ns
ns
ns
ns
TRTLRTH
Retransmit pulse width (5)
Retransmit set-up time (6)
Retransmit recovery time
TWHRTH
tRTS
tRTR
TRTHWL
14
Rev. E–20-Aug-01
M672061F
FLAGS
TRSLEFL
FLAGS
tEFL
tHFH, tFFH
tREF
Reset to EF low
-
30
30
30
30
-
-
-
25
25
15
25
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TRSLFFH
TRLEFL
Reset to HF/FF high
Read low to EF low
Read high to FF high
Read width after EF high
Write high to EF high
Write low to FF low
Write low to HF low
Read high to HF high
Write width after FF high
-
-
-
TRHFFH
TEFHRH
TWHEFH
TWLFFL
TWLHFL
TRHHFH
TFFHWH
EXPANSION
TWLXOL
TWHXOH
TXILXIH
tRFF
-
-
tRPE
30
15
-
tWEF
-
30
30
30
30
-
15
20
30
30
-
tWFF
-
-
tWHF
tRHF
-
-
-
-
tWPF
30
15
EXPANSION
tXOL
tXOH
tXI
Read/Write to XO low
Read/Write to XO high
XI pulse width
-
30
30
-
-
15
15
-
ns
ns
ns
ns
ns
-
-
30
10
10
15
10
10
TXIHXIL
tXIR
tXIS
XI recovery time
XI set-up time
-
-
TXILRL
-
-
1.
STD symbol.
ALT symbol.
Timings referenced as in ac test conditions.
All parameters tested only.
Pulse widths less than minimum value are not allowed.
Values guaranteed by design, not currently tested.
Only applies to read data flow-through mode.
2.
3.
4.
5.
6.
7.
15
Rev. E–20-Aug-01
M672061F
Figure 9. Asynchronous Write and Read Operation
Figure 10. Full Flag from Last Write to First Read
16
Rev. E–20-Aug-01
M672061F
Figure 11. Empty Flag from Last Read to First Write
Figure 12. Retransmit
Note:
EF, FF and PHF may change status during Retransmit, but flags will be valid at tRTC
Figure 13. Empty Flag Timing
W
tWEF
EF
R
tRPE
17
Rev. E–20-Aug-01
M672061F
Figure 14. Full Flag Timing
Figure 15. Programmable Half-Full Flag Timing
Figure 16. Expansion Out
18
Rev. E–20-Aug-01
Figure 17. Expansion In
Figure 18. Read Data Flow - Through Mode
Figure 19. Write Data Flow - Through Modes
19
M672061F
Rev. E–20-Aug-01
M672061F
20
Rev. E–20-Aug-01
Ordering Information
Reference Number
MMCP-672061FV-15-E(*)
MMCP-672061FV-15
MMCP-672061FV-30
SMCP-672061FV-15SB
SMCP-672061FV-30SB
SMCP-672061FV-15SC
SMCP-672061FV-30SC
MMCP-672061FV-15/883(*)
MMCP-672061FV-30/883(*)
SMCP-672061FV-15/883(*)
SMCP-672061FV-30/883(*)
5962-9317706QUC
Temperature Range
25°C
Speed
15ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
30ns
15ns
15ns
15ns
Package
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
SB28.3
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
FP28.4
Die
Quality Flow
Engineering Samples
Mil.
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
25°C
Mil.
SCC B
SCC B
SCC C
SCC C
MIL-883 B
MIL-883 B
MIL-883 S
MIL-883 S
QML Q
5962-9317705QUC
QML Q
5962-9317706VUC
QML V
5962-9317705VUC
QML V
MMDP-672061FV-15-E
MMDP-672061FV-15
MMDP-672061FV-30
SMDP-672061FV-15SB
SMDP-672061FV-30SB
SMDP-672061FV-15SC
SMDP-672061FV-30SC
MMDP-672061FV-15/883(*)
MMDP-672061FV-30/883(*)
SMDP-672061FV-15/883(*)
SMDP-672061FV-30/883(*)
5962-9317706QZC
Engineering Samples
Mil.
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
25°C
Mil.
SCC B
SCC B
SCC C
SCC C
MIL-883 B
MIL-883 B
MIL-883 S
MIL-883 S
QML Q
5962-9317705QZC
QML Q
5962-9317706VZC
QML V
5962-9317705VZC
QML V
MM0-672061FV-15-E
5962-9317706Q9A
Engineering Samples
QML Q
-55 to +125°C
-55 to +125°C
Die
5962-9317706V9A
Die
QML V
Note:
(*)contact factory
21
M672061F
Rev. E–20-Aug-01
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