SMDJ-65609EV-70/883 [TEMIC]
Standard SRAM, 128KX8, 70ns, CMOS, 0.400 INCH, FP-32;
| 型号： | SMDJ-65609EV-70/883 |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Standard SRAM, 128KX8, 70ns, CMOS, 0.400 INCH, FP-32 静态存储器 |
| 文件： | 总9页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M65609E
128 K ꢀ 8 Very Low Power CMOS SRAM Rad Tolerant
Introduction
The M65609E is a very low power CMOS static RAM
organized as 131072 × 8 bits.
access time at 35 ns over the full military temperature
range. The high stability of the 6T cell provides
excellent protection against soft errors due to noise.
Atmel Wireless & Microcontrollers brings the solution
to applications where fast computing is as mandatory as
low consumption, such as aerospace electronics,
portable instruments, or embarked systems.
The M65609E is processed according to the methods of
the latest revision of the MIL STD 883 (class B or S),
ESA SCC 9000 or QML.
Utilizing an array of six transistors (6T) memory cells,
the M65609E combines an extremely low standby
supply current (Typical value = 20 µA) with a fast
It is produced on the same process as the MH1RT sea of
gates series.
Features
D Operating voltage: 3.3 V
D Access time: 35, 70 ns
D 400 Mils width package
D TTL compatible inputs and outputs
D Asynchronous
D Very low power consumption
active : 200 mW (Max)
D Designed on 0.35 micron process
D Latch up immune
standby : 70 µW (Typ)
data retention: 50 µW (typ)
D Wide temperature Range : –55 To +125°C
D 200 Krads capability
D SEU LET better than 3 MeV
Interface
Block Diagram
9
10
Rev. B – February 5, 2001
1
Preliminary
M65609E
Pin Configuration
Pin Names
Truth Table
A0–A16
Address inputs
Data Input/Output
Chip select 1
Chip select 2
Write Enable
Output Enable
Power
INPUTS/
OUTPUTS
CS1 CS2
W
OE
MODE
I/O0–I/O7
H
X
X
L
X
X
X
Z
Z
Deselect/
Power-down
CS
1
CS
2
W
X
Deselect/
Power Down
L
L
L
H
H
H
H
L
L
X
H
Data Out
Data In
Z
Read
Write
OE
V
CC
H
Output Disable
GND
Ground
L = low, H = high, X = H or L, Z = high impedance.
32 pins Flatpack
400 MILS
A5
VCC
A4
A16
I/03
A15
A12
I/04
A13
A14
A9
I/02
A7
I/01
A3
A6
A8
A0
A10
I/08
A11
OE
A1
CS2
I/05
A2
I/07
GND
CSI
W
I/06
GND
Rev. B – February 5, 2001
2
Preliminary
M65609E
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . . - 0.5 V + 5 V
DC input voltage : . . . . . . . . . . . . . . . . . GND – 0,3 V to VCC + 0,3
DC output voltage high Z state : . . . . . . GND – 0,3 V to VCC + 0,3
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . –65 °C to + 150 °C
Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . 20 mA
Electro statics discharge voltage : . . . . . . . . . . . . . . . . . . . > 2 001 V
(MIL STD 883D method 3015.3)
Operating Range
OPERATING VOLTAGE
OPERATING TEMPERATURE
Military
3.3 V ± 10 %
– 55 _C to + 125 _C
Recommended DC Operating Conditions
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
Vcc
Supply voltage
3
0.0
3.3
0.0
0.0
–
3.6
0.0
0.8
V
V
V
V
Gnd
VIL
VIH
Ground
Input low voltage
Input high voltage
GND – 0.3
2.2
V
+ 0.3
CC
Capacitance
PARAMETER
Cin (1)
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
pF
Input low voltage
Output high volt
–
–
–
–
8
8
Cout (1)
pF
Note :
1. Guaranteed but not tested.
DC Parameters
PARAMETER
IIX (2)
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
µA
Input leakage current
Output leakage current
Output low voltage
Output high voltage
– 1
– 1
–
–
–
–
–
1
1
IOZ (2)
µA
VOL (3)
0.4
–
V
VOH (4)
2.4
Notes : 2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output Disabled.
3. Vcc min. IOL = 1 mA.
4. Vcc min. IOH = 0.5 mA.
Rev. B – February 5, 2001
3
Preliminary
M65609E
Consumption
65609E
– 35
SYMBOL
DESCRIPTION
UNIT
VALUE
ICCSB (5)
Standby supply current
2.5
2
mA
mA
mA
max
max
max
ICCSB (6)
Standby supply current
1
ICCOP (7)
Dynamic operating current
65
Notes : 5. CS ≥ VIH or CS ≤ VIL and CS ≤ VIL.
1
2
1
6. CS ≥ Vcc – 0.3 V or, CS < Gnd + 0.3 V and CS ≤ 0.2 V
1
2
1
7. F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = Gnd/Vcc, Vcc max.
Rev. B – February 5, 2001
4
Preliminary
M65609E
Write Cycle
65609E
– 35
SYMBOL
PARAMETER
UNIT
VALUE
TAVAW
TAVWL
TAVWH
TDVWH
Write cycle time
35
10
28
23
28
28
15
28
+3
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
min
min
min
min
min
min
max
min
min
min
min
Address set-up time
Address valid to end of write
Data set-up time
TE LWH
1
CS low to write end
1
TE HWH
2
CS high to write end
2
TWLQZ
TWLWH
TWHAX
TWHDX
TWHQX
Write low to high Z (11)
Write pulse width
Address hold from to end of write
Data hold time
Write high to low Z (11)
0
Read Cycle
65609E
– 35
SYMBOL
PARAMETER
UNIT
VALUE
TAVAV
TAVQV
TAVQX
Read cycle time
35
35
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
min
max
min
max
min
max
max
min
max
max
min
max
Address access time
Address valid to low Z
TE LQV
1
Chip-select access time
35
3
1
TE LQX
1
CS low to low Z (11)
1
TE HQZ
1
CS high to high Z (11)
1
20
35
3
TE HQV
2
Chip-select access time
2
TE HQX
2
CS high to low Z (11)
2
TE LQZ
2
CS low to high Z (11)
2
20
12
0
TGLQV
TGLQX
TGHQZ
Output Enable access time
OE low to low Z (11)
OE high to high Z (11)
10
Notes : 11. Parameters guaranteed, not tested, with output loading 5 pF. (see fig. 1.b.).
Rev. B – February 5, 2001
5
Preliminary
M65609E
Write Cycle 1. W Controlled. OE High During Write
TAVAW
Write Cycle 2. W Controlled. OE Low
TAVAW
Rev. B – February 5, 2001
6
Preliminary
M65609E
Write Cycle 3. CS1 or CS2 Controlled.
TAVAW
Note : 12. The internal write time of the memory is defined by the overlap of CS Low and CS HIGH and W LOW. Both signals must be
1
2
actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be
referenced to the actived edge of the signal that terminates the write.
Data out is high impedance if OE = VIH.
Rev. B – February 5, 2001
7
Preliminary
M65609E
Read Cycle nb 1
Read Cycle nb 2
Read Cycle nb 3
Rev. B – February 5, 2001
8
Preliminary
M65609E
Ordering Information
TEMPERATURE RANGE
PACKAGE
DEVICE
GRADE
SPEED
FLOW*
S
M
DJ
– 65609E
V
– 35
/883
M = Military
S = Space
–55° to +125°C
–55° to +125°C
V = Very low power
35 ns
70 ns
DJ = Flat Package 32 pins 400 mils
0 =
die
blank
/883
SB/SC
= MHS standards
= MIL-STD 883 Class B or S
= SCC 9000 level B/C
128K × 8
STATIC RAM
* For ordering in QML quality level, use the QML PIN according to SMD number (to be defined).
The information contained herein is subject to change without notice. No responsibility is assumed by Atmel Wireless & Microcontrollers for using this
publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
Rev. B – February 5, 2001
9
Preliminary
相关型号：
SMDJ10
Trans Voltage Suppressor Diode, 3000W, 10V V(RWM), Unidirectional, 1 Element, Silicon, DO-214AB, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, SMC, 2 PIN
LITTELFUSE
SMDJ10
Trans Voltage Suppressor Diode, 3000W, 10V V(RWM), Unidirectional, 1 Element, Silicon, DO-214AB
PROTEC
SMDJ100
Trans Voltage Suppressor Diode, 3000W, 100V V(RWM), Unidirectional, 1 Element, Silicon, DO-214AB
PROTEC
©2020 ICPDF网 联系我们和版权申明