T6818-TBQ [TEMIC]
Peripheral Driver,;型号: | T6818-TBQ |
厂家: | TEMIC SEMICONDUCTORS |
描述: | Peripheral Driver, |
文件: | 总16页 (文件大小:121K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• Supply voltage up to 40 V
• RDSon typ. 0.5 Ω @ 25°C, max. 1 Ω @ 150°C
• Up to 1.5 A output current
• Three half-bridge outputs formed by three high-side and three low-side drivers
• Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors
and inductors
• No crossover current
• Very low quiescent current Is < 10 µA in stand-by mode vs. total temperature range
• Outputs short-circuit protected
• Overtemperature protection for each switch and overtemperature prewarning
• Undervoltage protection
• Various diagnosis functions such as shorted output, open load, overtemperature and
power-supply fail
• Serial data interface, daisy chain capable, up to 2 MHz clock frequency
• SO14 power package
Triple Half
Bridge DMOS
Output Driver
with Serial Input
Control
Description
T6818 / T6828 are fully protected driver interfaces designed in 0.8-µm BCDMOS
technology. It is used to control up to 3 different loads by a microcontroller in auto-
motive and industrial applications.
T6818
T6828
Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A.
The drivers are internally connected to form 3 half-bridges and can be controlled sep-
arately from a standard serial data interface. Therefore all kinds of loads such as
bulbs, resistors, capacitors and inductors can be combined. The IC design especially
supports the applications of H-bridges to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature
and undervoltage. Various diagnosis functions and a very low quiescent current in
stand-by-mode opens a wide range of applications. Automotive qualification referring
to conducted interferences, EMC protection and 2 kV ESD protection gives added
value and enhanced quality for demanding up-market applications.
Ordering Information
Extended Type Number
Package
SO14
Remarks
Power package, tubed
T6818-TBS
T6818-TBQ
SO14
Power package with head slug, taped and
reeled
T6828-TBS
T6828-TBQ
SO14
SO14
Power package, tubed
Power package with head slug, taped and
reeled
Rev. A1, 07-Nov-01
1 (16)
Preliminary Information
Preliminary Information
Block Diagram
Figure 1.
O
C
S
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
n. n.
u. u.
n. n. n. n. n. n.
u. u. u. u. u. u.
3
VS
Input register
Output register
Serial interface
Charge
pump
n. n. n. n. n. n.
u. u. u. u. u. u.
DI
P
S
F
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
O
P
L
5
6
CLK
CS
UV
4
protection
Fault
Fault
Fault
detect
detect
detect
11
1
INH
VCC
10
Control
logic
Power-on
reset
DO
GND
GND
GND
GND
9
7
8
Fault
Fault
Fault
detect
detect
detect
Thermal
protection
14
2
12
OUT2
13
OUT1
OUT3
2 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Pin Configuration
Figure 2.
GND
OUT3
VS
1
2
3
4
5
6
7
14 GND
13 OUT1
12 OUT2
11 VCC
10 INH
CS
DI
CLK
GND
9
8
DO
GND
Pin Description
Pin
Symbol
Function
T6818: Ground; reference potential; internal connection to Pin 7, 8 and 14; cooling tab
T6828: Additional connection to heat slug
1
GND
Half bridge-output 3; formed by internally connected Power-MOS high-side switch 3 and low-side switch
3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short
and open load
2
OUT3
3
4
VS
CS
Power supply for output stages OUT1, OUT2 and OUT3, internal supply
Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
5
6
DI
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
CLK
7
8
GND
GND
Ground; see Pin 1
Ground; see Pin 1
Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit
status information to the µC (LSB is transferred first); output will remain tristated, unless device is
selected by CS = low, therefore, several ICs can operate on one data output line only.
9
DO
Inhibit input; 5-V logic input with internal pull down; low = stand-by,
high = normal operating
10
INH
11
12
13
14
VCC
OUT2
OUT1
GND
Logic supply voltage (5V)
Half bridge-output 2; see Pin 2
Half bridge-output 1; see Pin 2
Ground; see Pin 1
3 (16)
Preliminary Information
Rev. A1, 07-Nov-01
Preliminary Information
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-
chronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,
SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Figure 3. Data transfer
CS
DI
SRR
0
LS1
HS1
2
LS2
HS2
4
LS3
HS3
6
n. u.
7
n. u.
8
n. u.
9
n. u.
n. u.
n. u.
n. u.
n. u.
OCS
13
1
3
5
10
11
12
14
15
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
SCD
OPL
PSF
Input Data Protocol
Bit
Input Register
Function
Status register reset (high = reset; the bits PSF, OPL and SCD in
the output data register are set to low)
0
SRR
1
2
LS1
HS1
LS2
HS2
LS3
HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OCS
n. u.
n. u.
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
Not used
8
Not used
9
Not used
10
11
12
13
14
15
Not used
Not used
Not used
Overcurrent shutdown (high = overcurrent shutdown is active)
Not used
Not used
4 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Output Data Protocol
Output (Status)
Bit
Register
Function
0
TP
Temperature prewarning: high = warning
1
2
Status LS1
Status HS1
Status LS2
Status HS2
Status LS3
Status HS3
n. u.
high = output is on, low = output is off; not affected by SRR
high = output is on, low = output is off; not affected by SRR
3
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
4
5
6
7
8
n. u.
Not used
9
n. u.
Not used
10
11
12
n. u.
Not used
n. u.
Not used
n. u.
Not used
Short circuit detected: set high, when at least one high-side or
low-side switch is switched off by a short circuit condition. Bits 1
to 6 can be used to detect the shorted switch.
13
SCD
Open load detected: set high, when at least one active high side-
or low side-switch sinks/sources a current below the open load
threshold current.
14
15
OPL
PSF
Power-supply fail: undervoltage at Pin VS detected
After power-on reset, the input register has the following status
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(OCS)
(HS3)
(LS3)
(HS2)
(LS2)
(HS1)
(LS1)
(SRR)
x
x
H
x
x
x
x
x
x
L
L
L
L
L
L
L
Power-Supply Fail
In case of undervoltage at Pin VS the Power-Supply Fail bit (PSF) in the output register
is set and all outputs are disabled. An undervoltage condition is only detected if it
occurs over the undervoltage detection delay time tdUV. After the undervoltage occurred
the outputs are enabled immediately. The PSF bit keeps high until it is reset by the SRR
bit in the input register.
Open-Load Detection
If the current through a high side or low side switch in ON-state does not reach the open
load detection threshold, the open load detection bit (OPL) in the output register is set.
The OPL bit keeps high until it is reset by the SRR bit in the input register. An open load
condition is only detected if it occurs over the open load detection delay time tdSd
.
Overtemperature
Protection
If the junction temperature at one or more switches exceeds the thermal prewarning
threshold TjPW set, the temperature prewarning bit (TP) in the output register is set. When
5 (16)
Preliminary Information
Rev. A1, 07-Nov-01
Preliminary Information
temperature falls below the thermal prewarning threshold TjPW reset, the bit TP is reset.
The TP bit can be read without transferring a complete 16-bit data word: with CS = high
to low the state of TP appears at Pin DO. After the µC has read this information CS is
set high and the data transfer is interrupted without affecting the state of input and out-
put registers.
If the junction temperature at one or more switches exceeds the thermal shutdown
threshold Tj switch off, all outputs are disabled and the corresponding bits in the output reg-
ister are set to low. The outputs can be enabled again when the temperature falls below
the thermal shutdown threshold Tjswitchon and writing a high to the SRR bit in the input
register. Thermal prewarning and shutdown threshold have hysteresis.
Short-Circuit Protection
The output currents are limited by a current regulator. If the overcurrent shutdown bit
(OCS) in the input register is set, the concerned output is switched off after a short
delay time (tdSd) when the current exceeds the overcurrent limitation and shutdown
threshold. In this case the short-circuit detection bit (SCD) is set and the corresponding
status bit in the output register is set to low. For OCS = low the overcurrent shutdown is
inactive. In this case the SCD bit is set also if the current exceeds the overcurrent limita-
tion and shutdown threshold, but the outputs are not affected. By writing a high to the
SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled.
Inhibit
To inhibit the T6818 / T6828, switch Pin 10 (INH) to 0 V.
In this case all output switches are turned off and the data in the output register are
deleted. The current consumption is reduced to less than 10 µA out of VS and less than
20 µA out of VCC. The outputs are switched to tristate. The output switches can be acti-
vated again by switching Pin 10 (INH) to 5 V which initiates an internal power-on reset.
6 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Absolute Maximum Ratings
All values refer to GND pins
Parameter
Symbol
VVS
Value
-0.3 to 40
-1
Unit
V
Supply voltage
Pin 3
Pin 3
Pin 11
Supply voltage t<0.5s; IS>-2A
Logic supply voltage
VVS
V
VVCC
-0.3 to 7
V
VCS,VDI, VCLK
VINH
,
Logic input voltage
Pins 4 to 6, 10
-0.3 to VVCC+0.3
V
Logic output voltage
Input current
Pin 9
VDO
-0.3 to VVCC+0.3
-10 to +10
V
Pins 4 to 6, 10
Pin 9
ICS,IDI, ICLK, IINH
IDO
mA
mA
Output current
-10 to +10
Internal limited, see
output specification
Pins 2, 12 and
13
Output current
IOut3, IOut2, IOut1
Pins 2, 12 and
13towards Pin
3
Reverse conducting current
(tpulse = 150 µs)
IOut3, IOut2, IOut1
17
A
Junction-temperature range
Storage-temperature range
TJ
-40 to 150
-55 to 150
°C
°C
TSTG
Thermal Resistance
Parameter
Test Conditions
Symbol
Value
Unit
T6818
Measured to GND
Pins 1, 7, 8, 14
Junction – pin
RthJP
RthJA
30
65
K/W
K/W
Junction – ambient
T6828
Measured to heat slug, GND
Pins 1, 7, 8, 14
Junction – pin
RthJP
RthJA
5
K/W
K/W
Junction – ambient
30
Operating Range
Parameter
Symbol
VVS
Value
VUV 1) to 40
4.75 to 5.25
-0.3 to VVCC
2
Unit
V
Supply voltage
Logic supply voltage
VVCC
V
Logic input voltage
VCS,VDI, VCLK,V
V
INH
Serial interface clock frequency
Junction-temperature range
fCLK
Tj
MHz
°C
-40 to 150
7 (16)
Preliminary Information
Rev. A1, 07-Nov-01
Preliminary Information
Noise and Surge Immunity
Parameter
Conducted interferences
Interference suppression
ESD (Human Body Model)
ESD (Machine Model)
Test Conditions
Value
Level 4 1)
Level 6
2 kV
ISO 7637–1
VDE 0879 Part 3
ESD S 5.1
JEDEC A115A
200 V
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Current Consumption
VVS < 16 V,
INH = low
Quiescent current
(VS )
1.1
1.2
3
IVS
1
5
µA
µA
A
A
Quiescent current
(VCC)
4.75 V < VVCC <
5.25 V, INH = low
11
IVCC
15
25
VVS <16 V
normal operating,
1.3
1.4
Supply current (VS)
3
IVS
4
6
mA
µA
A
A
all outputs off
4.75 V < VVCC
5.25 V,
<
Supply current (VCC)
11
IVCC
350
500
normal operating
2
Undervoltage Detection, Power-On Reset
Power-on reset
threshold
2.1
11
VVCC
tdPor
VUv
3.4
30
3.9
95
4.4
160
7.0
V
µs
V
A
A
A
B
A
Powe-on reset
delay time
After switching on
VCC
2.2
2.3
2.4
2.5
Undervoltage-
detection threshold
VCC = 5 V
VCC = 5 V
3
3
5.5
Undervoltage-
detection hysteresis
∆VUv
tdUV
0.6
V
Undervoltage-
detection delay time
10
40
µs
3
Thermal Prewarning and Shutdown
Thermal prewarning
3.1
3.2
TjPW set
120
105
145
130
170
155
°C
°C
B
B
Thermal prewarning
TjPW reset
Thermal prewarning
hysteresis
3.3
∆TjPW
15
°C
B
3.4
3.5
Thermal shutdown
Thermal shutdown
Tj switch off
Tj switch on
150
135
175
160
200
185
°C
°C
B
B
Thermal shutdown
hysteresis
3.6
∆Tj switch off
15
°C
B
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No.
Parameters
Ratio thermal
shutdown / thermal
prewarning
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Tj switch off /
TjPW set
3.7
1.05
1.2
B
Ratio thermal
shutdown / thermal
prewarning
Tj switch on /
TjPW reset
3.8
1.05
1.2
B
4
Output Specification (OUT1-OUT3)
4.1
2, 12,
13
On resistance
On resistance
IOut = 1.5 A
RDS On L
RDS On H
IOut1-3
1
1
Ω
Ω
B
B
A
4.2
4.3
2, 12,
13
IOut = -1.5 A
VOut1-3 = 0 V
Source output
leakage current
2, 12,
13
,
-15
µA
output stages off
4.4
4.5
VOut1-3 = VVS,
Sink output leakage
current
2, 12,
13
IOut1-3
300
1.3
µA
V
A
A
output stages off
High-side switch
reverse diode forward
voltage
2, 12,
13
IOut = 1.5 A
IOut = -1.5 A
VOut1-3–VVS
Low-side switch
reverse diode forward
voltage
2, 12,
13
4.6
4.7
4.8
VOut1-3
IOut1-3
IOut1-3
-1.3
-2.5
1.5
V
A
A
A
A
A
Source overcurrent
limitation and
shutdown threshold
2, 12,
13
-2
2
-1.5
2.5
Sink overcurrent
limitation and
shutdown threshold
2, 12,
13
Overcurrent
shutdown delay time
4.9
tdSd
IOut1-3
IOut1-3
tdSd
10
-45
15
40
-15
45
µs
mA
mA
µs
A
A
A
A
A
Source open-load
detection threshold
2, 12,
13
4.10
4.11
4.12
4.13
-30
30
Sink open-load
detection threshold
2, 12,
13
Open-load detection
delay time
200
600
15
VVS = 13 V,
Source output switch
on delay 1)
tdon
5
15
5
µs
RLoad = 30 Ω
VVS = 13 V,
Sink output switch on
delay 1)
4.14
4.15
4.16
tdon
tdoff
tdoff
25
15
2
µs
µs
µs
A
A
A
RLoad = 30 Ω
VVS = 13 V,
Source output switch
off delay 1)
RLoad = 30 Ω
VVS = 13 V,
Sink output switch off
delay 1)
1
RLoad = 30 Ω
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
9 (16)
Preliminary Information
Rev. A1, 07-Nov-01
Preliminary Information
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified,
all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Dead time between
corresponding high-
and low-side switches
VVS = 13 V,
4.17
tdon -tdoff
1
µs
B
RLoad = 30 Ω
5
Logic Inputs DI, CLK, CS, INH
Input voltage low-
level threshold
4-6,
10
0.3 ×
VVCC
5.1
VIL
VIH
∆VI
IPD
IPU
V
V
A
A
B
A
A
Input voltage high-
level threshold
4-6,
10
0.7 V
VC
5.2
5.3
5.4
C
Hysteresis of input
voltage
4-6,
10
50
10
500
60
mV
µA
µA
Pull-down current Pin
DI, CLK, INH
5, 6,
10
VDI, VCLK, VINH = VCC
VCS = 0 V
Pull-up current
Pin CS
5.5
6
4
-50
-10
Serial Interface – Logic Output DO
Output-voltage high
IOL = -2 mA
level
VVCC
0.7 V
-
6.2
9
9
VDOH
IDO
V
A
A
Leakage current
(tristate)
VCS = VCC
6.3
-10
10
µA
0V < VDO < VVCC
7
Inhibit Input - Timing
Standby setup time
Standby setup time
7.1
7.2
tIINHsethl
tIINHsetlh
100
100
µs
µs
A
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level. Device not in
stand-by for t >1ms
10 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Serial Interface – Timing
Test
Timing
Parameters
DO enable after CS falling edge
DO disable after CS rising edge
DO fall time
Conditions
Chart No.
Symbol
tENDO
tDISDO
tDOf
Min.
Typ.
Max.
200
200
100
100
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
DO = 100 pF
DO = 100 pF
1
2
C
CDO = 100 pF
-
DO rise time
C
DO = 100 pF
DO = 100 pF
-
tDOr
DO valid time
C
10
4
tDOVal
tCSSethl
tCSSetlh
tCSh
CS setup time
225
225
500
225
225
500
225
225
40
CS setup time
8
CS high time
9
CLK high time
5
tCLKh
CLK low time
6
tCLKl
CLK period time
CLK setup time
CLK setup time
DI setup time
-
tCLKp
7
tCLKSethl
tCLKSetlh
tDIset
3
11
12
DI hold time
tDIHold
40
11 (16)
Preliminary Information
Rev. A1, 07-Nov-01
Preliminary Information
Figure 4. Serial interface timing with chart numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC
Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
12 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Application Circuit
Figure 5.
Vcc
U5021M
Enable
Watchdog
Vs
O
C
S
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
BYT41D
n. n.
u. u.
n. n. n. n. n. n.
u. u. u. u. u. u.
3
VS
V
Batt
+
13 V
Input register
Output register
Serial interface
Charge
pump
n. n. n. n. n. n.
u. u. u. u. u. u.
DI
P
S
F
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
O
P
L
T
P
5
6
CLK
CS
UV
protection
Vcc
4
µC
Fault
Fault
Fault
detect
detect
detect
Vcc
11
1
INH
VCC
10
Control
logic
5 V
+
Power-on
reset
DO
GND
GND
GND
GND
9
7
8
Fault
detect
Fault
detect
Fault
detect
Thermal
protection
14
2
12
OUT2
13
OUT1
OUT3
Vcc
M
M
Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as
possible to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value
for electrolytic capacitor depends on external loads, conducted interferences and
reverse conducting current IOutzx (see Absolute Maximum Ratings).
Recommended value for capacitors at VCC
:
Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended to place cooling areas on the PCB as
close as possible to GND pins.
13 (16)
Preliminary Information
Rev. A1, 07-Nov-01
Preliminary Information
Package Information
5.2
4.8
Package SO14
Dimensions in mm
8.75
7.62
3.7
1.4
0.25
0.2
0.4
3.8
0.10
1.27
6.15
5.85
14
8
technical drawings
according to DIN
specifications
1
7
14 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and
do not contain such substances.
15 (16)
Preliminary Information
Rev. A1, 07-Nov-01
Atmel Wireless & Microcontrollers Sales Offices
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Tel: +81 3 3523 3551
Fax: +81 3 3523 7581
Web Site
http://www.atmel-wm.com
© Atmel Germany GmbH 2001.
Atmel Germany GmbH makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel Germany GmbH’s Terms and Conditions. The Company assumes no responsibility for any errors which may appear in
this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commit-
ment to update the information contained herein. No licenses to patents or other intellectual property of Atmel Germany GmbH are granted by
the Company in connection with the sale of AtmelGermany GmbH products, expressly or by implication. Atmel Germany GmbH’s products are
not authorized for use as critical components in life support devices or systems.
Data sheets can also be retrieved fron the Internet: http://www.atmel-wm.com
Rev. A1, 07-Nov-01
相关型号:
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