TSC80251G2D-L16CED [TEMIC]
8/16-bit Microcontroller with Serial Communication Interfaces; 8位/ 16位微控制器，串行通信接口
| 型号： | TSC80251G2D-L16CED |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | 8/16-bit Microcontroller with Serial Communication Interfaces |
| 文件： | 总63页 (文件大小：813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSC80251G2D
8/16-bit Microcontroller with Serial Communication
Interfaces
1. Description
The TSC80251G2D products are derivatives of the the TSC83251G2D and TSC87251G2D provide on-chip
TEMIC Microcontroller family based on the 8/16-bit code memory: 32 Kbytes ROM and 32 Kbytes EPROM/
C251 Architecture. This family of products is tailored OTPROM respectively.
to 8/16-bit microcontroller applications requiring an
They provide transparent enhancements to Intel’s
increased instruction throughput, a reduced operating
8xC251Sx family with an additional Synchronous Serial
frequency or a larger addressable memory space. The
architecture can provide a significant code size reduction
when compiling C programs while fully preserving the
legacy of C51 assembly routines.
2
Link Controller (SSLC supporting I C, µWire and SPI
protocols), a Keyboard interrupt interface, a dedicated
Baud Rate Generator for UART, and Power Management
features.
The TSC80251G2D derivatives are pin and software
compatible with standard 80C51/Fx/Rx/Rx+ with
extended on-chip data memory (1 Kbyte RAM) and up
to 256 Kbytes of external code and data. Additionally,
TSC80251G2D derivatives are optimized for speed and
for low power consumption on a wide voltage range.
Note:
This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device usage, please request
the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide.
2. Typical Applications
● ISDN Terminals
● High-Speed Modems
● PABX (SOHO)
● Line Cards
● Scanners
● Banking Machines
● Barcode Readers
● Smart Cards Readers
● High-End Digital Monitors
● High-End Joysticks
● DVD ROM and Players
● Printers
● Plotters
Rev. A - May 7, 1999
1
TSC80251G2D
3. Features
● Pin and Software Compatibility with Standard 80C51
•
16-bit watchdog timer/counter capability
Products and 80C51Fx/Rx/Rx+
● Secure 14-bit Hardware Watchdog Timer
● Power Management
● Plug-In Replacement of Intel’s 8xC251Sx
®
● C251 core: Intel’s MCS 251 D-step Compliance
•
•
•
•
•
Power-On reset (integrated on the chip)
Power-Off flag (cold and warm resets)
Software programmable system clock
Idle mode
•
•
•
•
40-byte register file
Registers accessible as Bytes, Words or Dwords
Three-stage instruction pipeline
16-bit internal code fetch
Power-Down mode
● Enriched C51 Instruction Set
● Keyboard Interrupt Interface on Port 1
● Non Maskable Interrupt Input (NMI)
•
•
•
16-bit and 32-bit ALU
Compare and conditional jump instructions
Expanded set of move instructions
● Real-Time Wait States Inputs (WAIT#/AWAIT#)
● ONCE mode and full speed Real-Time In-Circuit
● Linear Addressing
Emulation support (Third Party Vendors)
● 1 Kbyte of On-Chip RAM
● High Speed Versions:
● External Memory Space (Code/Data) Programmable
•
•
•
4.5 to 5.5 V
from 64 Kbytes to 256 Kbytes
16 MHz and 24 MHz
● TSC87251G2D: 32 Kbytes of On-Chip EPROM/
Typical operating current: 35 mA @ 24 MHz
24 mA @ 16 MHz
OTPROM
•
SINGLE PULSE Programming Algorithm
•
Typical power-down current: 2 µA
● TSC83251G2D: 32 Kbytes of On-Chip Masked ROM
● TSC80251G2D: ROMless Version
● Low Voltage Version:
•
•
•
•
2.7 to 5.5 V
● Four 8-bit Parallel I/O Ports (Ports 0, 1, 2 and 3 of
16 MHz
the standard 80C51)
Typical operating current: 11 mA @ 3V
Typical power-down current: 1 µA
● Serial I/O Port: full duplex UART (80C51
compatible) with independent Baud Rate Generator
● Temperature Ranges:
● SSLC: Synchronous Serial Link Controller
2
•
•
•
Commercial (0°C to +70°C)
•
•
I C multi-master protocol
Industrial (-40°C to +85°C)
µWire and SPI master and slave protocols
Option: extended range (-55°C to +125°C)
● Three 16-bit Timers/Counters (Timers 0, 1 and 2 of
the standard 80C51)
● Packages:
● EWC: Event and Waveform Controller
•
•
•
PDIL 40, PLCC 44 and VQFP 44
•
Compatible with Intel’s Programmable Counter
Array (PCA)
CDIL 40 and CQPJ 44 with window
Options: known good dice and ceramic packages
•
Common 16-bit timer/counter reference with four
possible clock sources (Fosc/4, Fosc/12, Timer 1
and external input)
•
Five modules, each with four programmable
modes:
-
-
16-bit software timer/counter
16-bit timer/counter capture input and
software pulse measurement
-
-
High-speed output and 16-bit software pulse
width modulation (PWM)
8-bit hardware PWM without overhead
2
Rev. A - May 7, 1999
TSC80251G2D
4. Block Diagram
P3(A16) P2(A15-8) P1(A17) P0(AD7-0)
PSEN#
ALE/PROG#
EA#/VPP
ROM
Timers 0, 1 and 2
EPROM
OTPROM
32 Kbytes
RAM
PORTS 0-3
1 Kbyte
UART
Baud Rate Generator
16-bit Memory Code
16-bit Memory Address
Event and Waveform
Controller
2
I C/SPI/µWire
AWAIT#
Controller
Bus Interface Unit
Watchdog Timer
RST
Power Management
XTAL2
Clock Unit
Clock System Prescaler
XTAL1
Keyboard Interface
CPU
NMI
Interrupt Handler
Unit
VDD
VSS
VSS1
VSS2
Figure 1. TSC80251G2D Block Diagram
Rev. A - May 7, 1999
3
TSC80251G2D
5. Pin Description
5.1 Pinout
P1.0/T2
1
2
3
4
5
6
7
8
9
40
39
38
37
36
VDD
P1.1/T2EX
P1.2/ECI
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P1.3/CEX0
P1.4/CEX1/SS#
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA#/VPP
30 ALE/PROG#
29 PSEN#
P3.0/RXD 10
P3.1/TXD 11
P3.2/INT0# 12
P3.3/INT1# 13
P3.4/T0 14
TSC80251G2D
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
P3.5/T1 15
P3.6/WR# 16
P3.7/A16/RD# 17
XTAL2 18
XTAL1 19
VSS 20
Figure 2. TSC80251G2D 40-pin DIP package
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
7
8
9
39 P0.4/AD4
38 P0.5/AD5
37 P0.6/AD6
36 P0.7/AD7
35 EA#/VPP
34 NMI
33 ALE/PROG#
32 PSEN#
31 P2.7/A15
30 P2.6/A14
29 P2.5/A13
RST 10
P3.0/RXD 11
AWAIT# 12
P3.1/TXD 13
P3.2/INT0# 14
P3.3/INT1# 15
P3.4/T0 16
TSC80251G2D
P3.5/T1 17
Figure 3. TSC80251G2D 44-pin PLCC Package
4
Rev. A - May 7, 1999
TSC80251G2D
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NMI
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
TSC80251G2D
9
10
11
P3.5/T1
Figure 4. TSC80251G2D 44-pin VQFP Package
Table 1. TSC80251G2D Pin Assignment
DIP PLCC VQFP
Name
DIP PLCC VQFP
Name
1
2
39
40
41
42
43
44
1
VSS1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VSS2
1
2
P1.0/T2
21
22
23
24
25
26
27
28
29
30
P2.0/A8
3
P1.1/T2EX
P1.2/ECI
P2.1/A9
3
4
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN#
4
5
P1.3/CEX0
P1.4/CEX1/SS#
5
6
6
7
P1.5/CEX2/MISO
7
8
2
P1.6/CEX3/SCL/SCK/WAIT#
8
9
3
P1.7/A17/CEX4/SDA/MOSI/WCLK
9
10
11
12
13
14
15
16
17
18
19
20
21
22
4
RST
10
5
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
ALE/PROG#
NMI
6
11
12
13
14
15
16
17
18
19
20
7
31
32
33
34
35
36
37
38
39
40
EA#/VPP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
8
9
10
11
12
13
14
15
16
P3.5/T1
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
Rev. A - May 7, 1999
5
TSC80251G2D
5.2 Signals
Table 2. Product Name Signal Descriptions
Signal
Name
Alternate
Function
Type
Description
th
A17
O
18 Address Bit
P1.7
Output to memory as 18th external address bit (A17) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15).
th
A16
O
17 Address Bit
Output to memory as 17th external address bit (A16) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15).
P3.7
(1)
A15:8
O
I/O
O
Address Lines
P2.7:0
P0.7:0
Upper address lines for the external bus.
(1)
AD7:0
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
ALE
Address Latch Enable
ALE signals the start of an external bus cycle and indicates that valid address information
are available on lines A16/A17 and A7:0. An external latch can use ALE to demultiplex the
address from address/data bus.
AWAIT#
I
Real-time Asynchronous Wait States Input
When this pin is active (low level), the memory cycle is stretched until it becomes high.
When using the Product Name as a pin-for-pin replacement for a 8xC51 product, AWAIT#
can be unconnected without loss of compatibility or power consumption increase (on-chip
pull-up).
Not available on DIP package.
CEX4:0
EA#
I/O
I
PCA Input/Output pins
P1.7:3
CEXx are input signals for the PCA capture mode and output signals for the PCA compare
and PWM modes.
External Access Enable
EA# directs program memory accesses to on-chip or off-chip code memory.
For EA#= 0, all program memory accesses are off-chip.
For EA#= 1, an access is on-chip ROM if the address is within the range of the on-chip
ROM; otherwise the access is off-chip. The value of EA# is latched at reset.
For devices without ROM on-chip, EA# must be strapped to ground.
ECI
O
PCA External Clock input
P1.2
P1.5
ECI is the external clock input to the 16-bit PCA timer.
MISO
I/O
SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in
slave mode, MISO outputs data to the master controller.
MOSI
I/O
I
SPI Master Output Slave Input line
P1.7
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in
slave mode, MOSI receives data from the master controller.
INT1:0#
External Interrupts 0 and 1
P3.3:2
INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are
set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0
are set by a low level on INT1#/INT0#.
NMI
I
Non Maskable Interrupt
Holding this pin high for 24 oscillator periods triggers an interrupt.
When using the Product Name as a pin-for-pin replacement for a 8xC51 product, NMI can
be unconnected without loss of compatibility or power consumption increase (on-chip pull-
down).
Not available on DIP package.
P0.0:7
I/O
Port 0
AD7:0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high impedance inputs. To avoid any paraitic current consumption, Floating
P0 inputs must be polarized to V or V
.
SS
DD
6
Rev. A - May 7, 1999
TSC80251G2D
Signal
Name
Alternate
Function
Type
Description
P1.0:7
I/O
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides interrupt capability
for a keyboard interface.
P2.0:7
P3.0:7
I/O
I/O
I
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
A15:8
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
PROG#
Programming Pulse input
The programming pulse is applied to this input for programming the on-chip EPROM/
OTPROM.
PSEN#
RD#
O
O
I
Program Store Enable/Read signal output
PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in
UCONFIG0 byte (see Table 13, Page 15).
th
Read or 17 Address Bit (A16)
P3.7
Read signal output to external data memory depending on the values of bits RD0 and RD1
in UCONFIG0 byte (see Table 13, Page 15).
RST
Reset input to the chip
Holding this pin high for 64 oscillator periods while the oscillator is running resets the device.
The Port pins are driven to their reset conditions when a voltage greater than V
whether or not the oscillator is running.
is applied,
IH1
This pin has an internal pull-down resistor which allows the device to be reset by connecting
a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal
operation.
RXD
SCL
SCK
I/O
I/O
I/O
Receive Serial Data
P3.0
P1.6
P1.6
RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1,
2 and 3.
2
I C Serial Clock
2
When I C controller is in master mode, SCL outputs the serial clock to slave peripherals.
2
When I C controller is in slave mode, SCL receives clock from the master controller.
SPI Serial Clock
When SPI is in master mode, SCK outputs clock to the slave peripheral. When SPI is in
slave mode, SCK receives clock from the master controller.
2
SDA
SS#
T1:0
T2
I/O
I
I C Serial Data
P1.7
P1.4
2
SDA is the bidirectional I C data line.
SPI Slave Select Input
When in Slave mode, SS# enables the slave mode.
I/O
I/O
Timer 1:0 External Clock Inputs
When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count.
Timer 2 Clock Input/Output
P1.0
P1.1
For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock-out mode,
T2 is the clock output.
T2EX
TXD
I
Timer 2 External Input
In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-
reload mode, a falling edge causes the timer 2 register to be reloaded. In the up-down counter
mode, this signal determines the count direction: 1= up, 0= down.
O
Transmit Serial Data
P3.1
TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1,
2 and 3.
VDD
VPP
PWR
I
Digital Supply Voltage
Connect this pin to +5V or +3V supply voltage.
Programming Supply Voltage
The programming supply voltage is applied to this input for programming the on-chip EPROM/
OTPROM.
Rev. A - May 7, 1999
7
TSC80251G2D
Signal
Name
Alternate
Function
Type
Description
VSS
GND
GND
Circuit Ground
Connect this pin to ground.
VSS1
Secondary Ground 1
This ground is provided to reduce ground bounce and improve power supply bypassing.
Connection of this pin to ground is recommended. However, when using the TSC80251G2D
as a pin-for-pin replacement for a 8xC51 product, VSS1 can be unconnected without loss of
compatibility.
Not available on DIP package.
VSS2
GND
Secondary Ground 2
This ground is provided to reduce ground bounce and improve power supply bypassing.
Connection of this pin to ground is recommended. However, when using the TSC80251G2D
as a pin-for-pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of
compatibility.
Not available on DIP package.
WAIT#
WCLK
I
Real-time Synchronous Wait States Input
P1.6
The real-time WAIT# input is enabled by setting RTWE bit in WCON (S:A7h). During bus
cycles, the external memory system can signal ‘system ready’ to the microcontroller in real
time by controlling the WAIT# input signal.
O
Wait Clock Output
P1.7
P3.6
The real-time WCLK output is enabled by setting RTWCE bit in WCON (S:A7h). When
enabled, the WCLK output produces a square wave signal with a period of one half the
oscillator frequency.
WR#
O
I
Write
Write signal output to external memory.
XTAL1
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external
oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal
timing.
XTAL2
O
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external
oscillator is used, leave XTAL2 unconnected.
Note:
1. The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the Non-Page mode chip configuration. If the chip is configured in Page mode
operation, port 0 carries the lower address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data (D7:0).
8
Rev. A - May 7, 1999
TSC80251G2D
6. Address Spaces
The TSC80251G2D derivatives implement four different address spaces:
● On-chip ROM program/code memory (not present in ROMless devices)
● On-chip RAM data memory
● Special Function Registers (SFRs)
● Configuration array
6.1 Program/Code Memory
The TSC83251G2D and TSC87251G2D implement 32 Kbytes of on-chip program/code memory. Figure 5 shows
the split of the internal and external program/code memory spaces. If EA# is tied to a high level, the 32-Kbyte
on-chip program memory is mapped in the lower part of segment FF: where the C251 core jumps after reset. The
rest of the program/code memory space is mapped to the external memory. If EA# is tied to a low level, the
internal program/code memory is not used and all the accesses are directed to the external memory.
The TSC83251G2D products provide the internal program/code memory in a masked ROM memory while the
TSC87251G2D products provide it in an EPROM memory. For the TSC80251G2D products, there is no internal
program/code memory and EA# must be tied to a low level.
Program/code
External Memory Space
Program/code
Segments
On-chip ROM/EPROM
Code Memory
FF:FFFFh
32 Kbytes
32 Kbytes
FF:8000h
FF:7FFFh
EA#= 0
EA#= 1
32 Kbytes
FF:0000h
FE:FFFFh
64 Kbytes
FE:0000h
FD:FFFFh
Reserved
02:0000h
01:FFFFh
01:0000h
00:FFFFh
128 Kbytes
00:0000h
Figure 5. Program/Code Memory Mapping
Notes:
Special care should be taken when the Program Counter (PC) increments:
1. If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper eight
bytes of the on-chip ROM (FF:7FF8h-FF:7FFFh). Because of its pipeline capability, the TSC80251G2D derivative may attempt to prefetch
code from external memory (at an address above FF:7FFFh) and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these
8 bytes does not affect Ports 0 and 2.
2. When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for compatibility with the C51 Architecture). When PC
increments beyond the end of segment FE:, it continues at the reset address FF:0000h (linearity). When PC increments beyond the end of
segment 01:, it loops to the beginning of segment 00: (this prevents from its going into the reserved area).
Rev. A - May 7, 1999
9
TSC80251G2D
6.2 Data Memory
The TSC80251G2D derivatives implement 1 Kbyte of on-chip data RAM. Figure 6 shows the split of the internal
and external data memory spaces. This memory is mapped in the data space just over the 32 bytes of registers
area (see TSC80251 Programmers’ Guide). Hence, the part of the on-chip RAM located from 20h to FFh is bit
addressable. This on-chip RAM is not accessible through the program/code memory space.
For faster computation with the on-chip ROM/EPROM code of the TSC83251G2D/TSC87251G2D, its upper 16
Kbytes are also mapped in the upper part of the region 00: if the On-Chip Code Memory Map configuration bit
is cleared (EMAP# bit in UCONFIG1 byte, see Figure 8). However, if EA# is tied to a low level, the TSC80251G2D
derivative is running as a ROMless product and the code is actually fetched in the corresponding external memory
(i.e. the upper 16 Kbytes of the lower 32 Kbytes of the segment FF:). If EMAP# bit is set, the on-chip ROM is
not accessible through the region 00:.
All the accesses to the portion of the data space with no on-chip memory mapped onto are redirected to the external
memory.
Data External
Memory Space
On-chip ROM/EPROM
Code Memory
Data Segments
FF:FFFFh
32 Kbytes
32 Kbytes
FF:8000h
FF:7FFFh
16 Kbytes
16 Kbytes
EA#= 0
EA#= 1
FF:0000h
FE:FFFFh
64 Kbytes
FE:0000h
FD:FFFFh
EMAP#= 0
Reserved
02:0000h
01:FFFFh
64 Kbytes
01:0000h
00:FFFFh
RAM Data
16 Kbytes
EMAP#= 1
00:C000h
00:BFFFh
1 Kbyte
≈47 Kbytes
00:0420h
32 bytes reg.
Figure 6. Data Memory Mapping
6.3 Special Function Registers
The Special Function Registers (SFRs) of the TSC80251G2D derivatives fall into the categories detailed in Table 3
to Table 11.
SFRs are placed in a reserved on-chip memory region S: which is not represented in the data memory mapping
(Figure 6). The relative addresses within S: of these SFRs are provided together with their reset values in Table 12.
They are upward compatible with the SFRs of the standard 80C51 and the Intel’s 80C251Sx family. In this table,
the C251 core registers are identified by Note 1 and are described in the TSC80251 Programmer’s Guide. The
other SFRs are described in the TSC80251G1D Design Guide. All the SFRs are bit-addressable using the C251
instruction set.
10
Rev. A - May 7, 1999
TSC80251G2D
Table 3. C251 Core SFRs
Mnemonic Name
Mnemonic Name
(1)
(1)
ACC
Accumulator
SPH
Stack Pointer High - MSB of SPX
(1)
(1)
B
B Register
DPL
DPH
Data Pointer Low byte - LSB of DPTR
Data Pointer High byte - MSB of DPTR
(1)
(1)
PSW
Program Status Word
Program Status Word 1
Stack Pointer - LSB of SPX
PSW1
DPXL
Data Pointer Extended Low byte of DPX - Region
number
(1)
SP
Note:
1. These SFRs can also be accessed by their corresponding registers in the register file.
Table 4. I/O Port SFRs
Mnemonic Name
Mnemonic Name
P0
P1
Port 0
Port 1
P2
P3
Port 2
Port 3
Table 5. Timers SFRs
Mnemonic Name
Mnemonic Name
TL0
Timer/Counter 0 Low Byte
TMOD
Timer/Counter 0 and 1 Modes
TH0
TL1
Timer/Counter 0 High Byte
Timer/Counter 1 Low Byte
Timer/Counter 1 High Byte
Timer/Counter 2 Low Byte
Timer/Counter 2 High Byte
Timer/Counter 0 and 1 Control
T2CON
Timer/Counter 2 Control
T2MOD
RCAP2L
RCAP2H
WDTRST
Timer/Counter 2 Mode
TH1
TL2
Timer/Counter 2 Reload/Capture Low Byte
Timer/Counter 2 Reload/Capture High Byte
WatchDog Timer Reset
TH2
TCON
Table 6. Serial I/O Port SFRs
Mnemonic Name
Mnemonic Name
SCON
SBUF
Serial Control
SADDR
BRL
Slave Address
Serial Data Buffer
Baud Rate Reload
Baud Rate Control
SADEN
Slave Address Mask
BDRCON
Table 7. SSLC SFRs
Mnemonic Name
Mnemonic Name
SSCON
SSDAT
SSCS
Synchronous Serial control
SSADR
SSBR
Synchronous Serial Address
Synchronous Serial Bit Rate
Synchronous Serial Data
Synchronous Serial Control and Status
Rev. A - May 7, 1999
11
TSC80251G2D
Table 8. Event Waveform Control SFRs
Mnemonic Name
Mnemonic Name
CCON
EWC-PCA Timer/Counter Control
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
EWC-PCA Compare Capture Module 0 Low Register
CMOD
CL
EWC-PCA Timer/Counter Mode
EWC-PCA Compare Capture Module 1 Low Register
EWC-PCA Compare Capture Module 2 Low Register
EWC-PCA Compare Capture Module 3 Low Register
EWC-PCA Compare Capture Module 4 Low Register
EWC-PCA Compare Capture Module 0 High Register
EWC-PCA Compare Capture Module 1 High Register
EWC-PCA Compare Capture Module 2 High Register
EWC-PCA Compare Capture Module 3 High Register
EWC-PCA Compare Capture Module 4 High Register
EWC-PCA Timer/Counter Low Register
EWC-PCA Timer/Counter High Register
EWC-PCA Timer/Counter Mode 0
EWC-PCA Timer/Counter Mode 1
EWC-PCA Timer/Counter Mode 2
EWC-PCA Timer/Counter Mode 3
EWC-PCA Timer/Counter Mode 4
CH
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
Table 9. System Management SFRs
Mnemonic Name
Mnemonic Name
PCON
Power Control
Power Management
CKRL
Clock Reload
POWM
WCON
Synchronous Real-Time Wait State Control
Table 10. Interrupt SFRs
Mnemonic Name
Mnemonic Name
IE0
Interrupt Enable Control 0
IPL0
IPH1
IPL1
Interrupt Priority Control Low 0
Interrupt Priority Control High 1
Interrupt Priority Control Low 1
IE1
Interrupt Enable Control 1
IPH0
Interrupt Priority Control High 0
Table 11. Keyboard Interface SFRs
Mnemonic Name
Mnemonic Name
P1IE
P1F
Port 1 Input Interrupt Enable
Port 1 Flag
P1LS
Port 1 Level Selection
12
Rev. A - May 7, 1999
TSC80251G2D
Table 12. SFR Addresses and Reset Values
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
CH
0000 0000
CCAP0H
0000 0000
CCAP1H
0000 0000
CCAP2H
0000 0000
CCAP3H
0000 0000
CCAP4H
0000 0000
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
(1)
B
0000 0000
CL
0000 0000
CCAP0L
0000 0000
CCAP1L
0000 0000
CCAP2L
0000 0000
CCAP3L
0000 0000
CCAP4L
0000 0000
(1)
ACC
0000 0000
CCON
00X0 0000
CMOD
00XX X000
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
(1)
(1)
PSW
PSW1
0000 0000
0000 0000
T2CON
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
(1)
IPL0
X000 0000
SADEN
0000 0000
SPH
0000 0000
P3
IE1
IPL1
IPH1
IPH0
X000 0000
1111 1111
XX0X XXX0 XX0X XXX0 XX0X XXX0
IE0
0000 0000
SADDR
0000 0000
P2
WDTRST
1111 1111
WCON
XXXX XX00
1111 1111
SCON
0000 0000
SBUF
XXXX XXXX
BRL
0000 0000
BDRCON
XXX0 0000
P1LS
0000 0000
P1IE
0000 0000
P1F
0000 0000
P1
SSBR
0000 0000
SSCON
SSCS
SSDAT
0000 0000
SSADR
0000 0000
(2)
(3)
1111 1111
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
CKRL
0000 1000
POWM
0XXX XXXX
8Fh
87h
(1)
(1)
(1)
(1)
P0
SP
DPL
DPH
DPXL
PCON
0000 0000
1111 1111
0000 0111
0000 0000
0000 0000
0000 0001
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Reserved
Notes:
1. These registers are described in the TSC80251 Programmer’s Guide (C251 core registers).
2. In I C and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in I C mode and 0000 0100 in SPI mode.
3. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000 0000 in write mode.
2
2
Rev. A - May 7, 1999
13
TSC80251G2D
6.4 Configuration Bytes
The TSC80251G2D derivatives provide user design flexibility by configuring certain operating features at device
reset. These features fall into the following categories:
•
external memory interface (Page mode, address bits, programmed wait states and the address range for RD#,
WR#, and PSEN#)
•
•
•
source mode/binary mode opcodes
selection of bytes stored on the stack by an interrupt
mapping of the upper portion of on-chip code memory to region 00:
Two user configuration bytes UCONFIG0 (see Figure 7) and UCONFIG1 (see Figure 8) provide the information.
When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The
TSC80251G2D derivatives reserve the top eight bytes of the memory address space (FF:FFF8h-FF:FFFFh) for an
external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1
at FF:FFF9h.
For the mask ROM devices, configuration information is stored in on-chip memory (see ROM Verifying). When
EA# is tied to a high level, the configuration information is retrieved from the on-chip memory instead of the
external address space and there is no restriction in the usage of the external memory.
UCONFIG0
Configuration Byte 0
7
-
6
5
4
3
2
1
0
WSA1#
WSA0#
XALE#
RD1
RD0
PAGE#
SRC
Bit Number Bit Mnemonic
Description
Reserved
7
-
Set this bit when writing to UCONFIG0.
Wait State A bits
Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses
(all regions except 01:).
6
WSA1#
WSA1#
WSA0#
Number of Wait States
0
0
1
1
0
1
0
1
3
2
1
0
5
4
WSA0#
XALE#
Extend ALE bit
Clear to extend the duration of the ALE pulse from T
to 3·T
OSC.
OSC
Set to minimize the duration of the ALE pulse to 1·T
.
OSC
Memory Signal Select bits
3
2
RD1
RD0
Specify a 18-bit, 17-bit or 16-bit external address bus and the usage of RD#, WR# and PSEN#
signals (see Table 13).
(1)
Page Mode Select bit
1
0
PAGE#
SRC
Clear to select the faster Page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0.
Set to select the non-Page mode with A15:8 on Port 2 and A7:0/D7:0 on Port 0.
(2)
Source Mode/Binary Mode Select bit
Clear to select the binary mode.
Set to select the source mode.
Notes:
1. UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page modes. If P2.1 is cleared during the first data fetch, a
Page mode configuration is used, otherwise the subsequent fetches are performed in Non-Page mode.
2. This selection provides compatibility with the standard 80C51 hardware which is multiplexing the address LSB and the data on Port 0.
Figure 7. Configuration Byte 0
14
Rev. A - May 7, 1999
TSC80251G2D
UCONFIG1
Configuration Byte 1
7
6
5
-
4
3
2
1
0
CSIZE
-
INTR
WSB
WSB1#
WSB0#
EMAP#
Bit Number Bit Mnemonic
Description
(1)
On-Chip Code Memory Size bit
CSIZE
TSC87251G2D
Clear to select 16 Kbytes of on-chip code memory (TSC87251G1D product).
Set to select 32 Kbytes of on-chip code memory (TSC87251G2D product).
7
-
Reserved
Set this bit when writing to UCONFIG1.
TSC80251G2D
TSC83251G2D
Reserved
Set this bit when writing to UCONFIG1.
6
5
-
-
Reserved
Set this bit when writing to UCONFIG1.
(2)
Interrupt Mode bit
Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register).
Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the
PSW1 register).
4
3
2
INTR
WSB
(3)
Wait State B bit
Clear to generate one wait state for memory region 01:.
Set for no wait states for memory region 01:.
Wait State B bits
Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses
(only region 01:).
WSB1#
WSB1#
WSB0#
Number of Wait States
0
0
1
1
0
1
0
1
3
2
1
0
1
0
WSB0#
EMAP#
On-Chip Code Memory Map bit
Clear to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space (at 00:C000h-00:FFFFh).
Set not to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space.
Notes:
1. The CSIZE is only available on EPROM/OTPROM products.
2. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used
with code executing outside region FF:.
3. Use only for Step A compatibility; set this bit when WSB1:0# are used.
Figure 8. Configuration Byte 1
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
RD1
RD0
P1.7
P3.7/RD#
PSEN#
WR#
External Memory
Read signal for all external Write signal for all external
memory locations memory locations
0
0
A17
A16
256 Kbytes
Read signal for all external Write signal for all external
memory locations memory locations
0
1
1
1
0
1
I/O pin
I/O pin
I/O pin
A16
128 Kbytes
64 Kbytes
Read signal for all external Write signal for all external
memory locations memory locations
I/O pin
Read signal for regions 00: Read signal for regions FE: Write signal for all external
and 01: and FF: memory locations
(1)
2 × 64 Kbytes
Note:
1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code.
Rev. A - May 7, 1999
15
TSC80251G2D
7. Instruction Set Summary
This section contains tables that summarize the instruction set. For each instruction there is a short description, its
length in bytes, and its execution time in states (one state time is equal to two system clock cycles). There are
two concurrent processes limiting the effective instruction throughput:
● Instruction Fetch
● Instruction Execution
Table 20 to Table 34 assume code executing from on-chip memory, then the CPU is fetching 16-bit at a time and
this is never limiting the execution speed.
If the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize
the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited
depending on the average size of instructions (for the considered section of the program flow). The maximum
average instruction throughput is provided by Table 14 depending on the external memory configuration (from
Page Mode to Non-Page Mode and the maximum number of wait states). If the average size of instructions is not
an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer
values.
Table 14. Minimum Number of States per Instruction for given Average Sizes
Average size of
Instructions
(bytes)
Non-Page Mode (states)
Page Mode
(states)
0 Wait State
1 Wait State
2 Wait States
3 Wait States
4 Wait States
1
2
3
4
5
1
2
3
4
5
2
4
3
6
4
5
6
8
10
15
20
25
12
18
24
30
6
9
12
16
20
8
12
15
10
If the average execution time of the considered instructions is larger than the number of states given by Table 14,
this larger value will prevail as the limiting factor. Otherwise, the value from Table 14 must be taken. This is
providing a fair estimation of the execution speed but only the actual code execution can provide the final value.
7.1 Notation for Instruction Operands
Table 15 to Table 19 provide notation for Instruction Operands.
Table 15. Notation for Direct Addressing
Direct Address
Description
C251
C51
A direct 8-bit address. This can be a memory address (00h-7Fh) or a SFR address (80h-
FFh). It is a byte (default), word or double word depending on the other operand.
dir8
dir16
✓
✓
✓
A 16-bit memory address (00:0000h-00:FFFFh) used in direct addressing.
Table 16. Notation for Immediate Addressing
Description
Immediate
Address
C251
C51
#data
An 8-bit constant that is immediately addressed in an instruction
A 16-bit constant that is immediately addressed in an instruction
✓
✓
✓
#data16
#0data16
#1data16
A 32-bit constant that is immediately addressed in an instruction. The upper word is filled
with zeros (#0data16) or ones (#1data16).
✓
✓
#short
A constant, equal to 1, 2, or 4, that is immediately addressed in an instruction.
Rev. A - May 7, 1999
16
TSC80251G2D
Table 17. Notation for Bit Addressing
Direct Address
Description
C251
C51
A directly addressed bit (bit number= 00h-FFh) in memory or an SFR. Bits 00h-7Fh are
the 128 bits in byte locations 20h-2Fh in the on-chip RAM. Bits 80h-FFh are the 128 bits
in the 16 SFRs with addresses that end in 0h or 8h, S:80h, S:88h, S:90h,..., S:F0h, S:F8h.
bit51
bit
✓
A directly addressed bit in memory locations 00:0020h-00:007Fh or in any defined SFR.
✓
Table 18. Notation for Destination in Control Instructions
Description
Direct Address
C251
C51
A signed (two’s complement) 8-bit relative address. The destination is -128 to +127 bytes
relative to the next instruction’s first byte.
rel
✓
✓
An 11-bit target address. The target is in the same 2-Kbyte block of memory as the next
instruction’s first byte.
addr11
✓
✓
A 16-bit target address. The target can be anywhere within the same 64-Kbyte region as
the next instruction’s first byte.
addr16
addr24
A 24-bit target address. The target can be anywhere within the 16-Mbyte address space.
✓
Table 19. Notation for Register Operands
Register
Description
C251
C51
@Ri
A memory location (00h-FFh) addressed indirectly via byte registers R0 or R1
✓
Rn
n
Byte register R0-R7 of the currently selected register bank
Byte register index: n= 0-7
✓
Rm
Rmd
Byte register R0-R15 of the currently selected register file
Destination register
Rms
m, md, ms
Source register
Byte register index: m, md, ms= 0-15
✓
✓
WRj
Word register WR0, WR2, ..., WR30 of the currently selected register file
Destination register
Source register
A memory location (00:0000h-00:FFFFh) addressed indirectly through word register WR0-
WR30, is the target address for jump instructions.
A memory location (00:0000h-00:FFFFh) addressed indirectly through word register (WR0-
WR30) + 16-bit signed (two’s complement) displacement value
Word register index: j, jd, js= 0-30
WRjd
WRjs
@WRj
@WRj +dis16
j, jd, js
DRk
Dword register DR0, DR4, ..., DR28, DR56, DR60 of the currently selected register file
Destination register
Source register
A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register DR0-
DR28, DR56 and DR60, is the target address for jump instruction
A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register (DR0-
DR28, DR56, DR60) + 16-bit (two’s complement) signed displacement value
Dword register index: k, kd, ks= 0, 4, 8..., 28, 56, 60
DRkd
DRks
@DRk
@DRk +dis16
k, kd, ks
✓
17
Rev. A - May 7, 1999
TSC80251G2D
7.2 Size and Execution Time for Instruction Families
Table 20. Summary of Add and Subtract Instructions
Add
ADD <dest>, <src>
dest opnd ← dest opnd + src opnd
Subtract
Add with Carry
Subtract with Borrow
SUB <dest>, <src>
ADDC <dest>, <src>
SUBB <dest>, <src>
dest opnd ← dest opnd - src opnd
(A) ← (A) + src opnd + (CY)
(A) ← (A) - src opnd - (CY)
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
A, Rn
Register to ACC
1
2
1
2
3
3
3
4
5
5
4
4
5
5
4
4
1
1
2
2
2
2
2
2
2
3
4
4
3
3
4
4
3
3
2
2
(2)
(2)
A, dir8
Direct address to ACC
1
1
ADD
A, @Ri
Indirect address to ACC
2
1
2
3
5
3
4
3
1
1
2
4
2
3
A, #data
Immediate data to ACC
Rmd, Rms
WRjd, WRjs
DRkd, DRks
Rm, #data
WRj, #data16
DRk, #0data16
Rm, dir8
Byte register to/from byte register
Word register to/from word register
Dword register to/from dword register
Immediate 8-bit data to/from byte register
Immediate 16-bit data to/from word register
16-bit unsigned immediate data to/from dword register
Direct address (on-chip RAM or SFR) to/from byte register
Direct address (on-chip RAM or SFR) to/from word register
Direct address (64K) to/from byte register
Direct address (64K) to/from word register
Indirect address (64K) to/from byte register
Indirect address (16M) to/from byte register
Register to/from ACC with carry
6
5
ADD / SUB
(2)
(2)
3
2
WRj, dir8
Rm, dir16
WRj, dir16
Rm, @WRj
Rm, @DRk
A, Rn
4
3
(3)
(3)
3
2
(4)
(3)
(3)
(4)
(3)
(3)
4
3
4
3
2
3
1
2
Direct address (on-chip RAM or SFR) to/from ACC with
carry
(2)
(2)
A, dir8
2
1
2
1
ADDC / SUBB
A, @Ri
A, #data
Indirect address to/from ACC with carry
Immediate data to/from ACC with carry
1
2
2
1
2
2
3
1
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Rev. A - May 7, 1999
18
TSC80251G2D
Table 21. Summary of Increment and Decrement Instructions
Increment
Increment
Decrement
Decrement
INC <dest>
INC <dest>, <src>
DEC <dest>
dest opnd ← dest opnd + 1
dest opnd ← dest opnd + src opnd
dest opnd ← dest opnd - 1
DEC <dest>, <src>
dest opnd ← dest opnd - src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
A
ACC by 1
1
1
2
1
3
3
3
3
1
1
1
2
2
2
2
2
2
2
1
1
Rn
Register by 1
1
2
INC
DEC
(2)
(2)
dir8
Direct address (on-chip RAM or SFR) by 1
Indirect address by 1
2
2
@Ri
3
2
2
4
5
1
4
1
1
3
4
1
Rm, #short
WRj, #short
DRk, #short
DRk, #short
DPTR
Byte register by 1, 2, or 4
INC
DEC
Word register by 1, 2, or 4
Double word register by 1, 2, or 4
Double word register by 1, 2, or 4
Data pointer by 1
INC
DEC
INC
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 22. Summary of Compare Instructions
Compare
CMP <dest>, <src>
dest opnd - src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(2)
Comments
Bytes States Bytes States
Rmd, Rms
Register with register
3
3
3
4
5
5
5
4
4
5
5
4
4
2
3
5
3
4
6
2
2
2
3
4
4
4
3
3
4
4
3
3
1
2
4
2
3
5
WRjd, WRjs
DRkd, DRks
Rm, #data
Word register with word register
Dword register with dword register
Register with immediate data
WRj, #data16
DRk, #0data16
DRk, #1data16
Rm, dir8
Word register with immediate 16-bit data
Dword register with zero-extended 16-bit immediate data
Dword register with one-extended 16-bit immediate data
Direct address (on-chip RAM or SFR) with byte register
Direct address (on-chip RAM or SFR) with word register
Direct address (64K) with byte register
CMP
6
5
(1)
(1)
3
2
WRj, dir8
4
3
(2)
(2)
Rm, dir16
3
2
(3)
(2)
(2)
(3)
(2)
(2)
WRj, dir16
Rm, @WRj
Rm, @DRk
Direct address (64K) with word register
4
3
4
3
2
3
Indirect address (64K) with byte register
Indirect address (16M) with byte register
Notes:
1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
19
Rev. A - May 7, 1999
TSC80251G2D
Table 23. Summary of Logical Instructions (1/2)
(1)
Logical AND
Logical OR
ANL <dest>, <src>
ORL <dest>, <src>
XRL <dest>, <src>
CLR A
CPL A
RL A
dest opnd ← dest opnd Λ src opnd
dest opnd ← dest opnd ς src opnd
dest opnd ← dest opnd src opnd
(A) ← 0
(1)
(1)
Logical Exclusive OR
(1)
Clear
(1)
Complement
Rotate Left
(A) ←
(A)
(A)
← (A) , n= 0..6
n+1
n
(A) ← (A)
0
7
Rotate Left Carry
RLC A
(A)
← (A) , n= 0..6
n+1 n
(CY) ← (A)
7
(A) ← (CY)
0
Rotate Right
RR A
(A) ← (A) , n= 7..1
n-1 n
(A) ← (A)
7
0
Rotate Right Carry
RRC A
(A) ← (A) , n= 7..1
n-1 n
(CY) ← (A)
0
(A) ← (CY)
7
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
A, Rn
register to ACC
1
2
1
2
2
3
3
3
4
5
4
4
5
5
4
4
1
1
1
1
1
1
1
2
2
2
2
2
3
2
2
3
4
3
3
4
4
3
3
1
1
1
1
1
1
2
(3)
(3)
A, dir8
A, @Ri
A, #data
dir8, A
dir8, #data
Rmd, Rms
WRjd, WRjs
Rm, #data
WRj, #data16
Rm, dir8
WRj, dir8
Rm, dir16
WRj, dir16
Rm, @WRj
Rm, @DRk
A
Direct address (on-chip RAM or SFR) to ACC
Indirect address to ACC
1
1
2
3
Immediate data to ACC
1
1
(4)
(4)
ACC to direct address
2
2
(4)
(4)
Immediate 8-bit data to direct address
Byte register to byte register
3
3
2
3
3
1
2
2
ANL
ORL
XRL
Word register to word register
Immediate 8-bit data to byte register
Immediate 16-bit data to word register
Direct address (on-chip RAM or SFR) to byte register
Direct address (on-chip RAM or SFR) to word register
Direct address (64K) to byte register
Direct address (64K) to word register
Indirect address (64K) to byte register
Indirect address (16M) to byte register
Clear ACC
4
3
(3)
(3)
3
2
4
3
(5)
(5)
3
2
(6)
(5)
(5)
(6)
(5)
(5)
4
3
4
3
2
3
CLR
CPL
RL
1
1
1
1
1
1
1
1
1
1
1
1
A
Complement ACC
A
Rotate ACC left
RLC
RR
A
Rotate ACC left through CY
A
Rotate ACC right
RRC
A
Rotate ACC right through CY
Notes:
1. Logical instructions that affect a bit are in Table 29.
2. A shaded cell denotes an instruction in the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Rev. A - May 7, 1999
20
TSC80251G2D
Table 24. Summary of Logical Instructions (2/2)
Shift Left Logical
Shift Right Arithmetic
Shift Right Logical
Swap
SLL <dest>
SRA <dest>
SRL <dest>
SWAP A
<dest> ← 0
0
<dest>
← <dest> , n= 0..msb-1
n+1
n
(CY) ← <dest>
msb
<dest>
← <dest>
msb
msb
<dest> ← <dest> , n= msb..1
n-1
n
(CY) ← <dest>
0
<dest>
← 0
msb
<dest> ← <dest> , n= msb..1
n-1
n
(CY) ← <dest>
0
A
A
7:4
3:0
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
Rm
WRj
Rm
WRj
Rm
WRj
A
Shift byte register left through the MSB
Shift word register left through the MSB
Shift byte register right
3
3
3
3
3
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
2
SLL
SRA
SRL
Shift word register right
Shift byte register left
Shift word register left
SWAP
Swap nibbles within ACC
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
Table 25. Summary of Multiply, Divide and Decimal-adjust Instructions
Multiply
Divide
Divide
MUL AB
MUL <dest>, <src>
DIV AB
(B:A) ← (A)×(B)
extended dest opnd ← dest opnd × src opnd
(A) ← Quotient ((A) ⁄ (B))
(B) ← Remainder ((A) ⁄ (B))
ext. dest opnd high ← Quotient (dest opnd ⁄ src opnd)
ext. dest opnd low ← Remainder (dest opnd ⁄ src opnd)
DIV <dest>, <src>
DA A
Decimal-adjust ACC
for Addition (BCD)
IF [[(A) > 9] [(AC)= 1]]
3:0
THEN (A) ← (A) + 6 !affects CY;
3:0
3:0
IF [[(A) > 9] [(CY)= 1]]
7:4
THEN (A) ← (A) + 6
7:4
7:4
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
AB
Multiply A and B
1
3
3
1
3
3
1
5
6
1
2
2
1
2
2
1
5
5
MUL
Rmd, Rms
WRjd, WRjs
AB
Multiply byte register and byte register
Multiply word register and word register
Divide A and B
12
10
11
21
1
11
10
10
20
1
DIV
Rmd, Rms
WRjd, WRjs
A
Divide byte register and byte register
Divide word register and word register
Decimal adjust ACC
DA
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
21
Rev. A - May 7, 1999
TSC80251G2D
Table 26. Summary of Move Instructions (1/3)
Move to High word
Move with Sign extension
Move with Zero extension
Move Code
MOVH <dest>, <src>
MOVS <dest>, <src>
MOVZ <dest>, <src>
MOVC A, <src>
dest opnd
← src opnd
31:16
dest opnd ← src opnd with sign extend
dest opnd ← src opnd with zero extend
(A) ← src opnd
Move eXtended
MOVX <dest>, <src>
dest opnd ← src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(2)
Comments
Bytes States Bytes States
MOVH
MOVS
MOVZ
DRk, #data16
WRj, Rm
16-bit immediate data into upper word of dword register
Byte register to word register with sign extension
Byte register to word register with zeros extension
Code byte relative to DPTR to ACC
5
3
3
1
1
1
1
1
1
3
2
4
2
2
1
1
1
1
1
1
2
1
WRj, Rm
2
1
(3)
(3)
A, @A +DPTR
A, @A +PC
A, @Ri
6
6
MOVC
(3)
(3)
Code byte relative to PC to ACC
6
6
(2)
Extended memory (8-bit address) to ACC
4
5
(2)
(4)
(4)
A, @DPTR
@Ri, A
Extended memory (16-bit address) to ACC
3
3
MOVX
(2)
ACC to extended memory (8-bit address)
4
4
(2)
(3)
(3)
@DPTR, A
ACC to extended memory (16-bit address)
4
4
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. Extended memory addressed is in the region specified by DPXL (reset value= 01h).
3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
Table 27. Summary of Move Instructions (2/3)
(1)
Move
MOV <dest>, <src>
dest opnd ← src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(2)
Comments
Bytes States Bytes States
A, Rn
Register to ACC
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
2
2
2
2
2
3
3
2
3
3
3
3
2
3
3
3
2
(3)
(3)
A, dir8
Direct address (on-chip RAM or SFR) to ACC
Indirect address to ACC
1
1
A, @Ri
2
1
3
1
A, #data
Rn, A
Immediate data to ACC
ACC to register
1
2
(3)
(3)
Rn, dir8
Rn, #data
dir8, A
Direct address (on-chip RAM or SFR) to register
Immediate data to register
1
2
1
2
(3)
(3)
ACC to direct address (on-chip RAM or SFR)
Register to direct address (on-chip RAM or SFR)
Direct address to direct address (on-chip RAM or SFR)
Indirect address to direct address (on-chip RAM or SFR)
Immediate data to direct address (on-chip RAM or SFR)
ACC to indirect address
2
2
MOV
(3)
(4)
(3)
(3)
(3)
(4)
(3)
(3)
dir8, Rn
dir8, dir8
dir8, @Ri
dir8, #data
@Ri, A
2
3
3
3
3
3
4
3
3
4
(3)
(3)
@Ri, dir8
@Ri, #data
DPTR, #data16
Direct address (on-chip RAM or SFR) to indirect address
Immediate data to indirect address
3
4
3
2
4
2
Load Data Pointer with a 16-bit constant
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions from the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. Apply note 3 for each dir8 operand.
Rev. A - May 7, 1999
22
TSC80251G2D
Table 28. Summary of Move Instructions (3/3)
(1)
Move
MOV <dest>, <src>
dest opnd ← src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
Rmd, Rms
WRjd, WRjs
DRkd, DRks
Rm, #data
Byte register to byte register
3
3
3
4
5
5
5
4
4
4
5
5
5
4
4
4
4
4
4
4
5
5
5
4
4
4
4
5
5
5
5
5
5
5
5
2
2
3
3
3
5
2
2
2
3
4
4
4
3
3
3
4
4
4
3
3
3
3
3
3
3
4
4
4
3
3
3
3
4
4
4
4
4
4
4
4
1
1
2
2
2
4
Word register to word register
Dword register to dword register
Immediate 8-bit data to byte register
WRj, #data16
DRk, #0data16
DRk, #1data16
Rm, dir8
Immediate 16-bit data to word register
zero-ext 16bit immediate data to dword register
one-ext 16bit immediate data to dword register
Direct address (on-chip RAM or SFR) to byte register
Direct address (on-chip RAM or SFR) to word register
Direct address (on-chip RAM or SFR) to dword register
Direct address (64K) to byte register
5
4
(3)
(3)
3
2
WRj, dir8
4
3
DRk, dir8
6
5
(4)
(4)
Rm, dir16
3
2
(5)
(6)
(4)
(4)
(5)
(5)
(3)
(5)
(6)
(4)
(4)
(5)
(5)
(3)
WRj, dir16
DRk, dir16
Rm, @WRj
Rm, @DRk
WRjd, @WRjs
WRj, @DRk
dir8, Rm
Direct address (64K) to word register
4
6
3
4
4
5
4
3
5
2
3
3
4
3
Direct address (64K) to dword register
Indirect address (64K) to byte register
Indirect address (16M) to byte register
Indirect address (64K) to word register
Indirect address (16M) to word register
Byte register to direct address (on-chip RAM or SFR)
Word register to direct address (on-chip RAM or SFR)
Dword register to direct address (on-chip RAM or SFR)
Byte register to direct address (64K)
MOV
dir8, WRj
5
4
dir8, DRk
7
6
(4)
(4)
dir16, Rm
4
3
(5)
(6)
(4)
(4)
(5)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
(5)
(6)
(4)
(4)
(5)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
dir16, WRj
dir16, DRk
@WRj, Rm
@DRk, Rm
@WRjd, WRjs
@DRk, WRj
Word register to direct address (64K)
5
7
4
5
5
6
6
7
7
8
6
7
7
8
4
6
3
4
4
5
5
6
6
7
5
6
6
7
Dword register to direct address (64K)
Byte register to indirect address (64K)
Byte register to indirect address (16M)
Word register to indirect address (64K)
Word register to indirect address (16M)
Rm, @WRj +dis16 Indirect with 16-bit displacement (64K) to byte register
WRj, @WRj +dis16 Indirect with 16-bit displacement (64K) to word register
Rm, @DRk +dis24 Indirect with 16-bit displacement (16M) to byte register
WRj, @WRj +dis24 Indirect with 16-bit displacement (16M) to word register
@WRj +dis16, Rm Byte register to indirect with 16-bit displacement (64K)
@WRj +dis16, WRj Word register to indirect with 16-bit displacement (64K)
@DRk +dis24, Rm Byte register to indirect with 16-bit displacement (16M)
@DRk +dis24, WRj Word register to indirect with 16-bit displacement (16M)
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions unique to the C251 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states).
23
Rev. A - May 7, 1999
TSC80251G2D
Table 29. Summary of Bit Instructions
Clear Bit
CLR <dest>
dest opnd ← 0
Set Bit
Complement Bit
AND Carry with Bit
SETB <dest>
CPL <dest>
ANL CY, <src>
dest opnd ← 1
dest opnd ←
(CY) ← (CY) src opnd
bit
AND Carry with Complement of Bit ANL CY, /<src>
OR Carry with Bit ORL CY, <src>
OR Carry with Complement of Bit ORL CY, /<src>
(CY) ← (CY)
(CY) ← (CY) src opnd
(CY) ← (CY)
src opnd
src opnd
Move Bit to Carry
Move Bit from Carry
MOV CY, <src>
MOV <dest>, CY
(CY) ← src opnd
dest opnd ← (CY)
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
CY
Clear carry
1
2
4
1
2
4
1
2
4
2
4
2
4
2
4
2
4
2
4
2
4
1
1
2
3
1
2
3
1
2
3
2
3
2
3
2
3
2
3
2
3
2
3
1
(3)
(3)
CLR
bit51
Clear direct bit
2
2
(3)
(3)
bit
Clear direct bit
4
3
CY
Set carry
1
1
(3)
(3)
SETB
CPL
bit51
Set direct bit
2
2
(3)
(3)
bit
Set direct bit
4
3
CY
Complement carry
Complement direct bit
Complement direct bit
And direct bit to carry
And direct bit to carry
1
1
(3)
(3)
bit51
2
2
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
bit
4
1
3
1
3
1
3
1
3
1
3
2
4
3
1
2
1
2
1
2
1
2
1
2
2
3
CY, bit51
CY, bit
CY, /bit51
CY, /bit
CY, bit51
CY, bit
CY, /bit51
CY, /bit
CY, bit51
CY, bit
bit51, CY
bit, CY
ANL
ORL
And complemented direct bit to carry
And complemented direct bit to carry
Or direct bit to carry
Or direct bit to carry
Or complemented direct bit to carry
Or complemented direct bit to carry
Move direct bit to carry
Move direct bit to carry
MOV
Move carry to direct bit
Move carry to direct bit
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Rev. A - May 7, 1999
24
TSC80251G2D
Table 30. Summary of Exchange, Push and Pop Instructions
Exchange bytes
Exchange Digit
Push
XCH A, <src>
XCHD A, <src>
PUSH <src>
(A) ↔ src opnd
(A) ↔ src opnd
(SP) ← (SP) +1; ((SP)) ← src opnd;
(SP) ← (SP) + size (src opnd) - 1
(SP) ← (SP) - size (dest opnd) + 1;
dest opnd ← ((SP)); (SP) ← (SP) -1
3:0
3:0
Pop
POP <dest>
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
A, Rn
A, dir8
A, @Ri
A, @Ri
dir8
ACC and register
1
2
1
1
2
4
5
3
3
3
2
3
3
3
3
2
2
2
2
2
3
4
2
2
2
2
2
2
2
4
(3)
(3)
XCH
ACC and direct address (on-chip RAM or SFR)
ACC and indirect address
3
3
4
5
XCHD
ACC low nibble and indirect address (256 bytes)
Push direct address onto stack
4
5
(2)
(2)
2
2
#data
#data16
Rm
Push immediate data onto stack
4
5
4
5
3
5
3
4
Push 16-bit immediate data onto stack
Push byte register onto stack
PUSH
WRj
Push word register onto stack
DRk
Push double word register onto stack
Pop direct address (on-chip RAM or SFR) from stack
Pop byte register from stack
9
8
(2)
(2)
dir8
3
3
Rm
3
5
9
2
4
8
POP
WRj
Pop word register from stack
DRk
Pop double word register from stack
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 31. Summary of Conditional Jump Instructions (1/2)
Jump conditional on status
Jcc rel
(PC) ← (PC) + size (instr);
IF [cc] THEN (PC) ← (PC) + rel
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
JC
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
Jump if carry
2
2
3
3
3
3
3
3
3
3
1/4
1/4
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2
2
2
2
2
2
2
2
2
2
1/4
1/4
1/4
1/4
1/4
1/4
1/4
1/4
1/4
1/4
JNC
JE
Jump if not carry
Jump if equal
JNE
JG
Jump if not equal
Jump if greater than
JLE
Jump if less than, or equal
JSL
Jump if less than (signed)
JSLE
JSG
JSGE
Notes:
Jump if less than, or equal (signed)
Jump if greater than (signed)
Jump if greater than or equal (signed)
1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.
25
Rev. A - May 7, 1999
TSC80251G2D
Table 32. Summary of Conditional Jump Instructions (2/2)
Jump if bit
JB <src>, rel
(PC) ← (PC) + size (instr);
IF [src opnd= 1] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [src opnd= 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
Jump if not bit
Jump if bit and clear
JNB <src>, rel
JBC <dest>, rel
IF [dest opnd= 1] THEN
dest opnd ← 0
(PC) ← (PC) + rel
Jump if accumulator is zero
Jump if accumulator is not zero
Compare and jump if not equal
JZ rel
(PC) ← (PC) + size (instr);
IF [(A)= 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
IF [(A) ≠ 0] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr);
JNZ rel
CJNE <src1>, <src2>, rel
IF [src opnd1 < src opnd2] THEN (CY) ← 1
IF [src opnd1 ≥ src opnd2] THEN (CY) ← 0
IF [src opnd1 ≠ src opnd2] THEN (PC) ← (PC) + rel
(PC) ← (PC) + size (instr); dest opnd ← dest opnd -1;
IF [ϕ (Z)] THEN (PC) ← (PC) + rel
Decrement and jump if not zero
DJNZ <dest>, rel
Binary Mode(2) Source Mode(2)
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
(3)(6)
(3)(6)
(3)(6)
(3)(6)
(5)(6)
(5)(6)
(3)(6)
(3)(6)
(3)(6)
(3)
bit51, rel
bit, rel
Jump if direct bit is set
3
5
3
5
3
5
2
2
3
3
3
3
2
3
2/5
4/7
2/5
4/7
4/7
3
4
3
4
3
4
2
2
3
3
4
4
3
3
2/5
3/6
2/5
JB
Jump if direct bit of 8-bit address location is set
Jump if direct bit is not set
bit51, rel
bit, rel
JNB
JBC
Jump if direct bit of 8-bit address location is not set
Jump if direct bit is set & clear bit
3/6
(5)(6)
(5)(6)
(6)
bit51, rel
bit, rel
4/7
6/9
Jump if direct bit of 8-bit address location is set and clear
Jump if ACC is zero
7/10
2/5
(6)
(6)
JZ
rel
2/5
(6)
JNZ
rel
Jump if ACC is not zero
2/5
2/5
(3)(6)
(6)
(3)(6)
(6)
A, dir8, rel
A, #data, rel
Rn, #data, rel
@Ri, #data, rel
Rn, rel
Compare direct address to ACC and jump if not equal
Compare immediate to ACC and jump if not equal
Compare immediate to register and jump if not equal
Compare immediate to indirect and jump if not equal
Decrement register and jump if not zero
Decrement direct address and jump if not zero
2/5
2/5
2/5
2/5
CJNE
(6)
(6)
(6)
(6)
(6)
(6)
2/5
3/6
3/6
2/5
4/7
3/6
DJNZ
(4)(6)
(4)(6)
dir8, rel
3/6
3/6
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add 5 if it addresses a Peripheral SFR.
6. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.
Rev. A - May 7, 1999
26
TSC80251G2D
Table 33. Summary of unconditional Jump Instructions
Absolute jump
Extended jump
Long jump
AJMP <src>
EJMP <src>
LJMP <src>
SJMP rel
(PC) ← (PC) +2; (PC)
(PC) ← (PC) + size (instr); (PC)
(PC) ← (PC) + size (instr); (PC)
← src opnd
10:0
← src opnd
← src opnd
23:0
15:0
Short jump
(PC) ← (PC) +2; (PC) ← (PC) +rel
Jump indirect
No operation
JMP @A +DPTR
NOP
(PC)
(PC) ← (PC) +1
← FFh; (PC)
← (A) + (DPTR)
15:0
23:16
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
(2)(3)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(3)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
AJMP
EJMP
addr11
addr24
@DRk
@WRj
addr16
rel
Absolute jump
Extended jump
2
5
3
3
3
2
1
1
3
6
7
6
5
4
5
2
4
2
2
3
2
1
1
3
5
6
5
5
4
5
Extended jump (indirect)
Long jump (indirect)
LJMP
Long jump (direct address)
Short jump (relative address)
Jump indirect relative to the DPTR
No operation (Jump never)
SJMP
JMP
@A +DPTR
NOP
1
1
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 3 to the number of states if the destination address is external.
Table 34. Summary of Call and Return Instructions
Absolute call
Extended call
Long call
ACALL <src>
ECALL <src>
LCALL <src>
(PC) ← (PC) +2; push (PC)
;
15:0
(PC)
← src opnd
10:0
(PC) ← (PC) + size (instr); push (PC)
;
;
23:0
15:0
(PC)
← src opnd
23:0
(PC) ← (PC) + size (instr); push (PC)
(PC)
← src opnd
15:0
Return from subroutine
Extended return from subroutine
Return from interrupt
RET
ERET
RETI
pop (PC)
pop (PC)
IF [INTR= 0] THEN pop (PC)
15:0
23:0
15:0
IF [INTR= 1] THEN pop (PC) ; pop (PSW1)
23:0
Trap interrupt
TRAP
(PC) ← (PC) + size (instr);
IF [INTR= 0] THEN push (PC)
15:0
IF [INTR= 1] THEN push (PSW1); push (PC)
23:0
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
(2)(3)
(2)(3)
(2)(3)
(2)(3)
ACALL
ECALL
addr11
@DRk
addr24
@WRj
addr16
Absolute subroutine call
Extended subroutine call (indirect)
Extended subroutine call
Long subroutine call (indirect)
Long subroutine call
2
3
5
3
3
1
3
1
2
9
2
2
4
2
3
1
2
1
1
9
14
14
10
13
(2)(3)
(2)(3)
(2)(3)
13
(2)(3)
(2)(3)
(2)
9
9
LCALL
(2)(3)
(2)
9
RET
ERET
RETI
TRAP
Notes:
Return from subroutine
7
7
(2)
(2)
Extended subroutine return
Return from interrupt
9
8
(2)(4)
(2)(4)
7
7
(4)
(4)
Jump to the trap interrupt vector
12
11
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 5 to the number of states if INTR= 1.
27
Rev. A - May 7, 1999
TSC80251G2D
8. Programming and Verifying Non-Volatile Memory
8.1 Internal Features
The internal non-volatile memory of the TSC80251G2D derivatives contains five different areas:
● Code Memory
● Configuration Bytes
● Lock Bits
● Encryption Array
● Signature Bytes
8.1.1 EPROM/OTPROM Devices
All the internal non-volatile memory but the Signature Bytes of the TSC87251G2D products is made of EPROM
cells. The Signature Bytes of the TSC87251G2D products are made of Mask ROM.
The TSC87251G2D products are programmed and verified in the same manner as TEMIC’s TSC87251G1A, using
a SINGLE-PULSE algorithm, which programs at V = 12.75V using only one 100 µs pulse per byte. This results
PP
in a programming time of less than 10 seconds for the 32 Kbytes on-chip code memory.
(1)
The EPROM of the TSC87251G2D products in Window package is erasable by Ultra-Violet radiation (UV).
UV erasure set all the EPROM memory cells to one and allows a reprogramming. The quartz window must be
(2)
covered with an opaque label when the device is in operation. This is not so much to protect the EPROM array
from inadvertent erasure, as to protect the RAM and other on-chip logic. Allowing light to impinge on the silicon
die during device operation may cause a logical malfunction.
The TSC87251G2D products in plastic packages are One Time Programmable (OTP). Then an EPROM cell cannot
be reset by UV once programmed to zero.
Notes:
2
1. The recommended erasure procedure is exposure to ultra-violet light (at 2537 Å) to an integrated dose of at least 20 W-sec/cm . Exposing
2
the EPROM to an ultra-violet lamp of 12000 µW/cm rating for 30 minutes should be sufficient.
2. Erasure of the EPROM begins to occur when the chip is exposed to light wavelength shorter than 4000 Å. Since sunlight and fluorescent
light have wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room-level
fluorescent lighting) could cause inadvertent erasure.
8.1.2 Mask ROM Devices
All the internal non-volatile memory of TSC83251G2D products is made of Mask ROM cells. They can only be
verified by the user, using the same algorithm as the EPROM/OTPROM devices.
8.1.3 ROMless Devices
The TSC80251G2D products do not include on-chip Configuration Bytes, Code Memory and Encryption Array.
They only include Signature Bytes made of Mask ROM cells which can be read using the same algorithm as the
EPROM/OTPROM devices.
8.2 Security Features
In some microcontrollers applications, it is desirable that the user’s program code be secured from unauthorized
access. The TSC83251G2D and TSC87251G2D offer two kinds of protection for program code stored in the on-
chip array:
● Program code in the on-chip Code Memory is encrypted when read out for verification if the Encryption Array is
programmed.
● A three-level lock bit system restricts external access to the on-chip code memory.
Rev. A - May 7, 1999
28
TSC80251G2D
8.2.1 Lock Bit System
The TSC87251G2D products implement 3 levels of security for User’s program as described in Table 35. The
TSC83251G2D products implement only the first level of security.
Level 0 is the level of an erased part and does not enable any security features.
Level 1 locks the programming of the User’s internal Code Memory, the Configuration Bytes and the Encryption
Array.
Level 2 locks the verifying of the User’s internal Code Memory. It is always possible to verify the Configuration
Bytes and the Lock Bits. It is never possible to verify the Encryption Array.
Level 3 locks the external execution.
Table 35. Lock Bits Programming
External
Lock bits
LB[2:0]
Internal
External
Level
Verification
Programming
PROM read
(MOVC)
Execution
Execution
(1)
(2)
0
1
2
3
000
001
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
Enable
Enable
Disable
Disable
Disable
Enable
(1)
Enable
Disable
Disable
Disable
(3)
01x
Disable
Disable
(3)
1xx
Notes:
1. Returns encrypted data if Encryption Array is programmed.
2. Returns non encrypted data.
3. x means don’t care. Level 2 always enables level 1, and level 3 always enables levels 1 and 2.
The security level may be verified according to Table 36.
Table 36. Lock Bits Verifying
Level
Lock bits Data(1)
0
1
2
3
xxxxx000
xxxxx001
xxxxx01x
xxxxx1xx
Note:
1. x means don’t care.
8.2.2 Encryption Array
The TSC83251G2D and TSC87251G2D products include a 128-byte Encryption Array located in non-volatile
memory outside the memory address space. During verification of the on-chip code memory, the seven low-order
address bits also address the Encryption Array. As the byte of the code memory is read, it is exclusive-NOR’ed
(XNOR) with the key byte from the Encryption Array. If the Encryption Array is not programmed (still all 1s),
the user program code is placed on the data bus in its original, unencrypted form. If the Encryption Array is
programmed with key bytes, the user program code is encrypted and cannot be used without knowledge of the
key byte sequence.
To preserve the secrecy of the encryption key byte sequence, the Encryption Array can not be verified.
Cautions:
1. When a MOVC instruction is executed, the content of the ROM is not encrypted. In order to fully protect the user program code, the lock
bit level 1 (see Table 35) must always be set when encryption is used.
2. If the encryption feature is implemented, the portion of the on-chip code memory that does not contain program code should be filled with
“random” byte values to prevent the encryption key sequence from being revealed.
29
Rev. A - May 7, 1999
TSC80251G2D
8.3 Signature Bytes
The TSC80251G2D derivatives contain factory-programmed Signature Bytes. These bytes are located in non-volatile
memory outside the memory address space at 30h, 31h, 60h and 61h. To read the Signature Bytes, perform the
procedure described in section 8.5, using the verify signature mode (see Table 39). Signature byte values are listed
in Table 37.
Table 37. Signature Bytes (Electronic ID)
Signature Address
Signature Data
Vendor
TEMIC
30h
31h
58h
40h
F7h
77h
FDh
Architecture
C251
32 Kbytes EPROM or OTPROM
32 Kbytes MaskROM or ROMless
TSC80251G2D derivative
Memory
Revision
60h
61h
8.4 Programming Algorithm
Figure 9 shows the hardware setup needed to program the TSC87251G2D EPROM/OTPROM areas:
● The chip has to be put under reset and maintained in this state until the completion of the programming sequence.
● PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
● Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in
this state until the completion of the programming sequence (see below).
● The voltage on the EA# pin must be set to V
.
DD
● The programming mode is selected according to the code applied on Port 0 (see Table 38). It has to be applied
until the completion of this programming operation.
● The programming address is applied on Ports 1 and 3 which are respectively the Most Significant Byte (MSB)
and the Least Significant Byte (LSB) of the address.
● The programming data are applied on Port 2.
● The EPROM Programming is done by raising the voltage on the EA# pin to V , then by generating a low
PP
level pulse on ALE/PROG# pin.
● The voltage on the EA# pin must be lowered to V
before completing the programming operation.
DD
● It is possible to alternate programming and verifying operation (See Paragraph 8.5). Please make sure the
voltage on the EA# pin has actually been lowered to V before performing the verifying operation.
DD
● PSEN# and the other control signals have to be released to complete a sequence of programming operations
or a sequence of programming and verifying operations.
Rev. A - May 7, 1999
30
TSC80251G2D
VDD
VDD
RST
VDD
V
EA#/VPP
ALE/PROG#
PSEN#
PP
100 µs pulses
TSC87251G2D
Mode
A[7:0]
A[14:8]
Data
P0[7:0]
P3[7:0]
P1[7:0]
P2[7:0]
4 to 12 MHz
XTAL1
VSS/VSS1/VSS2
Figure 9. Setup for Programming
Table 38. Programming Modes
ROM Area(1)
RST
EA#/VPP PSEN# ALE/PROG#(2)
P0
P2
P1(MSB) P3(LSB)
16-bit Address
0000h-7FFFh (32 Kbytes)
On-chip Code Memory
1
V
0
0
1 Pulse
1 Pulse
68h
Data
PP
PP
CONFIG0: FFF8h
CONFIG1: FFF9h
Configuration Bytes
Lock Bits
1
V
69h
Data
LB0: 0001h
LB1: 0002h
LB2: 0003h
1
1
V
V
0
0
1 Pulse
1 Pulse
6Bh
6Ch
X
PP
Encryption Array
Data
0000h-007Fh
PP
Notes:
1. Signature Bytes are not user-programmable.
2. The ALE/PROG# pulse waveform is shown in Figure 31 page 54.
8.5 Verify Algorithm
Figure 10 shows the hardware setup needed to verify the TSC87251G2D EPROM/OTPROM or TSC83251G2D
ROM areas:
● The chip has to be put under reset and maintained in this state until the completion of the verifying sequence.
● PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
● Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in
this state until the completion of the verifying sequence (see below).
● The voltage on the EA# pin must be set to V
and ALE must be set to a high level.
DD
● The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion
of this verifying operation.
● The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address.
● Then device is driving the data on Port 2.
● It is possible to alternate programming and verification operation (see Paragraph 8.4). Please make sure the
voltage on the EA# pin has actually been lowered to V
before performing the verifying operation.
DD
● PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a
sequence of programming and verifying operations.
31
Rev. A - May 7, 1999
TSC80251G2D
Table 39. Verifying Modes
ROM Area(1)
RST
EA#/VPP PSEN# ALE/PROG#
P0
P2
P1(MSB) P3(LSB)
16-bit Address
0000h-7FFFh (32 Kbytes)
On-chip code memory
1
1
1
0
0
1
1
28h
Data
CONFIG0: FFF8h
CONFIG1: FFF9h
Configuration Bytes
1
29h
Data
Lock Bits
Signature Bytes
Note:
1
1
1
1
0
0
1
1
2Bh
29h
Data
Data
0000h
0030h, 0031h, 0060h, 0061h
1. To preserve the secrecy of on-chip code memory when encrypted, the Encryption Array can not be verified.
VDD
VDD
RST
VDD
EA#/VPP
ALE/PROG#
PSEN#
TSC8x251G2D
Mode
A[7:0]
P0[7:0]
P3[7:0]
P1[7:0]
P2[7:0]
Data
XTAL1
4 to 12 MHz
A[14:8]
VSS/VSS1/VSS2
Figure 10. Setup for Verifying
Rev. A - May 7, 1999
32
TSC80251G2D
9. Absolute Maximum Rating and Operating Conditions
9.1 Absolute Maximum Rating
Table 40. Absolute Maximum Ratings
● Storage Temperature......................... -65 to +150°C
● Voltage on any other Pin to VSS.... -0.5 to +6.5 V
● I
per I/O Pin ................................. 15 mA
● Power Dissipation ............................. 1.5 W
OL
9.2 Operating Conditions
Table 41. Operating Conditions
● Ambient Temperature Under Bias
Commercial ....................................... 0 to +70°C
Industrial............................................ -40 to +85°C
● V
DD
High Speed versions......................... 4.5 to 5.5 V
Low Voltage versions....................... 2.7 to 5.5 V
Note:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond
the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
Rev. A - May 7, 1999
33
TSC80251G2D
10. DC Characteristics - Commercial & Industrial
10.1 DC Characteristics: High Speed versions - Commercial & Industrial
Table 42. DC Characteristics; V = 4.5 to 5.5 V, T = -40 to +85°C
DD
A
Symbol
Parameter
Min
Typical(4)
Max
Units
Test Conditions
V
Input Low Voltage
-0.5
0.2·V
- 0.1
V
IL
DD
(except EA#, SCL, SDA)
(5)
V
Input Low Voltage
(SCL, SDA)
-0.5
0
0.3·V
V
V
V
V
V
IL1
DD
V
Input Low Voltage
(EA#)
0.2·V
- 0.3
DD
IL2
V
Input high Voltage
(except XTAL1, RST, SCL, SDA)
0.2·V
+ 0.9
V
V
+ 0.5
+ 0.5
IH
DD
DD
DD
(5)
V
Input high Voltage
(XTAL1, RST, SCL, SDA)
0.7·V
IH1
DD
(1)(2)
V
Output Low Voltage
(Ports 1, 2, 3)
0.3
0.45
1.0
I
I
I
= 100 µA
= 1.6 mA
= 3.5 mA
OL
OL
OL
OL
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
V
Output Low Voltage
(Ports 0, ALE, PSEN#, Port 2 in Page
Mode during External Address)
0.3
0.45
1.0
V
V
V
I
I
I
= 200 µA
= 3.2 mA
= 7.0 mA
OL1
OL
OL
OL
(3)
(3)
(3)
V
Output high Voltage
(Ports 1, 2, 3, ALE, PSEN#)
V
V
V
- 0.3
- 0.7
- 1.5
I
I
I
= -10 µA
= -30 µA
= -60 µA
OH
DD
DD
DD
OH
OH
OH
V
Output high Voltage
(Port 0, Port 2 in Page Mode during
External Address)
V
V
V
- 0.3
- 0.7
- 1.5
I
I
I
= -200 µA
= -3.2 mA
= -7.0 mA
OH1
DD
DD
DD
OH
OH
OH
V
I
V
data retention limit
1.8
V
RET
DD
Logical 0 Input Current
(Ports 1, 2, 3)
- 50
µA
V
V
= 0.45 V
IL0
IN
I
Logical 1 Input Current
(NMI)
+ 50
± 10
- 650
225
µA
µA
µA
= V
DD
IL1
IN
I
Input Leakage Current
(Port 0)
0.45 V < V < V
IN DD
LI
I
Logical 1-to-0 Transition Current
(Ports 1, 2, 3 - AWAIT#)
V = 2.0 V
IN
TL
R
I
RST Pull-Down Resistor
Pin Capacitance
40
110
10
kΩ
pF
RST
C
T = 25°C
A
IO
Operating Current
20
25
35
25
30
40
mA
F
F
F
= 12 MHz
= 16 MHz
= 24 MHz
DD
OSC
OSC
OSC
I
Idle Mode Current
5
6.5
9.5
6
8
12
mA
F
F
F
= 12 MHz
= 16 MHz
= 24 MHz
DL
OSC
OSC
OSC
I
Power-Down Current
2
20
13
75
µA
V
V
< V
< 5.5 V
PD
RET
DD
V
Programming supply voltage
Programming supply current
12.5
T = 0 to +40°C
A
PP
PP
I
mA
T = 0 to +40°C
A
34
Rev. A - May 7, 1999
TSC80251G2D
Notes:
1. Under steady-state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I
Maximum I
per port pin:............................................. 10 mA
OL
OL
per 8-bit port:
Port 0................. 26 mA
Ports 1-3............ 15 mA
Output Pins ....... 71 mA
Maximum Total I for all:
OL
If I
exceeds the test conditions, V
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and
3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In
applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the V
on ALE and PSEN# to drop below the specification when the address lines are stabilizing.
OH
4. Typical values are obtained using V = 5 V and T = 25°C. They are not tested and there is not guarantee on these values.
DD
A
2
5. The input threshold voltage of SCL and SDA meets the I C specification, so an input voltage below 0.3·V
will be recognized as a logic
DD
0 while an input voltage above 0.7·V
will be recognized as a logic 1.
DD
40
30
20
10
0
20
2
4
6
8
10
12
14
16
18
22
24
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
(1)
Frequency at X
(MHz)
TAL
Note:
1. The clock prescaler is not used: F
= F
.
OSC
XTAL
Figure 11. I /I Versus Frequency; V = 4.5 to 5.5 V
DD DL
DD
Rev. A - May 7, 1999
35
TSC80251G2D
10.2 DC Characteristics: Low Voltage versions - Commercial & Industrial
Table 43. DC Characteristics; V = 2.7 to 5.5 V, T = -40 to +85°C
DD
A
Symbol
Parameter
Min
Typical(4)
Max
Units
Test Conditions
V
Input Low Voltage
-0.5
0.2·V
- 0.1
V
IL
DD
(except EA#, SCL, SDA)
(5)
V
Input Low Voltage
(SCL, SDA)
-0.5
0
0.3·V
V
V
V
V
V
V
IL1
DD
V
Input Low Voltage
(EA#)
0.2·V
- 0.3
IL2
DD
V
Input high Voltage
(except XTAL1, RST, SCL, SDA)
0.2·V
+ 0.9
V
V
+ 0.5
+ 0.5
IH
(5)
DD
DD
DD
V
Input high Voltage
(XTAL1, RST, SCL, SDA)
0.7·V
IH1
DD
(1)(2)
V
Output Low Voltage
(Ports 1, 2, 3)
0.45
I
I
= 0.8 mA
OL
OL
(1)(2)
V
Output Low Voltage
0.45
= 1.6 mA
OL1
OL
(Ports 0, ALE, PSEN#, Port 2 in Page
Mode during External Address)
(3)
V
Output high Voltage
(Ports 1, 2, 3, ALE, PSEN#)
0.9·V
0.9·V
V
V
I
I
= -10 µA
= -40 µA
OH
DD
DD
OH
V
Output high Voltage
OH1
OH
(Port 0, Port 2 in Page Mode during
External Address)
V
I
V
data retention limit
DD
1.8
V
RET
Logical 0 Input Current
(Ports 1, 2, 3 - AWAIT#)
- 50
µA
V
V
= 0.45 V
IL0
IN
I
Logical 1 Input Current
(NMI)
+ 50
± 10
- 650
225
µA
µA
µA
= V
DD
IL1
IN
I
Input Leakage Current
(Port 0)
0.45 V < V < V
IN DD
LI
I
Logical 1-to-0 Transition Current
(Ports 1, 2, 3)
V = 2.0 V
IN
TL
R
I
RST Pull-Down Resistor
Pin Capacitance
40
110
10
kΩ
pF
RST
C
T = 25°C
A
IO
Operating Current
4
8
9
8
mA
5 MHz, V < 3.6 V
DD
10 MHz, V < 3.6 V
12 MHz, V < 3.6 V
DD
16 MHz, V < 3.6 V
DD
11
12
14
DD
11
DD
I
Idle Mode Current
0.5
1.5
2
1
4
5
7
mA
5 MHz, V < 3.6 V
DD
DL
10 MHz, V < 3.6 V
DD
12 MHz, V < 3.6 V
DD
3
16 MHz, V < 3.6 V
DD
I
Power-Down Current
1
10
µA
V
< V
< 3.6 V
PD
RET
DD
36
Rev. A - May 7, 1999
TSC80251G2D
Notes:
1. Under steady-state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I
Maximum I
per port pin:............................................. 10 mA
OL
OL
per 8-bit port:
Port 0................. 26 mA
Ports 1-3............ 15 mA
Output Pins ....... 71 mA
Maximum Total I for all:
OL
If I
exceeds the test conditions, V
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and
3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In
applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the V
on ALE and PSEN# to drop below the specification when the address lines are stabilizing.
OH
4. Typical values are obtained using V = 3 V and T = 25°C. They are not tested and there is not guarantee on these values.
DD
A
2
5. The input threshold voltage of SCL and SDA meets the I C specification, so an input voltage below 0.3·V
will be recognized as a logic
DD
0 while an input voltage above 0.7·V
will be recognized as a logic 1.
DD
15
10
5
0
2
4
6
8
10
12
14
16
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
(1)
Frequency at X
(MHz)
TAL
Note:
1. The clock prescaler is not used: F
= F
.
XTAL
OSC
Figure 12. I /I Versus X
Frequency; V = 2.7 to 3.6 V
DD
DD DL
TAL
Rev. A - May 7, 1999
37
TSC80251G2D
10.3 DC Characteristics: I
I
and I Test Conditions
DD, DL PD
VDD
VDD
I
DD
RST
VDD
VDD
TSC80251G2D
P0
(NC)
Clock Signal
XTAL2
XTAL1
EA#
VSS
All other pins are unconnected
Figure 13. I Test Condition, Active Mode
DD
VDD
I
DL
RST
VDD
VDD
TSC80251G2D
P0
(NC)
Clock Signal
XTAL2
XTAL1
EA#
VSS
All other pins are unconnected
Figure 14. I Test Condition, Idle Mode
DL
VDD
I
PD
RST
VDD
VDD
TSC80251G2D
P0
(NC)
XTAL2
XTAL1
EA#
VSS
All other pins are unconnected
Figure 15. I Test Condition, Power-Down Mode
PD
38
Rev. A - May 7, 1999
TSC80251G2D
11. AC Characteristics - Commercial & Industrial
11.1 AC Characteristics - External Bus Cycles
Definition of symbols
Table 44. External Bus Cycles Timing Symbol Definitions
Signals
Conditions
A
D
L
Address
H
L
High
Data In
ALE
Low
V
X
Z
Valid
Q
R
W
Data Out
RD#/PSEN#
WR#
No Longer Valid
Floating
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 45 and Table 46 list the AC timing parameters for the TSC80251G2D derivatives with no wait states. External
wait states can be added by extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks
parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states.
Figure 16 to Figure 21 show the bus cycles with the timing parameters.
Rev. A - May 7, 1999
39
TSC80251G2D
Table 45. Bus Cycles AC Timings; V = 4.5 to 5.5 V, T = -40 to 85°C
DD
A
12 MHz
16 MHz
24 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
T
1/F
83
78
62
58
41
38
37
3
ns
OSC
OSC
(2)
T
ALE Pulse Width
ns
LHLL
AVLL
LLAX
(2)
T
T
Address Valid to ALE Low
78
58
ns
Address hold after ALE Low
RD#/PSEN# Pulse Width
19
11
ns
(1)
RLRH
(3)
T
162
165
22
121
124
14
78
81
6
ns
(3)
T
WR# Pulse Width
ns
WLWH
(1)
T
ALE Low to RD#/PSEN# Low
ALE High to Address Hold
ns
LLRL
(2)
T
99
70
40
ns
LHAX
(1)
(3)
T
RD#/PSEN# Low to Valid Data
Data Hold After RD#/PSEN# High
Address Hold After RD#/PSEN# High
RD#/PSEN# Low to Address Float
Instruction Float After RD#/PSEN# High
Data Float After RD#/PSEN# High
RD#/PSEN# high to ALE High (Instruction)
RD#/PSEN# high to ALE High (Data)
WR# High to ALE High
146
104
61
ns
RLDV
RHDX
RHAX
(1)
(1)
T
T
T
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
(1)
0
0
0
RLAZ
T
45
40
30
RHDZ1
RHDZ2
RHLH1
RHLH2
T
T
T
215
165
115
49
43
31
215
215
169
169
115
115
T
ns
WHLH
(2)(3)
T
T
T
Address (P0) Valid to Valid Data In
Address (P2) Valid to Valid Data In
Address (P0) Valid to Valid Instruction In
Data Hold after Address Hold
Address Valid to RD# Low
250
306
150
175
223
109
105
140
68
ns
AVDV1
AVDV2
AVDV3
(2)(3)
ns
(3)
ns
T
0
0
0
ns
AXDX
(1)
(2)
T
100
100
158
90
70
40
40
74
32
72
84
ns
AVRL
(2)
T
Address (P0) Valid to WR# Low
Address (P2) Valid to WR# Low
Data Hold after WR# High
70
ns
ns
AVWL1
AVWL2
(2)
T
115
69
T
ns
WHQX
QVWH
WHAX
(3)
T
Data Valid to WR# High
133
167
102
125
ns
T
WR# High to Address Hold
ns
Notes:
1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·T
OSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·T
(N= 1..3).
OSC
40
Rev. A - May 7, 1999
TSC80251G2D
Table 46. Bus Cycles AC Timings; V = 2.7 to 5.5 V, T = -40 to 85°C
DD
A
12 MHz
16 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
T
1/F
83
72
62
52
51
6
ns
OSC
OSC
(2)
T
ALE Pulse Width
ns
LHLL
AVLL
LLAX
(2)
T
T
Address Valid to ALE Low
71
ns
Address hold after ALE Low
14
ns
(1)
RLRH
(3)
T
RD#/PSEN# Pulse Width
163
165
17
121
124
11
57
ns
(3)
T
WR# Pulse Width
ns
WLWH
(1)
T
ALE Low to RD#/PSEN# Low
ALE High to Address Hold
ns
LLRL
(2)
T
90
ns
LHAX
(1)
(3)
T
RD#/PSEN# Low to Valid Data
Data Hold After RD#/PSEN# High
Address Hold After RD#/PSEN# High
RD#/PSEN# Low to Address Float
Instruction Float After RD#/PSEN# High
Data Float After RD#/PSEN# High
RD#/PSEN# high to ALE High (Instruction)
RD#/PSEN# high to ALE High (Data)
WR# High to ALE High
133
92
ns
RLDV
RHDX
RHAX
(1)
(1)
T
T
T
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
(1)
0
0
RLAZ
T
59
48
RHDZ1
RHDZ2
RHLH1
RHLH2
T
T
T
225
175
60
47
226
226
172
172
T
ns
WHLH
(2)(3)
T
T
T
Address (P0) Valid to Valid Data In
Address (P2) Valid to Valid Data In
Address (P0) Valid to Valid Instruction In
Data Hold after Address Hold
Address Valid to RD# Low
289
296
144
160
211
98
ns
AVDV1
AVDV2
AVDV3
(2)(3)
ns
(3)
ns
T
0
0
ns
AXDX
(1)
(2)
T
111
111
158
82
64
ns
AVRL
(2)
T
Address (P0) Valid to WR# Low
Address (P2) Valid to WR# Low
Data Hold after WR# High
64
ns
ns
AVWL1
AVWL2
(2)
T
116
66
T
ns
WHQX
QVWH
WHAX
(3)
T
Data Valid to WR# High
135
168
103
125
ns
T
WR# High to Address Hold
ns
Notes:
1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·T
OSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·T
(N= 1..3).
OSC
Rev. A - May 7, 1999
41
TSC80251G2D
Waveforms in Non-Page Mode
ALE
(1)
T
LHLL
(1)
(1)
RLRH
T
T
T
RHLH1
LLRL
PSEN#
(1)
RLDV
T
T
RLAZ
(1)
T
T
LHAX
RHDZ1
(1)
T
T
T
RHDX
AVLL
LLAX
P0
A7:0
D7:0
(1)
Instruction In
T
AVRL
(1)
T
T
AVDV1
(1)
RHAX
T
AVDV2
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 16. External Bus Cycle: Code Fetch (Non-Page Mode)
ALE
(1)
T
LHLL
(1)
(1)
RLRH
T
T
T
RHLH2
LLRL
RD#/PSEN#
(1)
RLDV
T
T
RLAZ
(1)
T
T
LHAX
RHDZ2
(1)
T
T
T
RHDX
AVLL
LLAX
P0
A7:0
D7:0
(1)
Data In
T
AVRL
(1)
T
T
AVDV1
(1)
RHAX
T
AVDV2
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 17. External Bus Cycle: Data Read (Non-Page Mode)
42
Rev. A - May 7, 1999
TSC80251G2D
ALE
WR#
(1)
T
LHLL
(1)
WLWH
T
T
WHLH
(1)
T
LHAX
T
QVWH
(1)
T
T
T
AVLL
LLAX
WHQX
P0
A7:0
D7:0
(1)
Data Out
T
AVWL1
(1)
T
T
AVWL2
WHAX
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 18. External Bus Cycle: Data Write (Non-Page Mode)
Waveforms in Page Mode
ALE
(1)
T
LHLL
(1)
T
LLRL
(3)
PSEN#
(1)
RLDV
T
T
RLAZ
(1)
T
LHAX
T
RHDZ1
(1)
T
T
LLAX
AVLL
T
RHDX
P2
A15:8
D7:0
D7:0
Instruction In
(1)
Instruction In
T
AVRL
(1)
T
T
AXDX
AVDV1
(1)
(1)
AVDV3
T
T
AVDV2
T
RHAX
P0/A16/A17
A7:0/A16/A17
A7:0/A16/A17
(2)
(2)
Page Miss
Page Hit
Notes:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch) requires one state (2·T
);
OSC
a page miss requires two states (4·T
).
OSC
3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
Figure 19. External Bus Cycle: Code Fetch (Page Mode)
Rev. A - May 7, 1999
43
TSC80251G2D
ALE
(1)
T
LHLL
(1)
(1)
RLRH
T
T
T
RHLH2
LLRL
RD#/PSEN#
(1)
RLDV
T
T
RLAZ
(1)
T
T
LHAX
RHDZ2
(1)
T
T
T
RHDX
AVLL
LLAX
P2
A15:8
D7:0
(1)
Data In
T
AVRL
(1)
T
T
AVDV1
(1)
RHAX
T
AVDV2
P0/A16/A17
A7:0/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 20. External Bus Cycle: Data Read (Page Mode)
ALE
WR#
(1)
T
LHLL
(1)
T
T
WLWH
WHLH
(1)
T
LHAX
T
QVWH
(1)
T
T
T
AVLL
LLAX
WHQX
P2
A15:8
D7:0
(1)
Data Out
T
AVWL1
(1)
T
T
AVWL2
WHAX
P0/A16/A17
A7:0/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 21. External Bus Cycle: Data Write (Page Mode)
44
Rev. A - May 7, 1999
TSC80251G2D
11.2 AC Characteristics - Real-Time Synchronous Wait State
Definition of symbols
Table 47. Real-Time Synchronous Wait Timing Symbol Definitions
Signals
Conditions
C
WCLK
L
Low
R
RD#/PSEN#
WR#
V
X
Valid
W
Y
No Longer Valid
WAIT#
Timings
Table 48. Real-Time Synchronous Wait AC Timings; V = 2.7 to 5.5 V, T = -40 to 85°C
DD
A
Symbol
Parameter
Min
Max
Unit
T
T
T
T
Wait Clock Low to Wait Set-up
0
T
- 20
ns
ns
ns
ns
ns
ns
CLYV
CLYX
RLYV
RLYX
WLYV
WLYX
OSC
Wait Hold after Wait Clock Low
PSEN#/RD# Low to Wait Set-up
Wait Hold after PSEN#/RD# Low
WR# Low to Wait Set-up
2W·T
2W·T
2W·T
+ 5
+ 5
+ 5
(1+2W)·T
- 20
- 20
- 20
OSC
OSC
0
T
- 20
OSC
(1+2W)·T
OSC
OSC
T
T
0
T
- 20
OSC
Wait Hold after WR# Low
(1+2W)·T
OSC
OSC
Waveforms
State 1
State 2
State 3
State 1 (next cycle)
WCLK
T
min
CLYX
T
max
CLYX
ALE
T
CLYV
RD#/PSEN#
RD#/PSEN# stretched
T
T
max
RLYX
min
RLYX
T
RLYV
WAIT#
P0
A7:0
D7:0
stretched
stretched
A7:0
P2
A15:8
A15:8
Figure 22. Real-time Synchronous Wait State: Code Fetch/Data Read
Rev. A - May 7, 1999
45
TSC80251G2D
State 1
State 2
State 3
State 1 (next cycle)
WCLK
T
min
CLYX
T
max
CLYX
ALE
T
CLYV
RD#/PSEN#
WR# stretched
T
T
max
WLYX
min
WLYX
T
WLYV
WAIT#
P0
A7:0
D7:0
stretched
stretched
P2
A15:8
Figure 23. Real-time Synchronous Wait State: Data Write
11.3 AC Characteristics - Real-Time Asynchronous Wait State
Definition of symbols
Table 49. Real-Time Asynchronous Wait Timing Symbol Definitions
Signals
Conditions
S
PSEN#/RD#/WR#
AWAIT#
L
Low
Y
V
X
Valid
No Longer Valid
Timings
Table 50. Real-Time Asynchronous Wait AC Timings; V = 2.7 to 5.5 V, T = -40 to 85°C
DD
A
Symbol
Parameter
Min
Max
Unit
T
PSEN#/RD#/WR# Low to Wait Set-up
Wait Hold after PSEN#/RD#/WR# Low
T
- 10
ns
SLYV
SLYX
OSC
(1)
T
(2N-1)·T
+ 10
ns
OSC
Note:
1. N is the number of wait states added (N≥ 1).
Waveforms
RD#/PSEN#/WR#
T
SLYX
T
SLYV
AWAIT#
Figure 24. Real-time Asynchronous Wait State Timings
46
Rev. A - May 7, 1999
TSC80251G2D
11.4 AC Characteristics - Serial Port in Shift Register Mode
Definition of symbols
Table 51. Serial Port Timing Symbol Definitions
Signals
Conditions
D
Q
X
Data In
H
L
High
Data Out
Clock
Low
V
X
Valid
No Longer Valid
Timings
Table 52. Serial Port AC Timing -Shift Register Mode; V = 2.7 to 5.5 V, T = -40 to 85°C
DD
A
12 MHz
16 MHz
24 MHz(1)
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
T
Serial Port Clock Cycle Time
998
833
165
0
749
625
124
0
500
417
82
ns
ns
ns
ns
ns
XLXL
QVXH
XHQX
XHDX
XHDV
T
T
T
T
Output Data Setup to Clock Rising Edge
Output Data hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
0
974
732
482
Note:
1. For high speed versions only.
Waveforms
T
XLXL
TXD
T
(1)
QVXH
Set TI
T
XHQX
RXD (Out)
RXD (In)
0
1
2
3
4
5
6
7
(1)
T
Set RI
XHDX
T
XHDV
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Note:
1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.
Figure 25. Serial Port Waveforms - Shift Register Mode
Rev. A - May 7, 1999
47
TSC80251G2D
11.5 AC Characteristics - SSLC: I C Interface
2
Timings
2
Table 53. I C Interface AC Timing; V = 2.7 to 5.5 V, T = -40 to 85°C
DD
A
INPUT
OUTPUT
Symbol
Parameter
Min
Max Min
Max
(4)
(4)
(4)
(1)
THD; STA
TLOW
Start condition hold time
14·TCLCL
16·TCLCL
14·TCLCL
4.0 µs
4.7 µs
(1)
SCL low time
SCL high time
SCL rise time
SCL fall time
Data set-up time
(1)
THIGH
4.0 µs
(2)
TRC
1 µs
-
(3)
TFC
0.3 µs
0.3 µs
(4)
TSU; DAT1
TSU; DAT2
TSU; DAT3
THD; DAT
TSU; STA
TSU; STO
TBUF
250 ns
20·TCLCL - TRD
(1)
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
Data hold time
250 ns
1 µs
(4)
250 ns
8·TCLCL
(4)
0 ns
8·TCLCL - TFC
(4)
(4)
(4)
(1)
Repeated START set-up time
STOP condition set-up time
Bus free time
14·TCLCL
14·TCLCL
14·TCLCL
4.7 µs
(1)
4.0 µs
(1)
4.7 µs
(2)
(3)
TRD
SDA rise time
1 µs
-
TFD
SDA fall time
0.3 µs
0.3 µs
Notes:
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL= 400 pF.
4. TCLCL= T
OSC
= one oscillator clock period.
Waveforms
Repeated START condition
START or Repeated START condition
START condition
STOP condition
TSU;STA
TRD
0.7 V
DD
SDA
0.3 V
(INPUT/OUTPUT)
DD
TFD
TSU;STO
TBUF
TSU;DAT3
TRC
TFC
0.7 V
DD
SCL
0.3 V
(INPUT/OUTPUT)
DD
THD;STA
TLOW THIGH TSU;DAT1 THD;DAT
TSU;DAT2
2
Figure 26. I C Waveforms
48
Rev. A - May 7, 1999
TSC80251G2D
11.6 AC Characteristics - SSLC: SPI Interface
Definition of symbols
Table 54. SPI Interface Timing Symbol Definitions
Signals
Conditions
C
I
Clock
H
L
High
Data In
Data Out
SS#
Low
O
S
V
X
Z
Valid
No Longer Valid
Floating
Timings
Table 55. SPI Interface AC Timing; V = 2.7 to 5.5 V, T = -40 to 85°C
DD
A
Symbol
Parameter
Min
Max
Unit
Slave mode(1)
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Clock Period
8
T
T
T
CHCH
CHCX
CLCX
OSC
Clock High Time
Clock Low Time
SS# Low to Clock edge
3.2
3.2
200
100
100
OSC
OSC
, T
ns
SLCH
SLCL
IVCH
CHIX
, T
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
SS# High after Clock Edge
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
SS# Low to Output Data Valid
Output Data Hold after SS# High
SS# High to SS# Low
ns
ns
ns
ns
ns
ns
ns
ns
ns
IVCL
CLIX
, T
T
100
CLOV, CHOV
, T
0
CLOX
CHOX
CHSH
IVCH
, T
0
CLSH
, T
, T
100
100
IVCL
CLIX
CHIX
130
130
SLOV
SHOX
SHSL
ILIH
(2)
Input Rise Time
2
µs
µs
ns
ns
Input Fall Time
2
IHIL
Output Rise time
100
100
OLOH
OHOL
Output Fall Time
Rev. A - May 7, 1999
49
TSC80251G2D
Symbol
Parameter
Min
Max
Unit
Master mode(3)
T
T
T
T
T
T
T
T
T
T
T
Clock Period
4
T
T
T
CHCH
CHCX
CLCX
OSC
Clock High Time
Clock Low Time
1.6
1.6
50
50
OSC
OSC
, T
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
Input Data Rise Time
ns
IVCL
CLIX
IVCH
CHIX
, T
ns
ns
ns
µs
µs
ns
ns
T
65
CLOV, CHOV
, T
0
CLOX
ILIH
CHOX
2
2
Input Data Fall Time
IHIL
Output Data Rise time
50
50
OLOH
Output Data Fall Time
OHOL
Notes:
1. Capacitive load on all pins= 200 pF in slave mode.
2. The value of this parameter depends on software.
3. Capacitive load on all pins= 100 pF in master mode.
Waveforms
(1)
SS#
(output)
T
CHCH
T
T
CLCH
SCK
(SSCPOL= 0)
(output)
T
T
CLCX
CHCX
CHCL
SCK
(SSCPOL= 1)
(output)
T
T
T
T
IVCH
IVCL
CHIX
CLIX
MISO
(input)
MSB IN
BIT 6
LSB IN
T
T
T
T
CLOV
CHOV
CLOX
CHOX
MOSI
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
1. SS# handled by software.
Figure 27. SPI Master Waveforms (SSCPHA= 0)
50
Rev. A - May 7, 1999
TSC80251G2D
(1)
SS#
(output)
T
CHCH
T
T
CLCH
CHCL
SCK
(SSCPOL= 0)
(output)
T
T
CLCX
CHCX
SCK
(SSCPOL= 1)
(output)
T
T
T
T
IVCH
IVCL
CHIX
CLIX
MISO
(input)
MSB IN
BIT 6
LSB IN
T
T
T
T
CLOV
CHOV
CLOX
CHOX
MOSI
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
1. SS# handled by software.
Figure 28. SPI Master Waveforms (SSCPHA= 1)
SS#
(input)
T
T
T
T
SLCH
SLCL
CLSH
CHSH
T
T
SHSL
CHCH
T
T
CLCH
SCK
(SSCPOL= 0)
(input)
T
T
CLCX
CHCX
CHCL
SCK
(SSCPOL= 1)
(input)
T
T
T
T
CLOV
CHOV
CLOX
CHOX
T
T
SHOX
SLOV
MISO
(output)
(1)
SLAVE MSB OUT
BIT 6
SLAVE LSB OUT
T
T
T
T
IVCH
IVCL
CHIX
CLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but normally MSB of character just received.
Figure 29. SPI Slave Waveforms (SSCPHA= 0)
Rev. A - May 7, 1999
51
TSC80251G2D
SS#
(input)
T
T
T
T
SLCH
SLCL
CLSH
CHSH
T
T
SHSL
CHCH
T
T
CLCH
CHCL
SCK
(SSCPOL= 0)
(input)
T
T
CLCX
CHCX
SCK
(SSCPOL= 1)
(input)
T
T
T
T
CHOV
CLOV
CHOX
CLOX
T
T
SHOX
SLOV
MISO
(output)
(1)
SLAVE MSB OUT
BIT 6
SLAVE LSB OUT
T
T
T
T
IVCH
IVCL
CHIX
CLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but generally the LSB of the character which has just been received.
Figure 30. SPI Slave Waveforms (SSCPHA= 1)
52
Rev. A - May 7, 1999
TSC80251G2D
11.7 AC Characteristics - EPROM Programming and Verifying
Definition of symbols
Table 56. EPROM Programming and Verifying Timing Symbol Definitions
Signals
Conditions
A
E
G
Q
S
Address
H
L
High
Enable: mode set on Port 0
Program
Low
V
X
Z
Valid
Data Out
No Longer Valid
Floating
Supply (V
)
PP
Timings
Table 57. EPROM Programming AC timings; V = 4.5 to 5.5 V, T = 0 to 40°C
DD
A
Symbol
Parameter
Min
Max
Unit
T
XTAL1 Period
83.5
48
48
48
48
48
10
10
0
250
ns
OSC
T
Address Setup to PROG# low
T
T
T
T
T
AVGL
GHAX
OSC
OSC
OSC
OSC
T
Address Hold after PROG# low
Data Setup to PROG# low
Data Hold after PROG#
T
DVGL
GHDX
T
T
ENABLE High to V
PP
ELSH
SHGL
GHSL
OSC
T
T
V
V
Setup to PROG# low
µs
PP
PP
Hold after PROG#
µs
ns
µs
T
ENABLE Hold after V
PROG# Width
SLEH
PP
T
90
110
GLGH
Table 58. EPROM Verifying AC timings; V = 4.5 to 5.5 V, V = 2.7 to 5.5 V, T = 0 to 40°C
DD
DD
A
Symbol
Parameter
Min
Max
Unit
T
XTAL1 Period
83.5
250
48
ns
OSC
T
T
Address to Data Valid
Address to Data Invalid
ENABLE low to Data Valid
Data Float after ENABLE
T
AVQV
AXQX
OSC
0
0
0
ns
T
T
48
48
T
T
ELQV
EHQZ
OSC
OSC
Rev. A - May 7, 1999
53
TSC80251G2D
Waveforms
P1= A15:8
P3= A7:0
Address
Data
T
T
GHAX
AVGL
P2= D7:0
T
T
GHDX
DVGL
V
PP
V
T
T
T
GHSL
EA#/VPP
DD
SHGL
GLGH
V
SS
ALE/PROG#
P0
T
T
SLEH
ELSH
Mode= 68h, 69h, 6Bh or 6Ch
Figure 31. EPROM Programming Waveforms
P1= A15:8
P3= A7:0
Address
T
T
AXQX
AVQV
P2= D7:0
Data
T
T
EHQZ
ELQV
P0
Mode= 28h, 29h or 2Bh
Figure 32. EPROM Verifying Waveforms
54
Rev. A - May 7, 1999
TSC80251G2D
11.8 AC Characteristics - External Clock Drive and Logic Level References
Definition of symbols
Table 59. External Clock Timing Symbol Definitions
Signals
Conditions
C
Clock
H
L
High
Low
X
No Longer Valid
Timings
Table 60. External Clock AC Timings; V = 4.5 to 5.5 V, T = -40 to +85°C
DD
A
Symbol
Parameter
Min
Max
Unit
F
Oscillator Frequency
High Time
24
MHz
ns
OSC
T
10
10
3
CHCX
T
T
T
Low Time
ns
CLCX
CLCH
CHCL
Rise Time
ns
Fall Time
3
ns
Waveforms
T
T
CHCX
CLCH
V
- 0.5
DD
V
IH1
T
CLCX
V
IL
0.45 V
T
T
CLCL
CHCL
Figure 33. External Clock Waveform
INPUTS
0.2 V + 0.9
OUTPUTS
min
V
- 0.5
DD
V
DD
IH
0.2 V - 0.1
V
max
DD
IL
0.45 V
Note:
During AC testing, all inputs are driven at V
-0.5 V for a logic 1 and 0.45 V for a logic 0.
DD
Timing measurements are made on all outputs at V min for a logic 1 and V max for a logic 0.
IH
IL
Figure 34. AC Testing Input/Output Waveforms
V
+ 0.1 V
- 0.1 V
V
V
- 0.1 V
+ 0.1 V
LOAD
OH
OL
V
Timing Reference Points
LOAD
V
LOAD
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV
change from the loading V /V level occurs with I /I = ±20 mA.
OH OL
OL OH
Figure 35. Float Waveforms
Rev. A - May 7, 1999
55
TSC80251G2D
12. Packages
12.1 List of Packages
● PDIL 40
● CDIL 40 with window
● PLCC 44
● CQPJ 44 with window
● VQFP 44 (10x10)
12.2 PDIL 40 - Mechanical Outline
Figure 36. Plastic Dual In Line
Table 61. PDIL Package Size
MM
INCH
Min
Max
Min
Max
A
A1
A2
B
-
5.08
-
.200
-
0.38
3.18
0.36
0.76
0.20
50.29
15.24
12.32
-
.015
.125
.014
.030
.008
1.980
.600
.485
4.95
.195
.022
.070
.015
2.095
.625
.580
0.56
B1
C
1.78
0.38
D
53.21
E
15.87
E1
e
14.73
2.54 B.S.C.
.100 B.S.C.
.600 B.S.C.
eA
eB
L
15.24 B.S.C.
-
17.78
3.81
-
-
.700
.150
-
2.93
0.13
.115
.005
D1
Rev. A - May 7, 1999
56
TSC80251G2D
12.3 CDIL 40 with Window - Mechanical Outline
Figure 37. Ceramic Dual In Line
Table 62. CDIL Package Size
MM
INCH
Min
Max
Min
Max
A
b
-
5.71
-
.225
.023
.065
.015
2.105
.605
0.36
1.14
0.20
-
0.58
.014
.045
.008
-
b2
c
1.65
0.38
D
E
53.47
13.06
15.37
.514
e
2.54 B.S.C.
.100 B.S.C.
.600 B.S.C.
eA
L
15.24 B.S.C.
3.18
0.38
0.13
5.08
.125
.015
.005
.200
.055
-
Q
S1
a
1.40
-
0 - 15
0 - 15
N
40
57
Rev. A - May 7, 1999
TSC80251G2D
12.4 PLCC 44 - Mechanical Outline
Figure 38. Plastic Lead Chip Carrier
Table 63. PLCC Package Size
MM
INCH
Min
Max
Min
Max
A
A1
D
4.20
2.29
4.57
.165
.090
.685
.647
.590
.685
.647
.590
.180
.120
.695
.656
.630
.695
.656
.630
3.04
17.40
16.44
14.99
17.40
16.44
14.99
17.65
D1
D2
E
16.66
16.00
17.65
E1
E2
e
16.66
16.00
1.27 BSC
.050 BSC
G
1.07
1.07
0.51
0.33
1.22
.042
.042
.020
.013
.048
.056
-
H
1.42
J
-
K
0.53
.021
Nd
Ne
11
11
11
11
Rev. A - May 7, 1999
58
TSC80251G2D
12.5 CQPJ 44 with Window - Mechanical Outline
Figure 39. Ceramic Quad Pack J
Table 64. CQPJ Package size
MM
INCH
Min
Max
Min
Max
A
-
4.90
-
.193
.010
.691
.656
C
0.15
17.40
16.36
0.25
.006
.685
.644
D - E
17.55
D1 - E1
16.66
e
f
1.27 TYP
0.53
.050 TYP
0.43
0.86
.017
.034
.610
.021
.044
.630
J
1.12
Q
R
15.49
16.00
0.86 TYP
11
.034 TYP
N1
N2
11
11
11
59
Rev. A - May 7, 1999
TSC80251G2D
12.6 VQFP 44 (10x10) - Mechanical Outline
Figure 40. Shrink Quad Flat Pack (Plastic)
Table 65. VQFP Package Size
MM
INCH
Min
Max
Min
Max
A
A1
A2
A3
D
-
1.60
0.64 REF
0.64 REF
1.45
-
.063
.025 REF
.025REF
1.35
11.90
9.90
.053
.468
.390
.468
.390
.002
.018
.057
.476
.398
.476
.398
6
12.10
D1
E
10.10
11.90
9.90
12.10
E1
J
10.10
0.05
-
L
0.45
0.75
.030
e
0.80 BSC
0.35 BSC
.0315 BSC
.014 BSC
f
Rev. A - May 7, 1999
60
TSC80251G2D
13. Ordering Information
13.1 TSC80251G2D ROMless
TEMIC Part Number
ROM
Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TSC80251G2D-16CB
TSC80251G2D-24CB
TSC80251G2D-24CED
TSC80251G2D-24IA
TSC80251G2D-24IB
ROMless
ROMless
ROMless
ROMless
ROMless
16 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack
24 MHz, Industrial -40° to 85°C, PDIL 40
24 MHz, Industrial -40° to 85°C, PLCC 44
(1)
Low Voltage Versions 2.7 to 5.5 V, Commercial
TSC80251G2D-L16CB
TSC80251G2D-L16CED
ROMless
ROMless
16 MHz, Commercial, PLCC 44
(1)
16 MHz, Commercial, VQFP 44, Dry pack
Note:
1. Dry Pack mandatory for VQFP package.
13.2 TSC83251G1D 16 Kbytes Mask ROM
TEMIC Part Number(2)
ROM
Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TSC251G1Dxxx-16CB
TSC251G1Dxxx-24CB
TSC251G1Dxxx-24CED
TSC251G1Dxxx-24IA
TSC251G1Dxxx-24IB
16K MaskROM
16K MaskROM
16K MaskROM
16K MaskROM
16K MaskROM
16 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack
24 MHz, Industrial -40° to 85°C, PDIL 40
24 MHz, Industrial -40° to 85°C, PLCC 44
(1)
Low Voltage Versions 2.7 to 5.5 V, Commercial
TSC251G1Dxxx-L16CB
TSC251G1Dxxx-L16CED
16K MaskROM
16K MaskROM
16 MHz, Commercial 0° to 70°C, PLCC 44
(1)
16 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack
Notes:
1. Dry Pack mandatory for VQFP package.
2. xxx: means ROM code, is Cxxx in case of encrypted code.
13.3 TSC83251G2D 32 Kbytes MaskROM
TEMIC Part Number(2)
ROM
Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TSC251G2Dxxx-16CB
TSC251G2Dxxx-24CB
TSC251G2Dxxx-24CED
TSC251G2Dxxx-24IA
TSC251G2Dxxx-24IB
32K MaskROM
32K MaskROM
32K MaskROM
32K MaskROM
32K MaskROM
16 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack
24 MHz, Industrial -40° to 85°C, PDIL 40
24 MHz, Industrial -40° to 85°C, PLCC 44
(1)
Low Voltage Versions 2.7 to 5.5 V, Commercial
TSC251G2Dxxx-L16CB
TSC251G2Dxxx-L16CED
32K MaskROM
32K MaskROM
16 MHz, Commercial 0° to 70°C, PLCC 44
(1)
16 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack
Notes:
1. Dry Pack mandatory for VQFP package.
2. xxx: means ROM code, is Cxxx in case of encrypted code.
Rev. A - May 7, 1999
61
TSC80251G2D
13.4 TSC87251G2D OTPROM
TEMIC Part Number
ROM
Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TSC87251G2D-16CB
TSC87251G2D-24CB
TSC87251G2D-24CED
TSC87251G2D-24IA
TSC87251G2D-24IB
32K OTPROM
32K OTPROM
32K OTPROM
32K OTPROM
32K OTPROM
16 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack
24 MHz, Industrial -40° to 85°C, PDIL 40
24 MHz, Industrial -40° to 85°C, PLCC 44
(1)
Low Voltage Versions 2.7 to 5.5 V, Commercial
TSC87251G2D-L16CB
TSC87251G2D-L16CED
32K OTPROM
32K OTPROM
16 MHz, Commercial 0° to 70°C, PLCC 44
(1)
16 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack
Note:
1. Dry Pack mandatory for VQFP package.
13.5 TSC87251G2D EPROM - UV Window package
TEMIC Part Number
ROM
Description
High Speed Versions 4.5 to 5.5 V, Industrial
TSC87251G2D-24IC
TSC87251G2D-24IJ
32K EPROM
32K EPROM
24 MHz, Industrial -40° to 85°C, window CQPJ 44
24 MHz, Industrial -40° to 85°C, window CDIL 40
Low Voltage Versions 2.7 to 5.5 V, Industrial
TSC87251G2D-L16IC
32K EPROM
16 MHz, Commercial -40° to 85°C, window CQPJ 44
13.6 Options (Please consult TEMIC sales)
•
•
•
•
•
ROM code encryption
Tape & Real or Dry Pack
Known good dice
Ceramic packages
Extended temperature range: -55°C to +125°C
13.7 Starter Kit
TEMIC Part Number
Description
TSC80251-SK
TSC80251 Starter Kit
13.8 Products Marking
ROMless versions
Mask ROM versions
OTP versions
TEMIC
TEMIC
Customer Part number
Temic Part number
TEMIC
Temic Part number(1)
Temic Part number(1)
M
C
M
C
M C
INTEL’97
YYWW . Lot Number
INTEL’97
YYWW . Lot Number
INTEL’97
YYWW . Lot Number
Note:
1. Dry Pack letter (D) not included in the marking.
62
Rev. A - May 7, 1999
Sales Offices
Sales Locations
Europe Sales Offices
Finland
Germany
Italy
United Kingdom
TEMIC Nordic AB
c/o Atmel OY
Kappelitie 6B
FIN–02200
Tel: 358 9 4520 8219
Fax: 358 9 529 619
TEMIC Semiconductor
GmbH
Erfurter Strasse 31
85386 Eching
Tel: 49 89 3 19 70 0
Fax: 49 89 3 19 46 21
TEMIC Italiana
Via Grosio, 10/8
20151 Milano
Tel: 39 02 38 03 71
Fax: 39 02 38 03 72 34
TEMIC U.K. Ltd.
Easthampstead Road
Bracknell, Berkshire RG12 1LX
Tel: 44 1344 707 300
Fax: 44 1344 427 371
Spain
TEMIC Iberica
Principe de Vergara, 112
28002 Madrid
Tel: 34 91 564 51 81
Fax: 34 91 562 75 14
France
TEMIC Semiconductor
GmbH
Kruppstrasse 6
45128 Essen
Tel: 49 2 01 24 73 00
Fax: 49 2 01 2 47 30 47
TEMIC France
Les Quadrants – 3,
avenue du centre
B.P. 309
78054 St.–Quentin–en–Yvelines
Cedex
Sweden
TEMIC Nordic AB
Kavallerivaegen 24, Rissne
Box 2042
17202 Sundbyberg
Tel: 46 8 587 48 800
Fax: 46 8 587 48 850
TEMIC Semiconductor
GmbH
Theresienstrasse 2
74072 Heilbronn
Tel: 49 71 31 67 3636
Fax: 49 71 31 67 3163
Tel: 33 1 30 60 70 00
Fax: 33 1 30 60 71 11
North America Sales Offices
Western
Eastern
TEMIC North America
c/o Atmel Corporation
2325 Orchard Parkway
San Jose
TEMIC North America Inc.
180 Mount Airy Road, Ste. 100
Basking Ridge
New Jersey 07920
California 95131
Tel: 1 408 441 0311
Fax: 1 408 436 4200
Tel: 1 908 630 9200
Fax: 1 908 630 9201
Asia Pacific / Japan Sales Offices
China
Japan
Korea
Taiwan, R.O.C.
TEMIC Shanghai
c/o Atmel Corp
4th floor, Block A
Shanghai Eastern Business Bldg
586 Fanyu Road, Shanghai
200052 China
Tel: 86 21 6280 9241
Fax: 86 21 6283 8816
TEMIC Semiconductors
c/o Atmel Japan K.K.
Tonetsushinkawa Bldg.
1–24–8, Shinkawa, chuku
Tokyo 104–0033
TEMIC Korea Ltd.
Suite 605, Singsong Bldg.
25–4 Yoido–dong
Youngdeungpo–Ku
150–010 Seoul
TEMIC Taiwan, c/o Atmel Corp.
9F–1 NO.266
SEC.1 Wen HWA 2RD
Lin Kon Hsiang
Taipei Hsien
Tel: 886 2 2609 5581
Fax: 886 2 2600 2735
Tel: 81 3 3523 3551
Fax: 81 3 3523 7581
Tel: 82 2 785 1136
Fax: 82 2 785 1137
Hong Kong
Rep. of Singapore
TEMIC Hong Kong Ltd.
c/o Atmel Asia Ltd
# 1216, Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon, Hong Kong
Tel: 852 23 789 789
TEMIC Singapore Pte Ltd
Keppel Building, #03–00
25 Tampines Street 92
Singapore 528877
Tel: 65 260 8223
Fax: 65 787 9819
Fax: 852 23 755 733
63
May 1999
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