TSC80C31-L20IBD_技术文档

TSC80C31/80C51

CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller

Description

The TSC80C31/80C51 is high performance SCMOS In addition, the TSC80C31/80C51 has two

versions of the 8051 NMOS single chip 8 bit µC.

software-selectable modes of reduced activity for further

reduction in power consumption. In the Idle Mode the

CPU is frozen while the RAM, the timers, the serial port,

and the interrupt system continue to function. In the

Power Down Mode the RAM is saved and all other

functions are inoperative.

The fully static design of the TSC80C31/80C51 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The TSC80C31/80C51 retains all the features of the 8051

: 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ;

two 16 bit timers ; a 5-source, 2-level interrupt structure

; a full duplex serial port ; and on-chip oscillator and clock

circuits.

The TSC80C31/80C51 is manufactured using SCMOS

process which allows them to run from 0 up to 44 MHz

with VCC = 5 V. The TSC80C31/80C51 is also available

at 20 MHz with 2.7 V < Vcc < 5.5 V.

D TSC80C31/80C51-L16 : Low power version

Vcc : 2.7–5.5 V Freq : 0–16 MHz

D TSC80C31/80C51-30 : 0 to 30 MHz

D TSC80C31/80C51-36 : 0 to 36 MHz

D TSC80C31/80C51-40 : 0 to 40 MHz

D TSC80C31/80C51-44 : 0 to 44 MHz*

D TSC80C31/80C51-L20 : Low power version

Vcc : 2.7–5.5 V Freq : 0–20 MHz

D TSC80C31/80C51-12 : 0 to 12 MHz

D TSC80C31/80C51-20 : 0 to 20 MHz

D TSC80C31/80C51-25 : 0 to 25 MHz

* Commercial and Industrial temperature range only. For other speed

and range please consult your sale office.

Features

D Power control modes

D Fully static design

D 128 bytes of RAM

D 0.8 µm CMOS process

D Boolean processor

D 4 K bytes of ROM (TSC80C31/80C51)

D 32 programmable I/O lines

D Two 16 bit timer/counter

D 64 K program memory space

D 64 K data memory space

D 5 interrupt sources

D Programmable serial port

D Temperature range : commercial, industrial, automotive and

military

Optional

D Secret ROM : Encryption

D Secret TAG : Identification number

MATRA MHS

1

Rev. E (14 Jan.97)

TSC80C31/80C51

Interface

Figure 1. Block Diagram

2

MATRA MHS

Rev. E (14 Jan.97)

TSC80C31/80C51

Figure 2. Pin Configuration

P1.5

P1.6

P1.7

RST

P0.4/A4

P0.5/A5

P0.6/A6

P0.7/A7

EA

DIL40

RxD/P3.0

NC

PLCC44

ALE

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P

/A4

/A5

/A6

/A7

P

04

15

P

16

05

P

17

06

P

RST

07

RxD/P

EA

NC

30

PQFP44

NC

ALE

TxD/P

31

INT0/P

PSEN

32

INT1/P

P

/A15

33

27

T0/P

P

/A14

/A13

34

26

T1/P

P

25

35

Diagrams are for reference only. Packages sizes are not to scale.

MATRA MHS

3

Rev. E (14 Jan.97)

TSC80C31/80C51

Pin Description

It also receives the high-order address bits and control

signals during program verification in the

TSC80C31/80C51. Port 2 can sink or source three LS

TTL inputs. It can drive CMOS inputs without external

pullups.

VSS

Circuit ground potential.

VCC

Supply voltage during normal, Idle, and Power Down

operation.

Port 3

Port 3 is an 8 bit bi-directional I/O port with internal

pullups. Port 3 pins that have 1’s written to them are

pulled high by the internal pullups, and in that state can

be used as inputs. As inputs, Port 3 pins that are externally

being pulled low will source current (ILL, on the data

sheet) because of the pullups. It also serves the functions

of various special features of the TEMIC C51 Family, as

listed below.

Port 0

Port 0 is an 8 bit open drain bi-directional I/O port. Port 0

pins that have 1’s written to them float, and in that state

can be used as high-impedance inputs.

Port 0 is also the multiplexed low-order address and data

bus during accesses to external Program and Data

Memory. In this application it uses strong internal pullups

when emitting 1’s. Port 0 also outputs the code bytes

during program verification in the TSC80C31/80C51.

External pullups are required during program

verification. Port 0 can sink eight LS TTL inputs.

Port Pin

Alternate Function

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

RXD (serial input port)

TXD (serial output port)

INT0 (external interrupt 0)

INT1 (external interrupt 1)

TD (Timer 0 external input)

T1 (Timer 1 external input)

WR (external Data Memory write strobe)

RD (external Data Memory read strobe)

Port 1

Port 1 is an 8 bit bi-directional I/O port with internal Port 3 can sink or source three LS TTL inputs. It can drive

pullups. Port 1 pins that have 1’s written to them are CMOS inputs without external pullups.

pulled high by the internal pullups, and in that state can

be used as inputs. As inputs, Port 1 pins that are externally

being pulled low will source current (IIL, on the data

RST

A high level on this for two machine cycles while the

oscillator is running resets the device. An internal

pull-down resistor permits Power-On reset using only a

sheet) because of the internal pullups.

Port 1 also receives the low-order address byte during

program verification. In the TSC80C31/80C51, Port 1

can sink or source three LS TTL inputs. It can drive

CMOS inputs without external pullups.

capacitor connected to V . As soon as the Reset is

CC

applied (Vin), PORT 1, 2 and 3 are tied to one. This

operation is achieved asynchronously even if the

oscillator does not start-up.

Port 2

ALE

Port 2 is an 8 bit bi-directional I/O port with internal

pullups. Port 2 pins that have 1’s written to them are Address Latch Enable output for latching the low byte of

pulled high by the internal pullups, and in that state can the address during accesses to external memory. ALE is

be used as inputs. As inputs, Port 2 pins that are externally activated as though for this purpose at a constant rate of

being pulled low will source current (ILL, on the data 1/6 the oscillator frequency except during an external

sheet) because of the internal pullups. Port 2 emits the data memory access at which time one ALE pulse is

high-order address byte during fetches from external skipped. ALE can sink/source 8 LS TTL inputs. It can

Program Memory and during accesses to external Data drive CMOS inputs without an external pullup.

Memory that use 16 bit addresses (MOVX @DPTR). In If desired, ALE operation can be disabled by setting bit

this application, it uses strong internal pullups when 0 of SFR location AFh (MSCON). With the bit set, ALE

emitting 1’s. During accesses to external Data Memory is active only during MOVX instruction and external

that use 8 bit addresses (MOVX @Ri), Port 2 emits the fetches. Otherwise the pin is pulled low. MSCON SFR is

contents of the P2 Special Function Register.

set to XXXXXXX0 by reset.

4

MATRA MHS

Rev. E (14 Jan.97)

TSC80C31/80C51

PSEN

XTAL1

Program Store Enable output is the read strobe to external

Program Memory. PSEN is activated twice each machine

cycle during fetches from external Program Memory.

(However, when executing out of external Program

Memory, two activations of PSEN are skipped during

Input to the inverting amplifier that forms the oscillator.

Receives the external oscillator signal when an external

oscillator is used.

each access to external Data Memory). PSEN is not XTAL2

activated during fetches from internal Program Memory.

PSEN can sink or source 8 LS TTL inputs. It can drive

CMOS inputs without an external pullup.

Output of the inverting amplifier that forms the oscillator.

This pin should be floated when an external oscillator is

used.

EA

When EA is held high, the CPU executes out of internal

Program Memory (unless the Program Counter exceeds

3 FFFH). When EA is held low, the CPU executes only out

of external Program Memory. EA must not be floated.

Idle And Power Down Operation

Figure 3. shows the internal Idle and Power Down clock

configuration. As illustrated, Power Down operation

stops the oscillator. Idle mode operation allows the

interrupt, serial port, and timer blocks to continue to

function, while the clock to the CPU is gated off.

PCON : Power Control Register

(MSB)

SMOD

(LSB)

IDL

–

GF1

GF0

PD

These special modes are activated by software via the

Special Function Register, PCON. Its hardware address is

87H. PCON is not bit addressable.

Symbol

Position

Name and Function

SMOD

PCON.7

Double Baud rate bit. When set to

a 1, the baud rate is doubled when

the serial port is being used in

either modes 1, 2 or 3.

Figure 3. Idle and Power Down Hardware.

–

GF1

GF0

PD

PCON.6

PCON.5

PCON.4

PCON.3

PCON.2

PCON.1

(Reserved)

General-purpose flag bit.

Power Down bit. Setting this bit

activates power down operation.

Idle mode bit. Setting this bit

activates idle mode operation.

IDL

PCON.0

If 1’s are written to PD and IDL at the same time. PD

takes, precedence. The reset value of PCON is

(000X0000).

Idle Mode

The instruction that sets PCON.0 is the last instruction There are three ways to terminate the Idle mode.

executed before the Idle mode is activated. Once in the Activation of any enabled interrupt will cause PCON.0 to

Idle mode the CPU status is preserved in its entirety : the be cleared by hardware, terminating Idle mode. The

Stack Pointer, Program Counter, Program Status Word, interrupt is serviced, and following RETI, the next

Accumulator, RAM and all other registers maintain their instruction to be executed will be the one following the

data during idle. Table 1 describes the status of the instruction that wrote 1 to PCON.0.

external pins during Idle mode.

MATRA MHS

5

Rev. E (14 Jan.97)

TSC80C31/80C51

The flag bits GF0 and GF1 may be used to determine The second way of terminating the Idle mode is with a

whether the interrupt was received during normal hardware reset. Since the oscillator is still running, the

execution or during the Idle mode. For example, the hardware reset needs to be active for only 2 machine

instruction that writes to PCON.0 can also set or clear one cycles (24 oscillator periods) to complete the reset

or both flag bits. When Idle mode is terminated by an operation.

enabled interrupt, the service routine can examine the

status of the flag bits.

Power Down Mode

The instruction that sets PCON.1 is the last executed prior Table 1 describes the status of the external pins while in

to entering power down. Once in power down, the the power down mode. It should be noted that if the power

oscillator is stopped. The contents of the onchip RAM and down mode is activated while in external program

the Special Function Register is saved during power down memory, the port data that is held in the Special Function

mode. The hardware reset initiates the Special Fucntion Register P2 is restored to Port 2. If the data is a 1, the port

Register. In the Power Down mode, VCC may be lowered pin is held high during the power down mode by the

to mi-nimize circuit power consumption. Care must be strong pullup, T1, shown in Figure 4.

taken to ensure the voltage is not reduced until the power

down mode is entered, and that the voltage is restored

before the hardware reset is applied which freezes the

oscillator. Reset should not be released until the oscillator

has restarted and stabilized. A hardware reset is the only

way of exiting the power down mode.

Table 1. Status of the external pins during idle and power down modes.

MODE

Idle

PROGRAM MEMORY

ALE

PSEN

PORT0

Port Data

Floating

Port Data

Floating

PORT1

Port Data

PORT2

Port Data

Address

PORT3

Port Data

Internal

External

Internal

External

1

0

1

0

Idle

Power Down

Port Data

Stop Clock Mode

Due to static design, the TSC80C31/80C51 clock speed

can be reduced until 0 MHz without any data loss in

memory or registers. This mode allows step by step

utilization, and permits to reduce system power

consumption by bringing the clock frequency down to

any value. At 0 MHz, the power consumption is the same

as in the Power Down Mode.

Figure 4. I/O Buffers in the TSC80C31/80C51 (Ports

1, 2, 3).

I/O Ports

The I/O buffers for Ports 1, 2 and 3 are implemented as

shown in Figure 4.

6

MATRA MHS

Rev. E (14 Jan.97)

TSC80C31/80C51

When the port latch contains a 0, all pFETS in Figure 4.

When an I/O pin son Ports 1, 2, or 3 is used as an input,

are off while the nFET is turned on. When the port latch the user should be aware that the external circuit must

makes a 0-to-1 transition, the nFET turns off. The strong sink current during the logical 1-to-0 transition. The

pFET, T1, turns on for two oscillator periods, pulling the maximum sink current is specified as ITL under the D.C.

output high very rapidly. As the output line is drawn high, Specifications. When the input goes below

pFET T3 turns on through the inverter to supply the IOH approximately 2 V, T3 turns off to save ICC current. Note,

source current. This inverter and T form a latch which when returning to a logical 1, T2 is the only internal

holds the 1 and is supported by T2.

pullup that is on. This will result in a slow rise time if the

user’s circuit does not force the input line high.

When Port 2 is used as an address port, for access to

external program of data memory, any address bit that

contains a 1 will have his strong pullup turned on for the

entire duration of the external memory access.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output respectively, To drive the device from an external clock source,

of an inverting amplifier which is configured for use as an XTAL1 should be driven while XTAL2 is left

on-chip oscillator, as shown in Figure 5. Either a quartz unconnected as shown in Figure 6. There are no

crystal or ceramic resonator may be used.

requirements on the duty cycle of the external clock

signal, since the input to the internal clocking circuitry is

through a divide-by-two flip-flop, but minimum and

maximum high and low times specified on the Data Sheet

must be observed.

Figure 5. Crystal Oscillator.

Figure 6. External Drive Configuration.

TSC80C51 with Secret ROM

TEMIC offers TSC80C31/80C51 with the encrypted

secret ROM option to secure the ROM code contained in

the TSC80C31/80C51 microcontrollers.

–

Everytime a byte is addressed during a verify of the

ROM content, a byte of the encryption array is

selected.

MOVC instructions executed from external program

memory are disabled when fetching code bytes from

internal memory.

The clear reading of the program contained in the ROM

is made impossible due to an encryption through several

random keys implemented during the manufacturing

process.

EA is sampled and latched on reset, thus all state

modification are disabled.

The keys used to do such encryption are selected

randomwise and are definitely different from one For further information please refer to the application

microcontroller to another.

note (ANM053) available upon request.

This encryption is activated during the following phases :

MATRA MHS

7

Rev. E (14 Jan.97)

TSC80C31/80C51

TSC80C31/80C51 with Secret TAG

TEMIC offers special 64-bit identifier called “SECRET This Secret Tag option can be read-out by a software

TAG” on the microcontroller chip.

routine and thus enables the user to do an individual

identity check per device. This routine is implemented

inside the microcontroller ROM memory in case of

masked version which can be kept secret (and then the

value of the Secret Tag also) by using a ROM Encryption.

The Secret Tag option is available on both ROMless and

masked microcontrollers.

The Secret Tag feature allows serialization of each

microcontroller for identification of

equipment. A unique number per device is implemented

in the chip during manufacturing process. The serial

number is a 64-bit binary value which is contained and

addressable in the Special Function Registers (SFR) area.

a

specific

For further information, please refer to the application

note (ANM031) available upon request.

8

MATRA MHS

Rev. E (14 Jan.97)

TSC80C31/80C51

Electrical Characteristics

* Notice

Absolute Maximum Ratings*

Stresses at or above those listed under “ Absolute Maximum Ratings”

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions may affect

device reliability.

Ambiant Temperature Under Bias :

C = commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

I = industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C

Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V

Voltage on Any Pin to VSS . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V

CC

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W**

** This value is based on the maximum allowable die temperature and

the thermal resistance of the package

DC Parameters

TA = 0°C to 70°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 44 MHz

TA = –40°C + 85°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 44 MHz

Symbol

Parameter

Min

Typ (3)

Max

Unit

Test Conditions

VIL

VIH

Input Low Voltage

– 0.5

0.2 Vcc + 0.9

0.7 Vcc

0.2 Vcc – 0.1

Vcc + 0.5

V

Input High Voltage (Except XTAL and RST)

Input High Voltage (for XTAL and RST)

Output Low Voltage (Port 1, 2 and 3) (4)

VIH1

VOL

Vcc + 0.5

0.3

0.45

1.0

V

IOL = 100 µA

IOL = 1.6 mA (2)

IOL = 3.5 mA

VOL1 Output Low Voltage (Port 0, ALE, PSEN) (4)

0.3

0.45

1.0

V

IOL = 200 µA

IOL = 3.2 mA (2)

IOL = 7.0 mA

VOH

Output High Voltage Port 1, 2, 3

Vcc – 0.3

Vcc – 0.7

Vcc – 1.5

V

IOH = – 10 µA

IOH = – 30 µA

IOH = – 60 µA

VCC = 5 V ± 10 %

VOH1 Output High Voltage (Port 0, ALE, PSEN)

Vcc – 0.3

Vcc – 0.7

Vcc – 1.5

V

IOH = – 200 µA

IOH = – 3.2 mA

IOH = – 7.0 mA

VCC = 5 V ± 10 %

IIL

ILI

Logical 0 Input Current (Ports 1, 2 and 3)

Input leakage Current

– 50

± 10

– 650

30

µA

Vin = 0.45 V

0.45 < Vin < Vcc

Vin = 2.0 V

ITL

IPD

Logical 1 to 0 Transition Current (Ports 1, 2 and 3)

Power Down Current

5

µA Vcc = 2.0 V to 5.5 V (1)

KW

RRST RST Pulldown Resistor

50

90

200

10

CIO

ICC

Capacitance of I/O Buffer

pF

fc = 1 MHz, Ta = 25_C

Vcc = 5.5 V

Power Supply Current

Freq = 1 MHz Icc op

Icc idle

Freq = 6 MHz Icc op

0.7

0.5

4.2

1.4

1.8

1

9

mA

Icc idle

3.5

Freq ≥ 12 MHz Icc op max = 0.9 Freq (MHz) + 5

Icc idle max = 0.3 Freq (MHz) + 1.7

Freq ≤ 20 MHz Icc op typ = 0.7 Freq (MHz)

Freq ≥ 20 MHz Icc op typ = 0.5 Freq (MHz) + 4

Freq ≤ 20 MHz Icc idle typ = 0.16 Freq (MHz) + 0.4

Freq ≥ 20 MHz Icc idle typ = 0.12 Freq (MHz) + 1.2

MATRA MHS

9

Rev. E (14 Jan.97)

TSC80C31/80C51

** This value is based on the maximum allowable die temperature and

the thermal resistance of the package

Absolute Maximum Ratings*

Ambient Temperature Under Bias :

* Notice

A = Automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C

Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V

Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W**

Stresses above those listed under “ Absolute Maximum Ratings” may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

DC Parameters

TA = –40°C + 125°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 40 MHz

Symbol

VIL

Parameter

Min

– 0.5

Typ (3)

Max

Unit

V

Test Conditions

Input Low Voltage

0.2 Vcc – 0.1

Vcc + 0.5

VIH

Input High Voltage (Except XTAL and RST)

Input High Voltage (for XTAL and RST)

Output Low Voltage (Port 1, 2 and 3) (4)

0.2 Vcc + 0.9

0.7 Vcc

V

VIH1

VOL

V

0.3

0.45

1.0

V

IOL = 100 µA

IOL = 1.6 mA (2)

IOL = 3.5 mA

VOL1 Output Low Voltage (Port 0, ALE, PSEN) (4)

0.3

0.45

1.0

V

IOL = 200 µA

IOL = 3.2 mA (2)

IOL = 7.0 mA

Vcc – 0.3

Vcc – 0.7

Vcc – 1.5

V

IOH = – 10 µA

IOH = – 30 µA

VOH

Output High Voltage Port 1, 2 and 3

IOH = – 60 µA

VCC = 5 V ± 10 %

Vcc – 0.3

Vcc – 0.7

Vcc – 1.5

V

IOH = – 200 µA

VOH1 Output High Voltage (Port 0, ALE, PSEN)

IOH = – 3.2 mA

IOH = – 7.0 mA

VCC = 5 V ± 10 %

IIL

ILI

Logical 0 Input Current (Ports 1, 2 and 3)

Input leakage Current

– 75

±10

– 750

75

µA Vin = 0.45 V

µA 0.45 < Vin < Vcc

µA Vin = 2.0 V

ITL

Logical 1 to 0 Transition Current (Ports 1, 2 and 3)

Power Down Current

IPD

RRST

CIO

ICC

5

µA Vcc = 2.0 V to 5.5 V (1)

KW

RST Pulldown Resistor

50

90

200

10

Capacitance of I/O Buffer

pF fc = 1 MHz, Ta = 25_C

Power Supply Current

Vcc = 5.5 V

Freq = 1 MHz Icc op

Icc idle

Freq = 6 MHz Icc op

0.7

0.5

4.2

1.4

1.8

1

9

mA

Icc idle

3.5

Freq ≥ 12 MHz Icc op max = 0.9 Freq (MHz) + 5

Icc idle max = 0.3 Freq (MHz) + 1.7

Freq ≤ 20 MHz Icc op typ = 0.7 Freq (MHz)

Freq ≥ 20 MHz Icc op typ = 0.5 Freq (MHz) + 4

Freq ≤ 20 MHz Icc idle typ = 0.16 Freq (MHz) + 0.4

Freq ≥ 20 MHz Icc idle typ = 0.12 Freq (MHz) + 1.2

10

MATRA MHS

Rev. E (14 Jan.97)

TSC80C31/80C51

** This value is based on the maximum allowable die temperature and

the thermal resistance of the package

Absolute Maximum Ratings*

Ambient Temperature Under Bias :

* Notice

M = Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C