U3770M [TEMIC]

CT2 I/Q Modulator and Clock Circuitry; CT2的I / Q调制器和时钟电路
U3770M
型号: U3770M
厂家: TEMIC SEMICONDUCTORS    TEMIC SEMICONDUCTORS
描述:

CT2 I/Q Modulator and Clock Circuitry
CT2的I / Q调制器和时钟电路

射频调制器 射频解调器 微波调制器 微波解调器 射频和微波 时钟
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U3770M  
CT2 I/Q Modulator and Clock Circuitry  
Description  
U3770M is a quadrature modulator realized with with TEMIC’s PLL IC U2783B and the GaAs front end  
MATRA MHS’ advanced 0.8 micron CMOS process. U7001BG, a complete CT2 chip set is available.  
The IC is especially designed for CT2 application  
in conjunction with TEMIC’s RF/IF signal processor  
Electrostatic sensitive device.  
Observe precautions for handling.  
U2760B  
and  
a
CT2  
baseband  
controller  
TM  
(i.e., AMD PhoX controller Am79C4xx). Together  
Features  
Programmable 0.8/1.6 MHz quadrature modulated  
carrier generation  
Supply voltage range 2.7 to 3.3 V  
Low power consumption, typical 12 mW  
SO16 package or die form  
More than 26 dB LO and sideband suppression  
18.432 MHz CMOS level clock generation  
Block Diagram  
R
Ref in  
12.8 MHz  
LF  
95 9881  
11  
2
14  
CLK out  
Phase  
comparator  
VCO  
DIV / 25  
512 kHz  
Amp.  
DIV / 36  
512 kHz  
18.432 MHz  
3
VDD  
DGND  
AGND  
PROG  
TST  
4
DIV / 2  
or  
DIV / 4  
6.4 MHz  
3.2 MHz  
13  
12  
10  
Dual DFF  
9
MOD out  
6
5
Q
in  
in  
in  
QB  
8
7
I
IB  
in  
1, 15, 16  
DNC  
Figure 1. Block diagram  
MATRA MHS  
1 (5)  
Rev. A2, 03-Dec-97  
U3770M  
Functional Description  
U3770M has been designed to reduce power consumption reference oscillator. This way, only one crystal oscillator  
and cost of CT2 devices. An innovative CMOS I,Q modu- is needed in the complete CT2 device.  
lator with an extremely low current provides all the  
Internally, the 12.8 MHz reference signal is fed into a  
advantages of I,Q modulation:  
shaping amplifier and then into two logic dividers, to gen-  
No requirement for FM deviation tuning  
Eliminates the Gaussian filter  
erate a 512 kHz and a programmable 3.2 or 6.4 MHz  
clock. This clock is divided by 4 by two D flip-flops. The  
flip-flop outputs drive the four analog switches in quadra-  
ture. A pair of analog switches make a local oscillator  
(LO) suppression mixer. By summing the other pair out-  
puts, we obtain both LO and sideband suppression, of  
more than –26 dBc.  
Simplifies the power ramping control  
The modulated output carrier can be programmed to be  
0.8 MHz or 1.6 MHz by the PROG control pin.  
The typical supply voltage is 3 V @ 4 mA.  
The 512 kHz clock drives a frequency synthesizer. The  
To reduce overall system cost, an internal PLL generates VCO runs at a fixed frequency of 18.432 MHz. The VCO  
a 18.432 MHz clock signal from the system 12.8 MHz control voltage (LF pin) controls the VCO frequency.  
Pin Description  
Pin  
2
Symbol  
Function  
External 12.8 MHz reference  
frequency input  
DNC  
DNC  
DNC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
F
Ref in  
3
4
5
6
7
8
9
10  
VDD  
Supply voltage  
F
Ref in  
DGND Digital ground  
QB  
Analog switches input  
Analog switches input  
Analog switches input  
Analog switches input  
Modulator output signal  
Test input, must be connected to  
GND (only factory use)  
PLL loop filter  
in  
VDD  
CLK  
out  
Q
in  
IB  
in  
DGND  
AGND  
I
in  
MOD  
out  
TST  
QB  
Q
PROG  
LF  
11  
12  
LF  
PROG  
PROG = 0, 1.6 MHz mode  
PROG = 1, 0.8 MHz mode  
IB  
I
TST  
13  
14  
AGND Analog ground  
CLK  
Digital CMOS clock output  
18.432 MHz  
out  
MOD  
out  
1, 15,  
16  
DNC  
Do not connect  
95 9930  
Figure 2. Pinning  
2 (5)  
MATRA MHS  
Rev. A2, 03-Dec-97  
U3770M  
Absolute Maximum Ratings  
Stresses at or above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the  
device at these or any other conditions above those indicated in this data sheet is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
Parameters  
Symbol  
V
DD  
Value  
6
Unit  
V
Supply voltage  
Modulator input voltages  
I
IB  
Q
QB  
–0.5 to V  
V
DD  
DD  
Reference frequency input  
Ambient temperature  
Storage temperature  
F
T
T
–0.5 to V  
V
Ref in  
–40 to +85  
–65 to +150  
°C  
°C  
°C  
amb  
stg  
Junction temperature  
T
T < T  
+10  
j
j
amb  
Operating Range  
Parameters  
Symbol  
Value  
10%  
–5 to +70  
T < T +5  
Unit  
V
°C  
°C  
°C  
Supply voltage  
V
DD  
3
Ambient temperature  
Junction temperature  
Storage temperature  
T
amb  
T
j
j
amb  
T
stg  
–40 to +125  
Electrical Characteristics  
Test conditions (unless otherwise specified) related to test circuit  
V = 3 V, V  
V
and V , V  
= 1 V single ended, oscillator frequency F  
= 12.8 MHz, T = –5 to +70°C  
amb  
S
BIi, BIi  
BQi BQi  
PP  
Ref in  
Parameters  
Test Conditions / Pins  
Symbol  
Min.  
2.7  
Typ.  
Max.  
3.3  
Unit  
V
mA  
Supply voltage range  
Supply current  
Pin 3  
Pin 3  
Pin 2  
V
3
4
DD  
DD  
I
F
Ref in  
Input voltage  
Input impedance  
I, Q inputs  
V
150  
100  
mV  
k
F Ref in  
Z
F Ref in  
PP  
Pins 5, 6, 7 and 8  
Input voltage  
Single ended  
Single ended  
V
Z
F
1
V
k
kHz  
V
Iin, Qin  
Iin, Qin  
Iin, Qin  
PP  
Input impedance  
Input frequency  
External bias voltage  
20  
18  
1.5  
V
IB, QB  
MOD  
Output level  
Pin 9  
out  
1)  
Unloaded  
V
70  
–26  
mVRMS  
dBc  
Mod out  
LO and sideband suppres-  
sion  
LO sub  
SB sub  
Output impedance  
Z
5
k
Mod out  
CLK  
Pin 14  
out  
Output frequency  
Output voltage swing  
F
V
18.432  
MHz  
V
CLK out  
@ load = 20 pF  
1.8  
CLK out  
1)  
Note  
The output signal contains some harmonics, to be filtered by an external low-pass filter  
MATRA MHS  
3 (5)  
Rev. A2, 03-Dec-97  
U3770M  
Test Circuit  
47 nF  
4.7 nF  
LF  
22  
11  
RRef in  
12.8 MHz  
2
95 9967  
14  
Phase  
comparator  
DIV / 25  
VCO  
512 kHz  
CLK out  
3
Amp  
DIV / 36  
512 kHz  
18.432 MHz  
VDD  
4
DGND  
13  
DIV / 2  
or  
DIV / 4  
6.4 MHz  
3.2 MHz  
AGND  
12  
Dual DFF  
PROG  
10  
TST  
9
MOD out  
6
5
8
7
IB in  
QB in  
1 k  
Q in  
I in  
1 nF  
1 nF  
1 nF  
1 nF  
1 k  
1 k  
1 k  
Figure 3. Test circuit  
4 (5)  
MATRA MHS  
Rev. A2, 03-Dec-97  
U3770M  
Package Information  
Package: SO16  
We reserve the right to make changes to improve technical design and may do so without further notice.  
Parameters can vary in different applications. All operating parameters must be validated for each customer  
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized  
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,  
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or  
unauthorized use.  
TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany  
Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423  
MATRA MHS  
5 (5)  
Rev. A2, 03-Dec-97  

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