U3900BM-AFN [TEMIC]
Programmable Telephone Audio Processor; 程控电话音频处理器
| 型号： | U3900BM-AFN |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Programmable Telephone Audio Processor |
| 文件： | 总34页 (文件大小：754K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U3900BM
Programmable Telephone Audio Processor
Description
The programmable telephone audio processor U3900BM adaptation to the line. The U3900BM can also be supplied
is a linear integrated circuit for use in feature phones, via an external power supply. An integrated voice switch
answering machines, fax machines and cordless phones. with loudspeaker amplifier enables hands-free or loud-
It contains the speech circuit, tone-ringer interface with hearing operation. With an anti-feedback function,
DC/DC converter, sidetone equivalent and ear-protection acoustical feedback during loudhearing can be reduced
rectifiers. The circuit is line-powered and contains all significantly. The generated supply voltage is suitable for
components necessary for signal amplification and a wide range of peripheral circuits.
Features
Benefits
Speech circuit with anti-clipping
Savings of one piezoelectric transducer
Tone ringer interface with DC/DC converter
Speaker amplifier with anti-distortion
Complete system integration of analog signal
processing on one chip
Power-supply management, regulated, unregulated
and a special supply for electret microphone
Very few external components
Voice switch
Highly integrated solution
CLID + SCWID
DTMF generator
Switch matrix
Extremely versatile due to full programmability
Applications
Line current information
Fully programmable
Watchdog
Feature phone, answering machine, fax machine, speaker
phone, base station of cordless phone
Speech
circuit
Voice
switch
Audio
amplifier
Clock
Data
Serial
bus
DTMF
MCU
Reset
Tone
ringer
Class
14602
Ordering Information
Extended Type Number
U3900BM-AFN
U3900BM-AFNG3
Package
SSO44
SSO44
Remarks
Taped and reeled
Rev. A2, 25-Aug-98
1 (34)
Target Specification
U3900BM
Pin Description
Pin Symbol
Function
Input of A/D converter
1
44
43
42
41
40
39
38
37
SAO1
TSACL
MIC2
11
12
13
ADIN
CLI2
CLI1
2
SAO2
CLID input 2
CLID input 1
3
4
GND
VB
MIC1
VMIC
14 VRING Input for ringer supply
5
ES
MIC3
15
16
IMPA
Input for adjusting the ringer input impedance
COSC 70-kHz oscillator for ringing power converter
6
VMPS
SENSE
VL
TXACL
RECO2
RECO1
TLDR
17 SWOUT Output for driving the external switching
transistor
7
8
18
VMP
Regulated output voltage for supplying the
microcontroller (typ. 3.3 V/ 6 mA in speech
mode)
IND
9
36
35
34
33
32
31
30
29
28
27
26
25
RECIN
10
11
12
13
14
15
16
INLDR
INLDT
19
20
21
22
INT
BCL
BDA
Interrupt line for serial bus
Clock input for serial bus
Data line for serial bus
ADIN
CLI2
TLDT
HFTX
CEAR
CMIC
AMREC
AMPB
STO
OSCIN Input for 3.58-MHz oscillator
CLI1
23 OSCOUT Clock output for the microcontroller
24 RESET Reset output for the microcontroller
VRING
IMPA
COSC
25
26
27
28
STC
STRC
STO
Input for sidetone network
Input for sidetone network
Output for connecting the sidetone network
SWOUT
VMP
17
18
19
20
AMPB Input for playback signal of answering
machine
INT
STRC
STC
29 AMREC Output for recording signal of answering
machine
BCL
30
31
32
CMIC Input for cordless telephone
CEAR Output for cordless telephone
BDA
21
22
24
23
RESET
OSCOUT
OSCIN
HFTX Output for transmit-level detector in intercom
mode
14761
33
34
TLDT Time constant of transmit-level detector
INLDT Input of transmit-level detector
Figure 1. Pinning
Function
Pin Symbol
35 INLDR Input of receive-level detector
36 TLDR Time constant of receive-level detector
1
2
3
SAO1
SAO2
GND
Positive output of speaker amplifier
(single ended and push-pull operation)
37 RECO1 Positive output of the receive amplifier, also
used for sidetone network
Negative output of speaker amplifier
(push-pull only)
38 RECO2 Negative output of the receive amplifier
Ground, reference point for DC- and
AC signals
39 TXACL Time-constant adjustment for transmit anti-
clipping
4
5
6
VB
ES
Unstabilized supply voltage
40
41
MIC3
Input of hands-free microphone
Input for external supply indication
VMIC Reference node for microphone amplifier,
supply for electret microphone
VMPS Unregulated supply voltage for the micro-
controller (via series regulator to VMP)
42
43
MIC1
Inverting input of symmetrical microphone
amplifier with high common-mode rejection
ratio
7
8
SENSE Input for sensing the available line current
VL
Positive supply-voltage input to the device in
speech mode
MIC2
Non-inverting input of symmetrical micro-
phone amplifier with high common-mode
rejection ratio
9
IND
The internal equivalent inductance of the
circuit is proportional to the value of the
capacitor at this pin. A resistor connected to
ground may be used to adjust the DC mask.
44 TSACL Time-constant for speaker amplifier anti-
clipping
10
RECIN Receive amplifier input
2 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Table of Contents
1
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 CLID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
5
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carrier Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Recovery and Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLID: Logical Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carrier Detect, Bandpass Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Carrier Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
5
5
6
6
6
6
6
2.1.8
7
2.2
SCWID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Guard Time, Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Up Guard Time, Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Early Guard Time, Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Down Guard Time, Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wetting Pulse Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCWID: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAS Detect Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7
8
8
8
9
9
10
10
12
12
12
13
13
13
13
14
14
18
18
20
21
22
24
26
26
26
26
33
3
4
DC Line Interface and Supply-Voltage Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Supply Structure of the Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ringing Power Converter (RPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Ringing Frequency Detector (RFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
6
Clock Output Divider Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Melody – Confidence Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
8
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acoustic Feedback Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sidetone System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
10
11
12
13
14
14.1
14.2
14.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. A2, 25-Aug-98
3 (34)
Target Specification
VL
39
25 26 10
27
8
7
9
41
6
TXACL
42
43
40
Power
supply
18
STBAL
4
3
AGATX
MICRO
AGARX
TXA
VMIC
11
17
DTMF/
melody
Offset
Offset
30
32
28
Filter
canceler
canceler
16
14
15
Ringing
power
converter
MUX
ADC
VRING
AMPB CMIC LRX
DTMF
MIC
Switch matrix
LIDET VMP RFDO
POR
AMREC CEAR EPO RXLS
LTX
29
31
AGC
RA
REG
Filters
TIP
37
13
12
DIV.
1/8/16/32
AFS
control
CLID
BIDIR
serial
bus
38
44
SACL
SA
OSC.
3.58 MHz
RING
1
2
35 36 33 34
20 21 19
22
23 5 24
14604
C
VMP
RECO1
TXOUT
U3900BM
2 Class Function
The U3900BM includes a class function Calling Line a capture window (see the tables next page), and avoid a
IDentification (CLID) for on-hook and Spontaneous Call false detection.
Waiting IDentifier (SCWID) for off-hook status.
With the use of SCD bit the carrier detect function is
improved, because after a normal carrier detection
(NCD), a part (10 bits) of the channel seizure is taken in
2.1 CLID
count before alerting the microprocessor.
CLID is designed to demodulate CCITT V23 and BELL
202 (1200 bauds FSK asynchronous data) and is
compatible with both formats without external
intervention. It fulfils the CS B14-10W requirements.
Note:
When the CPE is off hook (SCWID mode) the CO sends
FSK
data
without
channel
seizure.
The
mark signal = 80 bits ±10 at 1200 bauds (1300 Hz con-
tinuously during 67 ms).
The main feature of this part is to provide, for the user,
information about the caller before answering the call.
The information is a DATA message sent from the Central
Office (CO) to the CPE during the silent interval, and
after the first ringing burst.
For this case a selected bandpass 1000 Hz to 1700 Hz
could be very useful for the carrier detect ...
After the interrupt due to the carrier detect the micro-
processor can change the bandpass frequencies according
to the FSK band.
2.1.1
Description
On the receive side, the received signal coming from
CLI1 and CLI2 first goes to an antialiasing filter after the
differential op-amp.
The normal carrier detect guard time is 26.4 ms.
The improved carrier detect guard time is 34.7 ms.
The carrier lost guard time is 8.8 ms, in all the cases.
The next section is a bandpass filter composed of an FSK
filter composed of a fifth order high-pass followed by a
third order low-pass filter. The low-pass and high-pass
cut-off frequencies are about 300 Hz and 3400 Hz
respectively.
2.1.3
Demodulator
This part is enabled with the carrier detect signal.
The reference signal is at 1700 Hz, (the same frequency
for BELL 202 and V23). All the incoming signals are
compared to this value to make a digital square wave
frequency varying in frequency and in phase as a function
of the input frequencies.
2.1.2
Carrier Detect
The carrier detect provides an indication (to the micro-
processor with an interrupt request) of the presence of a
signal in the FSK band. It detects a sufficient amplitude
signal at the output of the FSK bandpass filter.
2.1.4
Clock Recovery
Note that signals such as speech or DTMF tones also lie
in the FSK frequency band and the carrier detect may be
activated by these signals. The signals will be
demodulated and presented as DATA. To avoid false
DATA detection, a command bit is used to disable the
demodulator when no FSK signal is expected.
The process starts at the first low-level bit received from
the demodulator. After that the CLOCK is generated for
the 10 serial bits (1 bit start, 8 bits data, 1 bit stop).When
all the data are received DATA READY is generated. This
signal loads the serial data in a parallel buffer.
DATA READY provides an indication (to the micro-
processor with an interrupt request) of the presence data
byte available.
Four bits are provided to improve carrier detection
[CD_CD <3..0>]. With these bits it is possible to select
Rev. A2, 25-Aug-98
5 (34)
Target Specification
U3900BM
2.1.5
Data Recovery and Buffer
The incoming serial data are stored and sent to the SSB is generated, the INT pin will become active, and data
each 10 bits (1 start bit, 8 data, 1 stop bit ). When after a ready interrupt bit is set in the status register (bit 3). The
start bit 8 data bits and a stop bit are received, an interrupt received data is available in the CLID DATA register.
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
DATA
INT pin
14605
Figure 3. Interrupt treatment for SLID DATA register
2.1.6
CLID: Logical Part
Command bit SCD
from serial bus
Command bits
CD_CD < 3...0 >
from serial bus
CD
NCD
FSK
signal
Data recovery
and
DATA
DR
Carrier
detect
buffer
Serial
data
Clock
Data ready
Clock
recovery
Demodulator
From/to
14606
demodulator analog filter
Figure 4. Block diagram for CLID logical part
2.1.7
Carrier Detect, Bandpass Frequencies
Low Frequencies
High Frequencies
CD_CD<0>
CD_CD<1>
Value
290 Hz
515 Hz
770 Hz
1000 Hz
CD_CD<2>
CD_CD<3>
Value
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
3400 Hz
3100 Hz
2665 Hz
1700 Hz
6 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
2.1.8
Special Carrier Detect
If SCD = 0 Detect guard time = 26.4 ms
If SCD = 1 Detect guard time = 34.7 ms (26.4 ms + 10 bits of the channel seizure)
FSK signal
Channel seizure: 010101...
SCD = 0 SCD = 1
Mark: 1111...
Clid Data
Carrier detect
(Interrupt)
Carrier lost
26.4 ms
8.3 ms
8.8 ms
14077
Figure 5. Timing diagram for carrier detect in CLID mode
2.2 SCWID
CAS detector should also be immune to imitation from
near and far end speech.
Mark: 1111...
Clid Data
FSK signal
Carrier lost
Note that the term “near end” refers to the end of the
telephone connection receiving the caller ID service, “far
end” refers to the other end of the connection, the Central
Office (CO).
Carrier detect
(Interrupt)
ncd (SCWID)
26.4 ms
8.8 ms
14078
There are two aspects of speech immunity: talk-off and
talk-down.
Figure 6. Timing diagram for carrier detect in SCWID mode
Talk-off is the condition where signals are falsely
detected because of imitation by speech or music. An
imitation can be caused from the far end or the near end.
The Spontaneous Call Waiting IDentifier (SCWID) part
is designed to meet:
Talk-down is the condition where signals are missed
because of interference from speech or music.
The Bellcore “Customer Premises Equipment
Alerting Signal (CAS)”: TR-NWT-000030
&
SR-TSV-002476 specifications.
A CAS can be talked down only from the near end
because the far end has already been muted by the CO.
The British Telecom “Idle State Tone Alert Signal”:
SIN227 & SIN242 specifications.
2.2.2
Description
The European Telecommunication Standard: ETS300
778-1 & ETS300 778-2 specifications.
The SCWID part is a complete dual-tone receiver
designed to detect the two frequencies 2750 Hz and
2130 Hz dedicated for this alerting function. An output
interrupt is provided to the microprocessor when
detecting the alert signal.
2.2.1
Overview
SCWID is a feature that allows a subscriber who is
already engaged in a telephone call to receive caller ID
information about an incoming call.
This device part provides all necessary filtering without
any external component.
The on-chip filtering provides excellent signal-to-noise
performance.
The European Telecommunication Standard specifies
Dual-Tone Alerting Signal (DT-AS) for off-line data
transmission (on-hook) and on-line data transmission
(off-hook).
The dual-tone alert signal is divided into a high and a low
bandpass switched capacitor filters:
The British Telecom caller ID uses a Idle State Tone Alert
Signal in on-hook mode.
The high alert filter is a 2750 Hz bandpass design,
with a notch placed at 2130 Hz for low frequency
rejection.
Bellcore specifies a Dual-Tone Alert Signal called CPE
Alerting Signal (CAS) for use in off-hook data
transmission. Bellcore states that the CPE should be able
to detect the CAS in the presence of near end speech. The
The low alert filter is a 2130 Hz bandpass design, with
a notch placed at 2750 Hz for high frequency
rejection.
Rev. A2, 25-Aug-98
7 (34)
Target Specification
U3900BM
The filter outputs are smoothed and then limited by high-
gain comparators which have hysteresis to reduce
sensitivity to unwanted low-level signals, jitter and noise.
The outputs of the comparators are square-wave signals.
2.2.4
Up Guard Time, Description
The up guard time circuitry prevents false detection from
speech or music (talk-off).
The input signal (both 2130 Hz and 2750 Hz) must be
continuously high for a duration depending on the
2 programmable bits UGT0 and UGT1.
The two resulting rectangular waves are applied to the
digital circuitry where a counting algorithm measures and
averages their periods. This averaging prevents dual-tone
SCWID simulation by extraneous signals such as voice.
DGT0
DGT1
UGT Value
20 ms
0
1
0
1
0
0
1
1
25 ms
The averaging algorithm has been optimized to provide
excellent immunity to “talk-off” and tolerance to the
presence of interfering frequencies (third tones) and
noise.
30 ms
35 ms
If a drop occurs at any time before the selected value, the
detection system is cleared.
When both digital circuitries simultaneously detect a
valid tone (2130 Hz and 2750 Hz), the signal applied at
the guard-time block goes high. Should the alert tone
signal be lost, the input signal at the guard-time block will
go low.
Nevertheless, there is the possibility to improve such a
system using early guard time circuitry.
2.2.5
Early Guard Time, Description
The early guard time system, when enabled, helps the up
guard time to detect a CAS signal even if there are drops
in it. But there are conditions before validating such a
polluted signal.
2.2.3
Guard Time, Overview
The input signal (both 2130 Hz and 2750 Hz) must be
continuously high for duration depending on the
2 programmable bits EGT0 and EGT1.
To prevent false detection due to talk-off effects and to
detect real CAS signals even with drops, a guard-time
system is necessary. A guard-time system improves the
detection performance and verifies that the duration of a
valid signal is sufficient before alerting the
microprocessor with an interrupt. It rejects detection of
insufficient duration (up guard time) and mask dropouts
(down guard time).
EGT0
EGT1
EGT Value
Disabled
8.5 ms
0
1
0
1
0
0
1
1
10.3 ms
13.7 ms
After that, the input signal is filtered and a drop can occur
without clearing the system if it is not too long . The
maximum time value depends on the command filter bit
FFD.
There are nine bits for controlling the guard-time block:
2 bits, EGT0 and EGT1, for controlling the early
guard time
FFD
Filter Value
(Maximum Drop Duration)
2 bits, UGT0 and UGT1, for controlling the up guard
time
0
1
2 ms
4 ms
2 bits, DGT0 and DGT1, for controlling the down
guard time
If there are too many drops, the system is cleared. The
count of drops admitted depends on the command count
bit FDC.
1 bit, FFD, for controlling the width filter
1 bit, FDC, for controlling the drops count
FDC
Count Value
(Maximum Drop Count)
0
1
4
3
1 bit, WP, for enabling the wetting pulse function
One bit is dedicated for enabling the SCWID part.
The early guard time with filter and count drops allow a
good compromise to achieve talk-off and talk-down
immunity.
8 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
2.2.6
Down Guard Time, Description
2.2.7
Wetting Pulse Function
The down guard time circuitry prevents drops from
speech or music (talk-down).
The input signal (both 2130 Hz and 2750 Hz) must be
continuously low for a duration depending on the
2 programmable bits DGT0 and DGT1.
British Telecom states that the TE is required to apply a
DC wetting pulse and an AC load 205 ms after the end of
the alerting signal (the Idle State* Tone Alert Signal); the
duration of the wetting pulse is 151 ms; the TE shall rise
to a minimum of 25 mA and maintain that current for a
total time of not less than 5 ms.
The early guard time is used like for up guard time, but
the drop counter is not activated.
OCTEL3 provides a 15-ms counter (which starts at the
end of the alerting signal delayed by the down guard time
value) to help the microprocessor to fulfil this
requirement.
* Note:
The Idle State is an electrical condition into which the TE
(when connected to the network) is placed such that it
draws minimum current and does not activate the
exchange.
The signals at the output of the guard time system are sent
to the SSB-INTERRUPT treatment.
DGT0
DGT1
DGT Value
15 ms
An interrupt occurs at each edge of the OUT SCWID
detector.
0
1
0
1
0
0
1
1
17 ms
When the wetting pulse is enabled (CDE8. mode
UK = 1), an interrupt is sent to the microprocessor 15 ms
after the falling edge of the WP detector.
18 ms
19 ms
Idle state tone alert signal duration: 100 ±10 ms
frequencies: 2130 Hz + 2750 Hz
IN SCWID
detector
Choice of 4
UGT values
Choice of 4
DGT values
Up guard
time
Down guard
time
Interrupt
OUT SCWID
detector
to the µP
OUT WP
detector
15 ms
Interrupt
Interrupt
to the µP
to the µP
WETTING PULSE
(Under µP control)
20 ±5 ms
1 ms
15 ±
Not less
than 5 ms
Not less
than 25 mA
Current that
TE shall draw
14607
Figure 7. Alert detection timing diagram with wetting pulse
Rev. A2, 25-Aug-98
9 (34)
Target Specification
U3900BM
2.2.8
SCWID: Overview
CLASS
signal
Command bits CDE < 0...8 >
from serial bus
To interrupt
system
2130 Hz
Alert signal
low-frequency
logic part
Analog
filter
W pulse
Wetting
pulse
EGT UGT DGT FC
Alert
Time guard
2750 Hz
Alert signal
high-frequency
logic part
Analog
filter
14608
To CLID FSK filter
Figure 8. Alert detection
General information:
All the control bits provided for the SCWID function can be modified at any time with the microprocessor.
2.2.9
CAS Detect Process
Typical application:
The incoming signal from the CO is not polluted with speech or music. (The feature early guard time is not used)
CAS signal duration: 80 ±
5 ms
frequencies: 2130 Hz + 2750 Hz
IN SCWID
detector
Choice of 4
UGT values
Choice of 4
DGT values
Up guard
time
Down guard
time
OUT SCWID
detector
Interrupt
Interrupt
to the µP
to the µP
14609
Figure 9. Timing diagram of standard alert detection
If any drop in the CAS signal occurs before the end of the If any spike in the blank signal occurs before the end of
UGT specified value, then the time counter restarts and the DGT specified value, then the time counter restarts
the OUT SCWID detector remains low.
and the OUT SCWID detector remains high.
10 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
CAS Detect Process (continued)
Improved process:
To prevent false detection from speech and music by the far and the near end (talk-off), and to detect the incoming CAS
signal from the CO, polluted with speech or music by the near end (talk-down), a new feature is used: the early and
up guard time.
CAS signal duration: 80 ±
5 ms
frequencies: 2130 Hz + 2750 Hz mixed with speech and music frequencies
Values permitted for drops after
a successful early guard time
IN SCWID
detector
3 Drops had no effect (FDD = 4 ms, FDC = 4)
Drops
In signal
Restart
Early
guard time
Up guard time
Interrupt
OUT SCWID
detector
to the µP
Choice of 3
EGT values
Choice of 4
UGT values
14610
Figure 10. Timing diagram for early and up guard time
Note: In the case above, the EGT counter restarts 3 times. After a sucessful 10.3-ms EGT, 3 drops occured but without
any effect because the duration and the number is less than the maximum permitted.
CAS signal duration: 80 ±
5 ms
frequencies: 2130 Hz + 2750 Hz mixed with speech and music frequencies
Filter values permitted for spikes
after a successful early guard time
Spikes
in signal
mixed with speech and music frequencies
IN SCWID
detector
5 Spikes had no effect (FDD = 4 ms)
Restart
Early guard time
Down guard time
OUT SCWID
detector
Interrupt
to the µP
Choice of 3
EGT values
Choice of 4
DGT values
14611
Figure 11. Timing diagram of early and down guard time
Note: In the case above, the EGT counter restarts 3 times. After a sucessful 13.7-ms EGT, 5 spikes occured but without
any effect because the duration is less than the maximum permitted.
Rev. A2, 25-Aug-98
11 (34)
Target Specification
U3900BM
For line voltages below 2 V, the switches remain in
quiescent state as shown in the diagram.
3 DC Line Interface and
Supply-Voltage Generation
2. When the chip is in power-down mode (Bit
LOMAKE), e.g., during pulse dialing, all internal
blocks are disabled via the serial bus, except the
oscillator. In this condition, the voltage regulators and
their internal bandgap are the only active blocks.
The DC line interface consists of an electronic inductance
and a dual-port output stage which charges the capacitors
at VMPS and VB. The value of the equivalent inductance
is given by:
3. During ringing, the supply for the system is fed into
VB via the Ringing Power Converter (RPC).
Normally, the speaker amplifier in single-ended mode
is used for ringing. The frequency for the melody is
generated by the DTMF/Melody generator.
L = 2
R
C
(R
R ) / (R + R )
30 DC 30
SENSE
IND
DC
The U3900BM contains two identical series regulators
which provide a supply voltage VMP of 3.3 V suitable for
a microprocessor. In speech mode, both regulators are
active because VMPS and VB are charged
simultaneously by the DC-line interface. The output
current is 6 mA. The capacitor at VMPS is used to provide
the microcomputer with sufficient power during long line
interruptions. Thus, long flash pulses can be bridged or an
LCD display can be turned on for more than 2 seconds
after going on-hook. When the system is in ringing mode,
VB is charged by the on–chip ringing power converter. In
this mode, only one regulator is used to supply VMP with
maximum 3 mA.
4. In an answering machine, the chip is powered by an
external supply via Pin VB. The answering machine
connections could be directly put to U3900BM. The
answering machine is connected to the Pin AMREC.
For the output AMREC, an AGC function is select-
able via the serial bus. The output of the answering
machine will be connected to the Pin AMPB, which is
directly connected to the switching matrix, and thus
enables the signal to be switched to every desired
output.
3.1 Supply Structure of the Chip
V
R
SENSE
L
As main benefit of the U3900BM is the easy implementa-
tion of various applications due to the flexible system
structure of the chip.
10Ω
V
MPS
5.5 V
C
470µF
1 µF
Possible applications:
Group listening phone
Hands-free phone
–
+
–
+
IND
3.3 V
V
MP
R
+
–
R
47µF
300 kΩ
V
5.5 V
B
V
Phones which feature ringing with the built-in speaker
amplifier
220µF
14573
Answering machine with external supply
Figure 12. Supply generator
The special supply topology for the various functional
blocks is illustrated in figure 11.
4 Ringing Power Converter
(RPC)
There are four major supply states:
The RPC transforms the input power at VRING (high
voltage/ low current) into an equivalent output power at
VB (low voltage/ high current) which is capable of
driving the low-ohmic loudspeaker. The input impedance
at VRING is adjustable from 3 k to 12 k by RIMPA
1.
2.
3.
4.
Speech condition
Power down (pulse dialing)
Ringing
External supply
1. In speech condition, the system is supplied by the line (ZRING = RIMPA / 100) and the efficiency of the step-
current. If the LIDET-block detects a line voltage
above approximately 2 V, the internal signal VLON is
activated. This is detected via serial bus, all necessary
the blocks have to be switched on via the serial bus.
down converter is approximately 65%.
12 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
4.1 Ringing Frequency Detector
(RFD)
6 Serial Bus Interface
The circuit is controlled by an external microcontroller
through the serial bus. The serial bus is a bi-directional
system consisting of a one-directional clock line (BCL)
which is always driven by the microcontroller, and a
bi-directional data-signal line. It is driven by the
microcontroller as well as from the U3900BM (see
figure 12). The serial bus requires external pull-up
resistors as only open-collector transistors (Pin BDA) are
integrated.
The U3900BM provides an output signal for the
microcontroller. This output signal is always double the
value of the input signal (ringing frequency). It is
generated by a current comparator with hysteresis. The
levels for the on-threshold are programmable in 16 steps
and the off-level is fixed. Every change of the comparator
output generates a high level at the interrupt output INT.
The information can then be read out by means of a serial
bus with either a normal or a fast read mode. The block
RFD is always enabled.
WRITE:
The data is a 12-bit word:
A0 – A3: address of the destination register (0 to 15)
D0 – D7: content of the register
RINGTH[0:3]
min. 0
VRING
7 V
22 V
1 V
max. 15
step
The data line must be stable when the clock is high. Data
must be shifted serially.
5 Clock Output Divider
Adjustment
The Pin OSCOUT is a clock output which is derived from
the crystal oscillator of the ceramic resonator. It can be
used to drive a microcontroller or another remote
component and thereby reduces the number of crystals
required. The oscillator frequency can be divided by 1, 8,
16, 32. During power-on reset, the divider will be reset to
1 until it is changed by setting the serial bus.
After 12 clock periods, the write indication is sent. Then,
the transfer to the destination register is (internally)
generated by a strobe signal transition of the data line
when the clock is high (see figure 13).
READ:
There is a normal and a fast-read cycle.
In the normal read cycle, the microcontroller sends a 4-bit
address followed by the read indicator, then an 8-bit word
is read out. The U3900BM drives the data line (see
figure 14).
CLK[0:1]
Divider
Frequency
3.58 MHz
447 kHz
224 kHz
112 kHz
0
1
2
3
1
8
16
32
The fast read cycle is indicated by a strobe signal. With
the following two clocks the U3900BM reads out the sta-
tus bits RFDO and LIDET which indicate that a ringing
signal or a line signal is present (see figure 15).
6.1 Bus Timing
BDA
t
wSTA
t
r
t
f
t
hSTA
BCL
t
t
t
H
t
sSTA
t
t
L
sSTOP
hDAT
hSTA
t
hDAT
S
f
S
f
S
r
14793
S = Strobe falling, S = Strobe rising
f
R
Figure 13. Bus timing
Rev. A2, 25-Aug-98
13 (34)
Target Specification
U3900BM
DTMFF[2:3]
in DTMF
Mode
Frequency
Error / %
7 DTMF Dialing
The DTMF generator sends a multi-frequency signal
through the matrix to the line. The signal is the result of
the sum of two frequencies and is internally filtered. The
frequencies are chosen from a low and a high frequency
group.
0
1
2
3
00
01
10
11
1209
1336
1477
1633
–0.110
0.123
–0.020
–0.182
The circuit conforms to the CEPT recommendation
concerning DTMF option (rec. T/CF 46–03).
DTMFF4 in DTMF mode
Preemphasis Selection
2.5 dB
3.5 dB
Two different levels for the low level group and two
different preemphasis (2.5 dB and 3.5 dB) can be chosen
by means of the serial bus.
0
1
7.1 Melody – Confidence Tone
Generation
DTMFF
[0:4]
f
Hz
Tone- Error/%
Name
DTMF
Key
1
0
1
2
3
4
5
6
7
8
9
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
440.0
466.2
493.9
523.2
554.4
587.3
622.3
659.3
698.5
740.0
784.0
830.0
880.0
932.3
987.8
1046.5
a
b
h
–0.008
–0.016
–0.003
0.014
697 1209
770 1209
852 1209
941 1209
697 1336
770 1336
852 1336
941 1336
697 1477
770 1477
852 1477
941 1477
697 1633
770 1633
852 1633
941 1633
697 1209
770 1209
852 1209
941 1209
697 1336
770 1336
852 1336
941 1336
697 1477
770 1477
852 1477
941 1477
697 1633
770 1633
852 1633
941 1633
1
4
Melody/confidence tone frequencies are given in the
table below.
1
1
7
2
The frequencies are provided at the DTMF input of the
switch matrix. A sinus wave, a square wave or a pulsed
wave can be selected by the serial bus. Square signal
means output is half of frequency cycle high and half low,
so duty cycle of 50% square wave or 50% for pulsed
signal.
c
*
2
des
0.018
2
2
d
–0.023
–0.129
0.106
5
2
es
8
2
e
0
2
f
–0.216
–0.222
0.126
3
2
ges
6
DTMFM[0:2]
2
10 01010
g
9
0
1
000
001
DTMF generator OFF
Confidence tone melody
on (sinus)
2
11
12
13
14
15
01011
01100
01101
01110
01111
as
–0.169
0.288
#
2
a
b
h
A
B
C
D
1
2
2
–0.014
–0.004
–0.335
–0.355
–0.023
–0.129
0.106
2
3
010
011
Ringer melody (pulse)
Ringer melody
(square signal)
3
c
3
16 10000
17 10001
18 10010
1108.7 des
4
5
6
7
100
101
110
111
DTMF(high level)
DTMF(low level)
3
1174.7
1244.5
1318.5
1396.9
d
4
3
es
7
3
19
10011
e
*
3
20 10100
21 10101
f
–0.214
–0.222
0.126
2
3
1480.0 ges
5
3
22
23
24
25
26
27
28
29
30
31
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
1568.0
1661.2
1760.0
1864.6
1975.5
2093.0
g
8
3
as
–0.241
–0.302
–0.014
0.665
0
DTMFF[0:1]
in DTMF
Mode
Frequency
Error / %
3
a
b
h
3
3
6
3
9
0
1
2
3
00
01
10
11
697
770
852
941
–0.007
–0.156
0.032
4
c
0.367
#
4
2217.5 des
0.387
A
B
C
D
4
2349.3
2663.3
2983.0
d
0.771
0.316
–––
–––
14 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Write cycle
CLOCK
DATA
R/W=0
A0
D7 D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
Data fromµP
Strobe
fromµP
14574
Figure 14. Write cycle
Normal read cycle
CLOCK
DATA
A3 A2
A1
A0
R/W=1
D7
D6
D5
D4
D3
D2
D1
D0
Data fromµP
Strobe
Data from U3900BM
14794
fromµP
Figure 15. Normal read cycle
Fast read cycle
CLOCK
DATA
D7=IZC D6=IVE
Data from U3900BM
Strobe
from µP
14795
Figure 16. Fast read cycle
Rev. A2, 25-Aug-98
15 (34)
Target Specification
U3900BM
Table 1. Names and functions of the serial bus registers
Register
R0
Group
Enables
No
Name
ENRING
ERX
Description
Status
1
R0B0
R0B1
R0B2
R0B3
R0B4
R0B5
R0B6
R0B7
R1B0
R1B1
R1B2
R1B3
R1B4
R1B5
R1B6
R1B7
R2B0
R2B1
R2B2
R2B3
R2B4
R2B5
R2B6
R2B7
R3B0
R3B1
R3B2
R3B3
R3B4
R3B5
R3B6
R3B7
R4B0
R4B1
R4B2
R4B3
R4B4
R4B5
R4B6
R4B7
R5B0
R5B1
R5B2
R5B3
R5B4
R5B5
R5B6
R5B7
Enable ringer
Enable receive part
0
ETX
Enable transmit part
0
ENVM
ENMIC
ENSTBAL
MUTE
ENRLT
ENSACL
ENSA
ENSAO
ENAM
ENCT
ANAMAGC
ENCLID
ENSCWID
I1O1
Enable VM generator
1
1
Enable microphone
0
0
0
Enable sidetone balancing
Muting earpiece amplifier
Enable POR low threshold
Enable anti-clipping for speaker amplifier
Enable speaker amplifier and AFS
Enable output stage speaker amplifier
Enable answering machine connections
Enable cordless telephone connections
Enable answering machine AGC
Enable CLID
R1
R2
R3
R4
R5
Enables
Matrix
Matrix
Matrix
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Enable SCWID
Switch on MIC / LTX
I1O2
Switch on MIC / RXLS
I1O3
Switch on MIC / EPO
I1O4
Switch on MIC / CEAR
I1O5
Switch on MIC / AMREC
Switch on DTMF / LTX
Switch on DTMF / RXLS
Switch on DTMF / EPO
Switch on DTMF / CEAR
Switch on DTMF / AMREC
Switch on LRX / LTX
I2O1
I2O2
I2O3
I2O4
I2O5
I3O1
I3O2
Switch on LRX / RXLS
I3O3
Switch on LRX / EPO
I3O4
Switch on LRX / CEAR
Switch on LRX / AMREC
Switch on CMIC / LTX
I3O5
I4O1
I4O2
Switch on CMIC / RXLS
Switch on CMIC / EPO
I4O3
I4O4
Switch on CMIC / CEAR
Switch on CMIC / AMREC
Switch on AMPB / LTX
Switch on AMPB / RXLS
Switch on AMPB / EPO
Switch on AMPB / CEAR
Switch on AMPB / AMREC
Gain transmit AGA LSB
Gain transmit AGA
I4O5
I5O1
I5O2
I5O3
I5O4
Matrix
I5O5
AGATX
MICLIM
AGATX0
AGATX1
AGATX2
MICHF
DBM5
MIC0
Gain transmit AGA MSB
Select RF-microphone input
Max. transmit level for anti-clipping
Gain microphone amplifier LSB
Gain microphone amplifier MSB
MIC1
16 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Register
R6
Group
Sidetone
No
Name
FOFFC
Description
Speed up offset canceller
Status
0
R6B0
R6B1
R6B2
R6B3
R6B4
R6B5
R6B6
R6B7
R7B0
R7B1
R7B2
R7B3
R7B4
R7B5
R7B6
R7B7
R8B0
R8B1
R8B2
R8B3
R8B4
R8B5
R8B6
R8B7
R9B0
R9B1
R9B2
R9B3
R9B4
R9B5
R9B6
R9B7
DTAMAGC
SL0
Decay time answering machiune AGC
Slope adjustment for sidetone LSB
Slope adjustment for sidetone MSB
Low-frequency adjustment for sidetone LSB
Low-frequency adjustment for sidetone
Low-frequency adjustment for sidetone
Low-frequency adjustment for sidetone MSB
Pole adjustment for sidetone LSB
Pole adjustment for sidetone
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SL1
LF0
LF1
LF2
LF3
R7
Sidetone
AGARX
P0
P1
P2
Pole adjustment for sidetone
P3
Pole adjustment for sidetone
P4
Pole adjustment for sidetone MSB
Gain receive AGC LSB
AGARX0
AGARX1
AGARX2
EA0
Gain receive AGC
Gain receive AGC MSB
R8
EARA
PS
Gain earpiece amplifier LSB
Gain earpiece amplifier
EA1
EA2
Gain earpiece amplifier
EA3
Gain earpiece amplifier
EA4
Gain earpiece amplifier MSB
IMPSEL
LOMAKE
SD
Line-impedance selection (1 = 1 k
Short circuit during pulse dialing
Shut down
)
R9
AFS
AFS0
AFS1
AFS2
AFS3
AFS4
AFS5
AFSM
ALT
AFS gain adjustment LSB
AFS gain adjustment
AFS gain adjustment
AFS gain adjustment
AFS gain adjustment
AFS gain adjustment MSB
AFS mode
Antilarsen threshold
R10
SA
R10B0
R10B1
R10B2
R10B3
R10B4
R10B5
R10B6
R10B7
R11B0
R11B1
R11B2
R11B3
R11B4
R11B5
R11B6
R11B7
SA0
Gain speaker amplifier LSB
Gain speaker amplifier
Gain speaker amplifier
Gain speaker amplifier
Gain speaker amplifier MSB
SA1
SA2
SA3
SA4
SE
Speaker amplifier single-ended mode
Speaker amplifier charge-current adjustment LSB
Speaker amplifier charge-current adjustment MSB
Input selection ADC
LSCUR0
LSCUR1
ADC0
ADC1
ADC2
ADC3
NWT
SOC
R11
ADC
Input selection ADC
Input selection ADC
Input selection ADC
Network tuning
Start of ADC conversion
ADCR
MSKIT
Selection of ADC range
Mask for interrupt bits
Rev. A2, 25-Aug-98
17 (34)
Target Specification
U3900BM
Register
R12
Group
DTMF
No
R12B0
Name
DTMFF0
DTMFF1
DTMFF2
DTMFF3
DTMFF4
DTMFM0
DTMFM1
DTMFM2
CLK0
Description
DTMF frequency selection
Status
0
R12B1
R12B2
R12B3
R12B4
R12B5
R12B6
R12B7
R13B0
R13B1
R13B2
R13B3
R13B4
R13B5
R13B6
R13B7
R14B0
R14B1
R14B2
R14B3
R14B4
R14B5
R14B6
R14B7
R15B0
R15B1
R15B2
R15B3
R15B4
R15B5
R15B6
R15B7
DTMF frequency selection
DTMF frequency selection
DTMF frequency selection
DTMF frequency selection
Generator mode selection
Generator mode selection
Generator mode selection
Selection clock frequency for
Selection clock frequency for
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R13
R14
R15
CLK
RTH
TM
C
C
CLK1
RTH0
Ringer threshold adjustment LSB
Ringer threshold adjustment
Ringer threshold adjustment
Ringer threshold adjustment MSB
Test mode enable (low active)
Test mode enable (high active)
Test mode enable (high active)
Test mode enable (low active)
RTH1
RTH2
RTH3
TME0
TME1
TM
TME2
CLID
TME3
ENRXCL
GSCWID
WP
Selection of internal CLID input signals
Gain adjustment of SCWID behind sidetone
Wetting pulse
CLID
UGT0
SCWID up guard time
UGT1/SCD
SCWID up guard time/ CLIB special carier detect
DGT0/CDLF0 SCWID down guard time/ CLID LF carrier detect
DGT1/CDLF1 SCWID down guard time/ CLID LF carrier detect
EGT0/CDHF0 SCWID early guard time/ CLID HF carrier detect
EGT1/CDHF1 SCWID early guard time/ CLID HF carrier detect
FDD
FDC
Filter drop duration
Filter drops count
8 Power-on Reset
9 Watchdog Function
To avoid undefined states of the system when it is
powered on, an internal reset clears the internal registers.
To avoid the system operating the microcontroller in a
wrong condition, the cicuit provides a watchdog function.
The system (U3900BM + microcontroller) is woken up The watchdog has to be retriggered every second by
by any of the following conditions:
VMP > 2.75 V and VB > 2.45 V and
line voltage (VL)
triggering the serial bus (sending information to the IC or
other remoted components at the serial bus). If there has
been no bus transmission for more than one second the
watchdog iniates a reset.
or
or
ringer (VRING)
external supply (ES)
The power-down of the circuit is caused by a shut-down
sent by the serial bus (SD = 1), low-voltage reset or by the
watchdog function (see figures 16, 17 and 18).
18 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Line
LID
IVDD
OSCOUT
ton
VMP
Reset
trt
14585
trt – t = 4.5 ms
ton =osntart–up oscillator
Figure 17. Power-on reset (line)
VRING
VB
IVDD
VMP
OSCOUT
ton
Reset
trt
14586
Figure 18. Power-on reset (ringing)
Line
LID
VMP
IVDD
LVR
IVDD
Reset
OSCOUT
14612
Figure 19. Power-on reset if low voltage reset enabled
Rev. A2, 25-Aug-98
19 (34)
Target Specification
U3900BM
10 Acoustic Feedback Suppression
Acoustical feedback from the loudspeaker to the decision is made by the differential pair as to which
microphone may cause instability of the system. The direction should be transmitted.
U3900BM has a very efficient feedback-suppression
The attenuation of the controlled amplifiers TXA and SAI
circuit which uses a modified voice switch topology.
is determined by the emitter current IAFS which is bus
Figure 20 shows the basic system configuration.
programmable.
Two attenuators (TXA and SAI) reduce the critical loop
gain via the serial bus either in the transmit or in the
receive path. The sliding control in block AFS control
(figure 19) determines whether the TX or the RX signal
has to be attenuated. The overall loop gain remains
constant under all operating conditions.
IDTXA
IDSAI
Selection of the active channel is made by a comparison
of the logarithmically compressed TX- and RX- envelope
curve. Figure 19 shows the AFS control.
TLDT
TLDR
+
–
The system configuration for group listening, which is
implemented in the U3900BM, is illustrated in figure 21.
TXA and SAI represent the two attenuators, whereas the
logarithmic envelope detectors are shown in a simplified
way (operational amplifiers with two diodes).
IAFS
BUS
Receive and transmit signals are first processed by
logarithmic rectifiers in order to produce the envelopes of
the speech at TLDT and RLDT. After amplification a
14613
Figure 20. AFS control
TXA
MICRO
LOG
Line
AFS
control
LOG
SA
SAI
14591
Figure 21. Basic system configurations
20 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
TLDT
TXA
SAI
TX
TX
INLDT
INLDR
+
–
I
I
BUS
BUS
AFS
GSA
14614
TLDR
Figure 22. System configuration for group listening
11 Analog-to-Digital Converter (ADC)
The circuit is a 7-bit successive approximation analog-
to-digital converter in switched capacitor technique. An
SOC
50 µs
internal bandgap circuit generates a 1.25-V reference
voltage which is the equivalent of
1
MSB.
1 LSB = 19.5 mV. The possible input voltage at ADIN is
0 to 2.48 V.
EOC
14594
Figure 23. Timing of ADC
The ADC needs an SOC (Start Of Conversion) signal. In
the ‘High’ phase of the SOC signal, the ADC is reset.
50 s after the beginning of the ‘Low’ phase of the SOC
signal the ADC generates an EOC (End Of Conversion)
signal which indicates that the conversion is finished. The
rising edge of EOC generates an interrupt at the INT
output. The result can be read out by the serial bus.
SOC
ADC
EOC
IL 20mV/(1mA S)
ADIN
0.4 VB
MSB
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
0.4 VMPS
0.75 VMP
Voltages higher than 2.48 V have to be divided. The
signal which is connected to the ADC is determined by
5 bits ADC0, ADC1, ADC2, ADC3 and NWT.
TLDR/TLDT measuring is possible relative to a preced-
ing reference measurement. The current range of IL can
be doubled by ADCR. If ADCR is ‘High’, S has the value
0.5, otherwise S = 1.
8
8
(TLDR–REF)
(TLDT–REF)
0.4 SAO1
0.4 OFF1
0.4 OFF2
0.4 OFF3
The source impedance at ADIN must be lower than
250 k .
14595
Accuracy: 1 LSB ± 3%
Figure 24. ADC input selection
Rev. A2, 25-Aug-98
21 (34)
Target Specification
U3900BM
Table 2. Input selection AD converter
ADC[0:3]
Value
0
1
2
3
4
5
6
7
8
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
OFF
IL
ADIN external
VB
VMPS
VMP
TLDR
TLDT
Free
SAO1
Offcan1
Offcan2
Offcan3
Free
I1 = S 127 mA D / 127
V2 = 2.5 V D / 127 (max. 2.5 V)
V3 = (2.5 V / 0.4) D / 127
V4 = (2.5 V / 0.4) D / 127
V5 = (2.5 V / 0.75) D / 127
V6 = 1/8 (Vp – Ref) D / 127
V7 = 1/8 (Vp – Ref) D / 127
9
V4 = (2.5 V / 0.4) D / 127
TEMIC internal use
TEMIC internal use
10
11
12
13
14
15
TEMIC internal use
Free
Free
D = measured digital word (0 < = D < = 127)
S = programmable gain 0.5 or 1
Vp = peak value of the measured signal
12 Switch Matrix
AMPB CMIC LRX DTMF MIC
The switch matrix has 5 inputs and 5 outputs. Every pair
of input and output can be connected. The inputs and
outputs used must be enabled. If 2 or more inputs are
switched to an output, the sum of the inputs is available
at the output. The inputs MIC and LRX have offset
cancellers with a 3-dB corner frequency of 270 Hz.
AMPB and CMIC have a 60-k input impedance. The
TXO output has a digitally-programmable gain stage with
a gain of 2, 3 to 9 dB depending on AGATX0 (LSB),
AGATX1, AGATX2 (MSB) and a first-order low-pass
filter with 0.5 dB damping at 3300 Hz and 3 dB damping
at 9450 Hz. The outputs RXLS, EPO and CEAR have a
gain of 0 dB. If a switch is open, the path has a damping
of more than 60 dB.
Offset
canceller
Offset
canceller
I5
I4
I3
I2
I1
Lowpass
O1
O5
O4
O3
O2
AGATX0
AGATX1
AGATX2
2 ... 9 dB
LTX
AGC
AGCI AMREC EPO RXLS
TXO
–10 dB
14079
STO
Figure 25. Diagram of switch matrix
22 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Table 3. Table of bits and corresponding switches
Register
R2
Group
Matrix
No.
Name
Description
R2B0
R2B1
R2B2
R2B3
R2B4
R2B5
R2B6
R2B7
R3B0
R3B1
R3B2
R3B3
R3B4
R3B5
R3B6
R3B7
R4B0
R4B1
R4B2
R4B3
R4B4
R4B5
R4B6
R4B7
R5B0
I1O1
I1O2
I1O3
I1O4
I1O5
I2O1
I2O2
I2O3
I2O4
I2O5
I3O1
I3O2
I3O3
I3O4
I3O5
I4O1
I4O2
I4O3
I4O4
I4O5
I5O1
I5O2
I5O3
I5O4
I5O5
Switch on MIC / LTX
Switch on MIC / RXLS
Switch on MIC / EPO
Switch on MIC / CEAR
Switch on MIC / AMREC
Switch on DTMF / LTX
Switch on DTMF / RXLS
Switch on DTMF / EPO
Switch on DTMF / CEAR
Switch on DTMF / AMREC
Switch on LRX / LTX
R3
R4
R5
Matrix
Matrix
Matrix
Switch on LRX / RXLS
Switch on LRX / EPO
Switch on LRX / CEAR
Switch on LRX / AMREC
Switch on CMIC / LTX
Switch on CMIC / RXLS
Switch on CMIC / EPO
Switch on CMIC / CEAR
Switch on CMIC / AMREC
Switch on AMPB / LTX
Switch on AMPB / RXLS
Switch on AMPB / EPO
Switch on AMPB / CEAR
Switch on AMPB / AMREC
Rev. A2, 25-Aug-98
23 (34)
Target Specification
U3900BM
13 Sidetone System
The Sidetone Balancing (STB) has the task to reduce the The 3 programmable parameters are
crosstalk from LTX (microphone) to LRX (earpiece) in
the frequency range of 0.3 to 3.4 kHz. The LTX signal is
converted into a current in the MOD block. This current
is transformed into a voltage signal (LINE) by the line
impedance ZL. The LINE signal is fed into the summing
amplifier DIFF1 via capacitor CK and attenuator AMP1.
1. LF (gain at low frequency).
LF has 15 programming steps. LF(0) gives –2 dB
gain, LF(15) gives 5.5 dB gain.
LF
0
1
2
3
4
5
6
7
Step gain –2 –1.3 –0.6 0.1 0.6 1.0 1.3 1.6
On the other side the LTX buffered by STOAMP drives
an external low-pass filter (RST, CST). The external low-
pass filter and the internal STB have the transfer function
drawn in the STB box. The amplified STB-output signal
drives the negative input of the summing block. If both
signals at the DIFF1 block are equal in level and phase,
we have a good suppression of the LTX signal. In this
condition the frequency and phase response of the STB
block will represent the frequency curve on line.
LF
8
9
10
11
12
13
14
15
Step gain 1.9 2.2 2.5 3.0 3.6 4.2 4.8 5.5
STO_DIFF(LF)= (–10 dB – 2 dB + 0.5 dB LF + 9 dB) LTX
2. P (the pole position of the lowpass).
The P adjustment has 31 Steps. P(0) means the
lowpass determined by the external application
(RST, CST). The internally processed low-pass
frequency is fixed by this equation.
1
f(P)
1.122P
In real live the line impedance ZL varies strongly for
different users. To reach a good suppression with one
application for all different line impendances, the STB
function is programmable.
2
CST RST
3. SL
(sidetone slope; the pole frequency of the highpass)
The SL have 3 steps. SL(0) is a lower frequency of the
highpass. SL(3) is a higher frequency of the highpass.
With SL we can influence the suppression at high
frequencies.
LTX
LINE
8dB
CK
ZL
MOD
LRX
RECIN
DIFF1
+
–10dB
0–7dB
–
STO
AGARX
AMP1
STO_DIFF
–10dB
STOAMP
9dB AMP2
STO
8.2 kΩ
Sidetone balancing
P
STRC
STC
LF
g
CTO
33 nF
SL
f
14579
LF
P
SL
Figure 26. Programmable sidetone supression circuit
24 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
< = 32 dB
0 / 6 dB
LSCUR
[
]
1:2
SE
V
V
B
M
CFN
Offset
canceler
CHARLSC
ENSA
200 kΩ
100 kΩ
SAI
V
–
B
100 kΩ
V
B
SAO1
–
+
+
ENSA
47 µF
V
V
ENSA
SACL
M
M
V
B
100 kΩ
30 kΩ
50 Ω
VB_REG
100 kΩ
100 kΩ
V
B
100 kΩ
V
–
B
ENSA
SAO2
–
+
+
[
]
EN 1:6
PROG_SAI
V
V
EN
M
M
ENSA
IDSAI
Ron = 2 Ω
ENSACL
TSACL
ENSA ENSAO SE
14593
Figure 27. Speaker amplifier
–10dB
Offset
cancel
–3dB ... –10dB and 7dB (NWT)
7dB→0dB and
ST
32dB
–14.5dB
20dB (NWT)
SAO1
Sidetone
balancing
Offset
cancel
Loud–
speaker
6dB
LRX
RXLS
EPO
VL
Line
1.5dB steps
1dB steps
SAO2
26dB→-3dB and
–10dB (DTMF)
RECO1
Earpiece
DTMF
Filter
DTMF
< –24dBm/
–22dBm >
DTMF
< –40dBm/
–38dBm >
DTMF
generator
MIC1
1dB steps
RECO2
VL
Switching
matrix
Handset
micro–
phone
30dB→12dB
9dB→2dB
0dB
7dB
Offset
cancel
MIC2
MIC3
8dB
MIC
LTX
Line
TXA
Handsfree
micro–
1dB steps
MOD
6dB steps
1dB steps
0dB
phone
CEAR
0dB
0dB
Cordless
AMPB AMREC
CMIC
AMREC
Answering
machine
0dB
0dB
Answering
machine
AGCO
AGCI
AGC
AMPB
14620
Figure 28. Audio frequency signal management U3900BM
Rev. A2, 25-Aug-98
25 (34)
Target Specification
U3900BM
14 Technical Data
14.1 Absolute Maximum Ratings
Parameters
Line current
DC line voltage
Symbol
Value
140
12
Unit
mA
V
I
L
V
L
Maximum input current
Junction temperature
Ambient temperature
Storage temperature
I
15
125
–25 to +75
–55 to +150
0.9
mA
°C
°C
°C
W
RING
T
j
T
amb
T
stg
Total power dissipation,
T
amb
= 60°C
P
tot
14.2 Thermal Resistance
Parameters
SSO44
Symbol
R
thJA
Value
70
Unit
K/W
Junction ambient
14.3 Electrical Characteristics
f = 1 kHz, 0 dBm = 775 mV , IVMIC = 0.3 mA, IMP = 3 mA, R = 1.3 MΩ, T
= 25°C, Z = 68 nF + 100 Ω,
ear
rms
DC
amb
Z
= 68 nF, f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
M
Parameters
DC characteristics
DC voltage drop-over
circuit
Test Conditions / Pins
I = 2 mA
Symbol
Min.
Typ.
Max.
Unit
V
Fig.
2.4
5.0
7.5
9.4
L
I = 14 mA
V
L
4.6
8.8
5.4
L
I = 60 mA
L
I = 100 mA
L
10.0
Transmission amplifier, I = 14 mA, V
= 2 mV
, MICG[0:1] = 2, AGATX[0:2] = 7
RMS
L
MIC
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, (G = 48 dB)
T
Transmit amplification MICG[0:1] = 2
AGATX[0:2] = 7
G
46
47
48
0
dB
dB
dB
T
Frequency response
(see note 1)
I ≥ 14 mA,
f = 3.4 kHz
G
–1
L
T
T
T
Gain change with
current
I = 14 to 100 mA
L
G
G
±0.5
±0.5
Gain deviation
T
amb
= –10 to +60°C
dB
dB
CMRR of microphone
amplifier
Input resistance of
MIC amplifier
CMRR
60
75
80
50
R
R
kΩ
kΩ
dB
i
Input resistance of
MIC3 amplifier
Gain difference
between MIC1, MIC2
to MIC3
MICHF = 1
MICHF = 1
150
300
i
G
±0.4
T
Distortion at line
I ≥ 14 mA
L
d
t
2
%
V = 700 mV
L
rms
Note 1)
26 (34)
Frequency response is due to internal filters
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Electrical Characteristics (continued)
Parameters
Maximum output
voltage
Test Conditions / Pins
I ≥ 19 mA, d < 5%
Symbol
Min.
1.3
Typ.
2.5
Max.
3.7
Unit
dBm
Fig.
V
Lmax
L
V
MIC
= 10 mV
CTXA = 1 µF
DBM5 = 0
DBM5 = 1, V
= 14 mV
V
3.8
5.0
–5.2
6.2
dBm
dBm
MIC
Lmax
V
MIC
= 20 mV
V
MICOmax
MICG[0:1] = 3
Noise at line psopho-
metrically weighted
I ≥ 14 mA
MICG[0:1] = 2
AGATX[0:2] = 7
no
L
– 80
– 72
dBmp
ms
Anti-clipping:
attack time
CTXA = 1 F
each 3 dB overdrive
t
a
0.5
16
release time
Gain at low operating
current
t
r
ms
dB
I = 8 mA
G
T
46.5
49.5
5
L
I
= 1 mA
MP
R
DC
= 680 kΩ
V
= 0.5 mV
= 300 A
MIC
I
VMIC
Distortion at low oper- I = 8 mA
d
t
%
L
ating current
I
= 1 mA
MP
R
DC
= 680 kΩ
V
MIC
= 5 mV
I
= 300 A
VMIC
Receiving amplifier
I = 14 mA, V
L
= 300 mV,
GEN
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31,
AGARX[0:2] = 0
Adjustment range of
receiving gain
Single ended,
I ≥ 14 mA,
L
G
R
–25
11
dB
Mute = 1,
EA[0:4] = 2 – 31
AGARX[0:2] = 0 – 7
Receiving amplifica-
tion
Differential
AGARX[0:2] = 0
EA[0:4] = 21
EA[0:4] = 31
G
R
–1
10
0
11
1
12
dB
dB
Frequency response
Gain change with cur- I = 14 to 100 mA
I ≥ 14 mA, f = 3.4 kHz
G
G
–1
0
±0.5
dB
dB
L
RF
L
R
rent
Gain deviation
T
amb
= –10 to +60°C
G
R
±0.5
dB
Ear protection
differential
I ≥ 14 mA,
EP
3
V
rms
L
V
GEN
= 11 V
rms
MUTE suppression
I = 14 mA
L
G
R
60
dB
Output voltage d < 2% I = 14 mA
L
differential
Z
= 68 nF + 100 Ω
tbd.
V
rms
ear
EA[0:4] = 11
Z = 100 Ω
ear
EA[0:4] = 31
Maximum output
current d < 2%
10
mAp
Rev. A2, 25-Aug-98
27 (34)
Target Specification
U3900BM
Electrical Characteristics (continued)
Parameters
Test Conditions / Pins
I = 14 mA
Symbol
Ro
Min.
Typ.
– 80
Max.
– 77
Unit
dBmp
Fig.
Receiving noise
psophometrically
weighted
Sidetone suppression
Output resistance
L
Z
= 68 nF + 100 Ω
ear
EA[0:4] = 21
Z = 600 Ω
Each output against GND
20
–2
dB
dB
10
2
Gain at low operating
current (receive only)
I = 5 mA, I = 1 mA
G
R
0
L
MP
I
= 300 A
M
V
GEN
= 200 mV
R
DC
= 680 kΩ,
EA[0:4] = 21,
ENMIC = ETX = I101 = 0
AC impedance
IMPH = 0
IMPH = 1
Z
Z
570
950
600
1000
640
1050
imp
imp
Distortion at low
operating current
I = 8 mA, I = 1 mA
dR
5
%
L
MP
V
GEN
= 400 mV
R
DC
= 680 kΩ
EA[0:4] = 21
Adjustment step:
ear-piece amplifier
Adjustment step:
AGARX
AGARX[0:4] = 1
0.8
0.8
1
1
1.2
1.2
dB
dB
EA[0:4] = 1
Gain for DTMF signal AMPB → RECO1/2
EA[0:4] = 1
–16
dB
DTMF, I = 14 mA, ETX = I201 = 1, AGATX[0:2] = 7, DTMFM[0:2] = 4, DTMFF[0:2] = 0
L
Max. level at line
Sum level, 600
DTMFM[0:2] = 5
Sum level, 600
DTMFM[0:2] = 4
–5.1
–3.6
–2.1
dBm
dBm
DTMF level at line
(low gain)
–7.6
–6.1
–4.6
Preemphasis
600
DTMFF4 = 0
DTMFF4 = 1
2
3
2.5
3.5
3
4
dBm
dBm
Speaker amplifier, differential mode
AMPB → SAO1/2
ENSACL = ENSA = ENSAO = ENAM = I5O2 = 1, SA[0:4] = 0
Minimum line current
for operation
Gain from AMPB to
SAO
No AC signal
= 3 mV, I = 15 mA,
SA[0:4] = 31
SA[0:4] = 0
I
8
mA
Lmin
V
AMPB
G
SA
L
37
38
–8.5
1.5
39
dB
dB
Adjustment step
speaker amplifier
SA[0:4] = –1
1.3
1.7
Output power
single ended
Load resistance:
R = 50 Ω, d < 5%
L
V
AMPB
= 20 mV, SE = 1
I = 15 mA
I = 20 mA
L
P
SA
P
SA
3
7
20
mW
mW
L
Max. output power
differential
Load resistance:
R = 50 Ω, d < 5%
L
P
SA
200
mW
V
AMPB
= 20 mV, SE = 0
V = 5 V
B
28 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Electrical Characteristics (continued)
Parameters
Output noise
(input AMPB open)
psophometrically
weighted
Test Conditions / Pins
I > 15 mA
Symbol
Min.
Typ.
Max.
240
Unit
Fig.
L
n
SA
V
psoph
Gain deviation
I = 15 mA
L
T
= –10 to +60°C
G
VSAO
±1
dB
dB
amb
SA
Mute suppression
I = 15 mA, V = 0 dBm,
60
–1
L
L
V
= 4 mV, I5O2 = 0
AMPB
Gain change with
current
Gain change with
frequency
Attack time of
anti-clipping
Release time of
anti-clipping
Charge current
Pin SAO2
Discharge current
Pin SAO2
Adjustment step of
charge current
Adjustment step of
discharge current
I = 15 to 100 mA
L
G
G
±1
dB
dB
ms
ms
mA
mA
A
SA
I = 15 mA f = 3.4 kHz
L
0
SA
20 dB over drive
t
r
5
t
f
80
ENSAO = 0, SE = 1
LSCUR[0:1] = 3
ENSAO = 0, SE = 0
LSCUR[0:1] = 3
ENSAO = 0, SE = 1
LSCUR[0:1] = 1
ENSAO = 0, SE = 0
LSCUR[0:1] = 1
I
–1.45
0.95
–480
320
–1.2
1.2
–0.95
1.45
–320
480
CHA
I
DIS
–400
400
A
Microphone amplifier,
V = 5 V, V
B
= 2 mV, V
= 2 mV, ENMIC = ENCT = I1O4 = 1, MICHF = 0
MIC
MIC3
Gain MIC Amp.:
MIC1/2 → CEAR
MICG[0:1] = 0
MICG[0:1] = 1
MICG[0:1] = 2
MICG[0:1] = 3
18.4
24.4
30.4
36.4
36.4
19
25
31
37
37
19.6
25.6
31.6
37.6
37.6
dB
dB
dB
dB
dB
MIC3 → CEAR
MICHF = 1, MICG[0:1] = 3
Input suppression:
MIC3 → MIC1/2
MIC1/2 → MIC3
Settling time
MICG[0:1] = 3, MICHF = 0
MICHF = 1
FOFFC = 0
60
60
dB
dB
ms
9
12
offset-cancellers, 5
Settling time offset-
cancellers in speed-up
mode, 5
FOFFC = 1
1.8
2.4
ms
AGC for answering machine, AMPB → AMREC,
ENAM = I5O5 = 1
Nominal gain
Max. output level
Attack time
V
= 5 mV
= 50 mV, d< 5%
–1
160
0
200
2
1
240
dB
mVp
ms
AMPB
V
AMPB
20 dB overdrive
Release time
100
ms
Rev. A2, 25-Aug-98
29 (34)
Target Specification
U3900BM
Electrical Characteristics (continued)
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Fig.
Switching matrix, VL = 0, VB = 5 V, ENCT =ENAM = I4O4 = I5O4 = 1, V
= V
= 1 V
rms
AMPB
CMIC
Input impedance
AMPB, CMIC
50
60
70
kΩ
Gain CMIC → CEAR,
AMREC → CEAR
–0.4
0
0.4
dB
Max. input level
AMPB, CMIC
600
mV
Max. output level
CEAR
VB–
600 mV
V
PP
Offset
I4O4: 1 → 0
V
AMREC
±30
mV
dB
Mute switching matrix I4O4 = 0
60
Power-on reset
VL = 0, V = 3.3 V, V = 5 V, U3900BM in power-down mode
MP B
Power-on reset by V
threshold, VL or
V = 4 V, ES = 4 V,
rise VMP
VMPon
2.65
2.75
2.85
3.05
V
V
MP
B
V
RING
or ES high
Power-on reset by V
V
MP
= 3 V, ES = 3 V,
VBon
2.85
2.95
B
threshold, V or V
rise V
L
RING
B
or ES high
Low voltage interrupt
V = 0, V = 3.3 V, V = 0 V
L MP B
VMP decreasing
Decrease VMP until INT
returns to high
VLVI
2.5
2.6
2.7
V
Power-off reset
V = 0, V = 3.3 V, V = 0 V
L MP B
Low voltage reset
Decrease VMP until RESET
returns to low
VLVI – VLVR
VLVR
2.35
100
2.45
150
2.55
V
Difference voltage
between low voltage
interrupt and reset
mV
Logical part
V = 3.3 V, V = 5 V
MP B
Output impedance at
OSCOUT
0.5
1.0
kΩ
Pins BCL,
BDA (input mode)
Low level
High level
0.2
V
V
V
MP
0.8 V
MP
Input leakage current
Pins INT,
BDA (output mode)
0 < V < V
Output low
(resistance to GND)
–1
220
1
A
i
MP
310
400
Ω
AFS acoustic feedback suppression, I = 14 mA, V
= 300 mV,
GEN
L
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31,
AGARX[0:2] = 0
Adjustment range of
attenuation
Attenuation of transmit I ≥ 15 mA, I
I ≥ 15 mA
0
50
52
52
dB
dB
dB
L
= 0 A
G
T
48
48
50
50
L
INLDT
INLDT
gain
I
= 10 A
INLDR
Attenuation of speaker I ≥ 15 mA, I
= 10 A
G
SA
L
amplifier
30 (34)
I
= 0 A
INLDR
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Electrical Characteristics (continued)
Parameters
Supply voltages, V
Test Conditions / Pins
= 25 mV, T = – 10 to + 60°C
Symbol
Min.
3.1
Typ.
3.3
Max.
Unit
Fig.
MIC
amb
V
MP
V
MPS
V
MIC
V
B
I = 14 mA, R = 680 k
V
MP
3.5
5.7
4
V
V
V
V
L
DC
I
= 3 mA
MP
I = 100 mA, R = inf.,
V
MPS
L
DC
I
= 0 mA
MP
I
I
14 mA, R = 1.3 M
= 700 A
V
MIC
1.5
L
DC
M
I = +20 mA, I = 0 mA
V
B
5.5
20
6.3
B
L
VL = 100 mA
Ringing power converter, I = 1 mA, I = 0 R = 500 k
IMPA
Maximum output
power
MP
M
V
RING
= 20.6 V,
P
SA
mW
DTMFM[0:2] = 3
I2O2 = ENSA = ENSAO =
SE = 1
Threshold
V
: high to low
6.5
7
7
V
V
RING
low to high
RINGTH [0:3] = 0
6.3
7.7
low to high
RINGTH [0:3] = 15
RINGTH = 1
20
0.8
22
1
24
1.2
V
V
Adjustment steps
threshold
Input impedance
Z-diode voltage
V
= 30 V
= 25 mA
4
30.8
5
6
kΩ
V
RING
I
V
RING
RINGmax
Serial bus BCL, BDA, AS, VMP = 3.3 V, RBDA = RBCL = RINT = 12 k
Input voltage
HIGH
LOW
BDA, BCL,
V
iBUS
INT
3.0
0
V
1.5
V
V
DD
Output voltage
Acknowledge LOW
Clock frequency
BDA
BCL
I
= 3 mA
V
f
BCL
0.4
100
1
V
kHz
s
BDA
O
Rise time BDA, BCL
Fall time BDA, BCL
t
r
t
f
300
ns
Period of BCL
HIGH
LOW
HIGH
LOW
t
t
4.0
4.7
s
s
H
L
Setup time
Start condition
Data
t
4.7
250
4.7
4.7
s
ns
s
sSTA
t
sDAT
Stop condition
t
sSTOP
1)
Time space
t
s
wSTA
Hold time
Start condition
DATA
t
t
4.0
0
s
s
hSTA
hDAT
1)
This is a space of time where the bus must be free from data transmission and before a new transmission can be started
Rev. A2, 25-Aug-98
31 (34)
Target Specification
U3900BM
Electrical Characteristics (continued)
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Fig.
Alert tone detection
Low tone frequency
High tone frequency
Frequency deviation
accept
f
2130
2750
Hz
Hz
%
l
f
h
Range within which tones
are accepted
Range within which tones
are rejected
±0.75
±3.5
Frequency deviation
reject
%
Accept signal level per
tone
Reject signal level per
tone
Positive and Negative
twist accept
Noise tolerance
37.78
0.22
dBm
dBm
dBm
dB
–43.78
7
Band-limited random noise
300 to 3400 Hz. Present
only when tone is present.
Speech level is in ASL
(Active Speech Level).
Over the CAS signal level
range –16 dBm to –30 dBm
per performance objectives
stated in SR-TSV-002476
appendices A&B.
SNR
TONE
tbd
20
tbd
tbd
Speech tolerance
tbd
tbd
dB
Tone alert guard time and wetting pulse signal
Early guard time – 1
Disabled
egt
ugt
–
8.3
–
8.5
–
8.7
ms
ms
ms
ms
– 2
– 3
– 4
10.1
13.4
19.5
24.5
29.5
34.5
17.5
19.5
21.5
24.5
10.3
13.7
20
25
30
35
18
20
22
25
10.5
14.0
20.5
25.5
30.5
35.5
18.5
20.5
22.5
25.5
Up guard time
– 1
– 2
– 3
– 4
Down guard time – 1
dgt
– 2
– 3
– 4
Wetting pulse signal
delay
Delay after the Alert Signal
falling edge
wpd
14.8
15
15.2
32 (34)
Rev. A2, 25-Aug-98
Target Specification
U3900BM
Electrical Characteristics (continued)
Parameters
FSK detection
Input signal power level
Test Conditions / Pins Symbol
Min.
Typ.
Max.
–1.5
–1.5
1212
Unit
Fig.
1)
On-HOOK mode
On-HOOK mode
Off-HOOK mode
Off-HOOK mode
Pifon
Prjon
Pifoff
Prjoff
–38
–44
–38
–44
1188
dBm
dBm
dBm
dBm
baud
2)
2)
Reject signal level (threshold)
3)
Input signal level
Reject signal level (threshold)
Transmission rate
T
r
1200
(CCITT V23 & BELL 202)
Space frequency (CCITT V23)
Mark frequency (CCITT V23)
Space frequency (BELL 202)
Mark frequency (BELL 202)
Signal-to-noise ratio
SfV
MfV
SfB
MfB
S/N fsk
2079
1287
1178
1188
20
2100
1300
2200
1200
2121
1313
2222
1212
200 – 340 baud
dBm
1)
2)
3)
Referenced to a 600 termination at the CPE Tip and Ring interface. Input signal at Pins CLI1 and CLI2.
Signal lower than –43.8 dBm is rejected.
Referenced to a 600 termination at the CPE Tip and Ring interface. With a maximum gain in the RX chain.
Input signal at Pin VL.
15 Package Information
9.15
8.65
Package SSO44
Dimensions in mm
18.05
17.80
7.50
7.30
2.35
0.3
0.8
0.25
0.10
0.25
10.50
10.20
16.8
44
23
technical drawings
according to DIN
specifications
13040
1
22
Rev. A2, 25-Aug-98
33 (34)
Target Specification
U3900BM
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of
ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or
unauthorized use.
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
34 (34)
Rev. A2, 25-Aug-98
Target Specification
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