U4930B [TEMIC]
Consumer Circuit, PDIP52,;
| 型号： | U4930B |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Consumer Circuit, PDIP52, 光电二极管 商用集成电路 |
| 文件： | 总26页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U4930B
Single Chip TV Baseband Processor
Description
2
The U4930B is an alignment-free, I C-bus controlled TV processor, RGB control, the sync and deflection
baseband processor that has been designed for use with processor.
the baseband delay line U3665M and the SECAM
decoder U4935B.
The IC is realized in a bipolar VLSI technology and
The IC includes a multiple video-input selector switch, operates with +5/+8 V supply voltage. Easy interfacing
chroma filters, sharpness control and black level stretcher and the optional add-on SECAM decoder U4935B
function, PAL/NTSC color decoder, luminance provides flexibility to design a multistandard TV.
Features
Multiple video switch with two CVBS inputs and a
SVHS (or third CVBS) input
RGB control with cut-off and white point adjustment,
linear RGB input and fast blanking
Synchronization with drive circuits for H/V
deflection
CVBS output signals for the teletext decoder and a
SCART interface
Vertical compression of the picture for 16:9 on 4:3 TV
sets
Y delay, sharpness control and black level stretcher
function in the luminance channel
2
I C-bus control of all functions,
Integrated and auto-tuned chroma traps, band pass
filters
no manual alignment
Minimum number of external components
PAL/NTSC color decoder with automatic color
standard decoder
Easy interfacing with an add-on SECAM decoder for
multistandard applications
Ordering Information
Extended Type Number
U4930B-A
Package
SDIP52
Remarks
TELEFUNKEN Semiconductors
1 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Figure 1. Block diagram
2 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Pin Description
Pin Connection Diagram
Pin
1
Symbol
NC
Function
Not connected
Pin for testing
2
Test
3
GND
SCP
Ground (deflection)
1
52
51
50
49
NC
Test
Sync
NC
4
Sandcastle pulse output /
H-flyback pulse input
2
5
6
Mute
H out
Mute output filter
Horizontal output
3
GND
SCL
7
H osc.
Vs (8 V)
PHI1
Horizontal oscillator (503 kHz)
8-V supply voltage (deflection)
PHI1 loop filter
8
4
5
6
SCP
SDA
9
Mute
10
11
12
13
14
PHI2
PHI2 loop filter
48
47
46
CVBS–TXT
C (SVHS)
C
Saw
Vertical sawtooth capacitor
Reference current
H out
H osc
I
ref
V drive(+)
V drive(–)
Vertical drive (positive)
Y (SVHS) /
CVBS – 3
7
8
Vertical drive (negative) /
vertical pulse
45
44
43
42
41
40
39
38
37
36
VS (8 V)
15
16
17
18
19
20
21
22
23
24
25
26
Vs
NC
Supply voltage (digital)
Not connected
CVBS – 2
9
PHI 1
PHI 2
NC
Not connected
CVBS – 1
CVBS–SCART
C BPH
NC
Not connected
10
ACL
Vs (8 V)
R out
G out
B out
GND
Automatic contrast limiting filter
8-V supply voltage (RGB)
R output
C saw 11
G output
Iref
12
13
C Phase
B output
Ground (RGB)
V drive (+)
– (B–Y) out
– (R–Y) out
V
Beam current limiter input
BCL
U4930B
Vs (5 V)
5-V supply voltage
(luminance/chrominance)
V drive (–) 14
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
B in
G in
B input
VS
15
C
freq
G input
R in
R input
16
NC
GND
Insert. sw.
–(B–Y) in
–(R–Y) in
Xtal1
Insertion switch
–(B–Y) input
17
18
19
NC
NC
SEC ref
–(R–Y) input
Crystal 4.43 MHz
APC filter
35
34
33
32
Xtal 2
APC
Xtal2
Crystal 3.58 MHz
SECAM reference output
Ground (luminance/chrominance)
Ident filter (frequency)
–(R–Y) output
ACL
APC
SEC
ref
GND
Xtal 1
VS (8 V) 20
C
freq.
21
22
23
– (R–Y) in
– (B–Y) in
R out
G out
B out
–(R–Y) out
–(B–Y) out
–(B–Y) output
31
C
phase
Ident filter (PAL phase)
Black peak hold time constant
C
BPH
30
29
Insert. sw.
R in
43 CVBS–SCART CVBS-SCART output
44
45
46
CVBS–1
CVBS–2
Y(SVHS)
CVBS-1 input
CVBS-2 input
GND 24
Y(SVHS) input
(or CVBS-3 input)
V BCL
25
28
27
G in
B in
47
48
49
50
51
52
C(SVHS)
C(SVHS) input
26
VS (5 V)
CVBS–TXT CVBS-TXT output
2
SDA
SCL
NC
SDA (I C-bus)
96 11817
2
SCL (I C-bus)
Not connected
Sync
Sync separator input
Figure 2. Pin connection diagram
TELEFUNKEN Semiconductors
3 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
I2C–Bus Specification
2
The I C-bus is a bi-directional, two-wire bus for inter- The module address for the U4930B is “BA”
or
hex
communication between the microcontroller and the IC. “1011 1010” in the write mode.
2
The transmission is done over a serial data line (SDA) and
synchronized by a serial clock line (SCL). Both lines are
LOW activ.
The IC differentiates between normal and autoincrement
mode transmission. For the autoincrement mode, set the
sixth bit of the subaddress byte to “1”.
Each transmission must begin with a start condition and
end with a stop condition. Between a start and a stop
condition, when SCL is HIGH, the data line SDA must be
stable. Only while SCL is LOW is the data line allowed
to change. Each transmission consists of at least three
bytes. Each byte has to be followed immediately by an
acknowledge bit “A”.
In the autoincrement mode, the subaddress can be
followed by more than one byte. The bytes from the third
byte on will all be interpreted as data. The subaddress will
be internally automatically incremented and the IC stores
the data successively in the correct registers.
By programming the read/write bit “1” – LSB in the
module address byte – the IC provides information about
its internal status. When POD is read out for the first time,
The maximum clock frequency is 100 kHz.
TTL level (HIGH > 3 V, LOW < 1.5 V) is used for this bit is “1”. All other read out result in “0” until the next
driving.
power down / up process occurs.
Write mode (module address is “1011 1010”2):
1. Normal mode
MSB
LSB
MSB
X X 0
LSB
D7
D7
D0
D0
start
stop
A
A
A
module address
subaddress
data byte
2. Autoincrement mode
MSB
LSB
0
MSB
LSB
start
A
A
A
A
X X 1
module address
subaddress a
data byte 1
data byte n
. . .
stop
A
data byte a + 1
Read mode (module address is “1011 1011”2):
MSB
LSB
D7
start
stop
A
A = Acknowledge bit
module address
readable data byte
95 10854
Figure 3. I2C-bus transmission modes of the U4930B
4 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Subaddress and Data Bytes
Sub–ad-
dress
Data Byte
Register
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
1. Brightness *)
2. Contrast *)
3. Tint *)
4. Saturation *)
5. Sharpness *)
6. R – drive
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
x
x
x
x
x
x
x
BRI6
CON6
TIN6
SAT6
x
BRI5
CON5
TIN5
SAT5
SH5
RDR5
BDR5
RCO5
GCO5
BCO5
TRP0
YDL0
x
HSH5
VSL5
VSZ5
SCO5
VSH5
FFA
BRI4
CON4
TIN4
SAT4
SH4
RDR4
BDR4
RCO4
GCO4
BCO4
BRI3
CON3
TIN3
SAT3
SH3
RDR3
BDR3
RCO3
GCO3
BCO3
BRI2
CON2
TIN2
SAT2
SH2
RDR2
BDR2
RCO2
GCO2
BCO2
3.58
BRI1
CON1
TIN1
SAT1
SH1
RDR1
BDR1
RCO1
GCO1
BCO1
NTSC
ISA1
BRI0
CON0
TIN0
SAT0
SH0
RDR0
BDR0
RCO0
GCO0
BCO0
SEC
x
x
7. B – drive
8. R – cut off
9. G – cut off
10. B – cut off
11. VideoSW1
12. VideoSW2
13. VideoSW3
14. H – shift
15. V – slope
16. V – size
17. S – correction
18. V – shift
RCO7
GCO7
BCO7
RCO6
GCO6
BCO6
TRP1
YDL1
x
x
x
x
x
x
x
x
x
x
TRPD AUTO
YDLS
BPFC
HSH4
VSL4
VSZ4
SCO4
VSH4
ISB1
BPFD VMUT
ISB0
ISA0
BLS
PACL
HSH0
VSL0
VSZ0
SCO0
VSH0
VPE
x
x
HSH3
VSL3
VSZ3
SCO3
VSH3
HSH2
VSL2
VSZ2
SCO2
VSH2
HPD
HSH1
VSL1
VSZ1
SCO1
VSH1
SERV
COMP
x
x
FFB
19. DeflectionSW
VDSM PH1T
Readable Data Byte
POD 3.58
60HZ
MUTE
n.u.
NTSC
SEC
STID
x
= Don’t care
= Will be executed during the vertical fly-back time
*)
n.u. = not used
TELEFUNKEN Semiconductors
5 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Data Byte Input Conditions
Initial and
Nominal
Settings
Function
Bitname
Input Conditions
Forced color standard
select
SEC, NTSC, 3.58
3.58
NTSC
SEC
Color standard
PAL – 4.43
PAL – 3.58
NTSC – 3.58
NTSC – 4.43
SECAM
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
PAL – 4.43
Auto mode
AUTO
0 = forced color standard
1 = automatic search for the color standard
Forced
ON
Trap switch disabled
Trap select
TRPD
0 = chroma trap ON
1 = chroma trap OFF
TRP0, TRP1
TRP1
TRP0 trap for
0
0
1
SECAM
PAL/NTSC
CVBS-1
1
PAL/NTSC
CVBS-TXT switch
ISA0, ISA1
ISA1
ISA0 CVBS-TXT/ decoder output
0
0
1
0
1
CVBS–1
0
CVBS–2
1
Y(SVHS) + C(SVHS)
CVBS-3
1
CVBS-SCART switch ISB0, ISB1
ISB1
ISB0 CVBS–SCART output
0
0
CVBS–1
0
1
CVBS–2
CVBS-1
1
0
Y(SVHS) + C(SVHS)
CVBS–3
1
1
Y – delay
YDLS, YDL0,
YDL1
YDL1
YDL0
YDLS
Delay time (ns)
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
90
120
180
240
300
360
240 ns
6 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Data Byte Input Conditions (continued)
Function
Bitname
Input Conditions
Initial and
Nominal
Settings
Peak ACL
PACL
BLS
0 = peak ACL detection at 120 IRE
1 = peak ACL detection at 150 IRE
150 IRE
Black-level stretcher
Video mute switch
0 = black level stretcher OFF
1 = black level stretcher ON
OFF
VMUT
BPFD
BPFC
COMP
VPE
0 = video mute OFF
1 = video mute ON
OFF
Band pass filter disable
0 = chroma band pass filter ON
1 = chroma band pass filter OFF
ON
Band pass filter
correction
0 = chroma band pass filter correction ON
1 = chroma band pass filter correction OFF
OFF
Compressed mode
Vertical pulse enable
Service switch
0 = V – size normal
1 = V – size compressed
Normal
0 = vertical sawtooth
1 = vertical pulse
Vert.
sawtooth
SERV
HPD
0 = vertical deflection ON
1 = vertical deflection OFF (service mode)
ON
Horizontal pulse enable
PHI1 time constant
0 = horizontal pulse enabled
1 = horizontal pulse disabled
Enabled
FAST
PH1T
0 = PHI1 time constant FAST
1 = PHI1 time constant SLOW
(during vertical retrace FAST)
Vertical divider
VDSM
0 = normal operation of the vertical divider
1 = vertical divider switched to search mode
valid only for PHI1 loop locked
Normal
Search
Forced field frequency
FFB, FFA
FFB
|
|
|
|
FFA
|
|
|
|
0
0
1
0
1
0
search
forced 60 Hz
forced 50 Hz
valid only for PHI1 loop not locked
TELEFUNKEN Semiconductors
7 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Readable Status Bits
Function
Bitname
Input Conditions
0 = search mode active
1 = color standard identified
Search mode indication
STID
Color standard decoder
mode
SEC, NTSC,
3.58
3.58
NTSC
SEC
Color standard
PAL – 4.43
PAL – 3.58
NTSC – 3.58
NTSC – 4.43
SECAM
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
Power down indication
PHI1 lock indication
POD
0 = normal mode
1 = power down occured since last reading
MUTE
60HZ
0 = PHI1 loop locked
1 = PHI1 loop not locked (mute)
Field frequency indication
0 = field frequency 60 Hz
1 = field frequency 60 Hz
Nominal Settings
Register
Subaddress
Control Range
Nominal Settings
(hex)
00
01
02
03
04
05
06
07
08
09
0D
0E
0F
10
11
1.
2.
3.
4.
5.
6.
7.
8.
9.
Brightness
Contrast
Tint
0 to 127
0 to 127
0 to 127
0 to 127
0 to 63
0 to 63
0 to 63
0 to 255
0 to 255
0 to 255
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
71
58
64
Saturation
Sharpness
R – drive
B – drive
R – cut off
G – cut off
72
16
30
30
128
128
128
32
10. B – cut off
14. H – shift
15. V – slope
16. V – size
32
32
17. S – correction
18. V – shift
32
32
8 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Absolute Maximum Ratings
Reference point Pins 3, 24 and 37, unless otherwise specified
Parameters
Symbol
Pin
Value
Unit
Supply voltage
Output currents
V
8, 20
26
9.0
5.5
V
V
s
I
6
5
+150
mA
°C
°C
V
out
Junction temperature
T
j
Storage temperature range
Electrostatic handling *)
T
stg
–25 to +150
±200
V
ESD
All pins
*) Equivalent to discharging a 200 pF capacitor via a 0- resistor
Operating Range
Parameters
Supply voltage range
Symbol
Pin
Value
Unit
V
s
8, 20
26
7.6 to 8.4
4.75 to 5.25
V
V
Ambient temperature
T
amb
0 to +70
°C
Thermal Resistance
Parameters
Symbol
Test Condition
Value
40
Unit
K/W
Junction ambient
R
thJA
When soldered
to PCB
TELEFUNKEN Semiconductors
9 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Electrical Characteristics
V = 5 V/ 8 V, T
= 25°C; reference point Pins 3, 24 and 37, unless otherwise specified
S
amb
Test conditions: nominal settings (see tables on pages 7, 8 and 9), CVBS-1 = 1 V (peak-to-peak value),
unless otherwise specified
Parameters
Test Conditions / Pins Symbol
Min.
Typ.
Max.
Unit
DC supply
Supply voltage
Pin 8
Pin 20
Pin 26
V
s
8
8
5
V
V
V
Supply current
Pin 8
Pin 20
Pin 26
I
25
20
65
mA
mA
mA
s
2
I C bus
Input voltage for HIGH level
Input voltage for LOW level
Input current
Pins 49, 50
Pins 49, 50
V
3.0
V
V
A
V
V
iH
V
iL
1.5
1
Pins 49, 50
I
i
Output voltage for LOW level
Power down reset threshold level
Video input selector – Inputs
Isink = 3 mA, Pin 49
Pin 8
V
oL
0.4
V
4
s
CVBS-1 input signal
(peak-to-peak value)
Pin 44
Pin 44
v
1.0
2.1
1.4
1.4
V
44
CVBS-1 clamping level
CVBS-1 input impedance
V
V
44
Input voltage over
clamping level
Pin 44
Z44
1
1
1
M
CVBS-2 input signal
(peak-to-peak value)
Pin 45
v
45
1.0
2.1
V
CVBS-2 clamping level
CVBS-2 input impedance
Pin 45
V
V
45
Input voltage over
clamping level
Pin 45
Z
M
45
Y(SVHS) or CVBS-3 input signal
(peak-to-peak value)
Pin 46
v
46
1.0
2.1
1.4
V
Y(SVHS) or CVBS-3 clamping level
Pin 46
V
V
46
Y(SVHS) or CVBS-3 input impedance Input voltage over
clamping level
Z
M
46
Pin 46
C(SVHS) input signal (burst amplitude) Chroma/ burst ratio =
v
47
0.3
0.42
V
(peak-to-peak value)
C(SVHS) dc level
2.2/1
Pin 47
Pin 47
Pin 47
V
2.3
40
V
k
47
C(SVHS) input impedance
Z
47
10 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Electrical Characteristics (continued)
Parameters
Test Conditions / Pins Symbol
Min.
0.8
Typ.
1.0
Max.
1.2
Unit
V
Video input selector – Outputs
CVBS-SCART output signal
(peak-to-peak value)
Pin 43
Pin 43
v
43
CVBS-SCART black level
V
43
2.4
10
V
CVBS-SCART output frequency
characteristic
3 dB bandwidth
f
MHz
BW
Pin 43
Pin 43
Pin 48
CVBS-SCART output impedance
Z
250
2.4
43
CVBS-TXT output signal
(peak-to-peak value)
v
48
1.6
2.0
V
CVBS-TXT black level
Pin 48
V
2.5
7
V
48
CVBS-TXT output frequency
characteristic
3 dB bandwidth
f
MHz
BW
Pin 48
CVBS-TXT output impedance
Pin 48
Z
250
48
Video input selector
Attenuation of non selected
CVBS-input signal
Pins 43, 48
G
50
20
dB
att
Luminance processing
Chroma trap filter frequencies
– PAL / NTSC
– SECAM (combined trap filter)
f
fsc
4.25
4.406
MHz
dB
Color subcarrier suppression at trap
frequencies
All standards
G
att
Y delay time min.
t
90
ns
ns
dmin
Y delay time max.
t
360
dmax
Sharpness control curve
Sharpness center frequency
See figure 4
f
2
MHz
mV
RGB output level difference between
BLS on and BLS off
Black-peak level of
the luminance signal
at 30 IRE on CVBS-1
Pins 21, 22, 23
V
o
–400
–100
–300
–200
+100
RGB output level difference between
BLS on and BLS off
Black-peak level of
the luminance signal
at 70 IRE on CVBS-1
Pins 21, 22, 23
V
o
0
mV
dB
RGB output level ratio between
VMUTE on and VMUTE off
CVBS-1 5 MHz
signal (note 1)
Pins 21, 22, 23
–40
TELEFUNKEN Semiconductors
11 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Electrical Characteristics (continued)
Parameters
Test Conditions / Pins Symbol
Min.
Typ.
0.53
Max.
Unit
V
Chrominance processing – Outputs
–(R–Y) output signal amplitude
(peak-to-peak value)
C (SVHS) 0.3 V
(peak-to-peak level)
burst amplitude
Pin 39
v
39
–(R–Y) black level
Pin 39
V
39
2.4
V
–(R–Y) output frequency characteristic 3 dB bandwidth
Pin 39
f
0.8
MHz
BW
–(R–Y) output impedance
Pin 39
Z
100
39
–(B–Y) output signal amplitude
(peak-to-peak value)
C (SVHS) 0.3 V
v
40
0.67
V
(peak-to-peak level)
burst amplitude
Pin 40
–(B–Y) black level
Pin 40
V
40
2.4
V
–(B–Y) output frequency characteristic 3 dB bandwidth
Pin 40
f
0.8
MHz
BW
–(B–Y) output impedance
Pin 40
During vertical
blanking Pin 36
PAL/NTSC forced or
identified Pin 36
SECAM forced or
identified Pin 36
Pin 36
Z
100
0.3
40
SECAM reference output signal
amplitude (peak-to-peak value)
v
36
V
V
V
SECAM reference output dc voltage
SECAM reference output dc voltage
SECAM reference frequency
V
V
1.5
4.4
36
36
f
4.43
180
MHz
A
ref
Required current (from U4935B) to
stop PAL/ NTSC identification
SECAM identified
by U4935B Pin 36
I
120
26
36
Chrominance processing
Chroma bandpass filter center
frequency
Correction OFF
Correction ON
f
fsc
fsc+0.3
MHz
ACC control range
ACC
G
dB
dB
Change in amplitude of –(R–Y),
Variable C (SVHS)
3
–(B–Y)-signals over ACC control range +6/–20 dB
Pins 39, 40
C (SVHS) input level at killer ON
Related to nom. input
Pins 21, 22, 23
v
–45
–40
20
dB
i
Color remaining at killer ON
Pins 21, 22, 23
v
o
mV
Hz
Oscillator catching range
(fsc = 4.43 and 3.58 MHz)
Referred to the free
f
±300
±600
running frequency f
sc
Tint control range (0 to 127 steps)
NTSC-signal
45
°
12 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Electrical Characteristics (continued)
Parameters
Test Conditions / Pins Symbol
Min.
Typ.
1.05
Max.
Unit
V
RGB processing – Inputs
–(R–Y) input signal
(peak-to-peak value)
All standards
(SECAM with
U4935B)
v
32
Pin 32
Pin 32
Pin 32
–(R–Y) clamping level
–(R–Y) input impedance
V
3.0
V
M
V
32
32
31
Z
1
1
–(B–Y) input signal
(peak-to-peak value)
All standards
(SECAM with
U4935B)
v
1.33
Pin 31
Pin 31
Pin 31
–(B–Y) clamping level
–(B–Y) input impedance
V
31
3.0
0.7
V
M
V
Z
31
RGB insertion input signals
(peak-to-peak value)
For an output signal
of 2 V (black-to-
white)
v
27,28,29
Pins 27, 28, 29
RGB insertion clamping level
RGB insertion input impedance
Pins 27, 28, 29
Pins 27, 28, 29
Pin 30
V
2.6
V
M
V
27,28,29
Z
1
27,28,29
Insertion switch input voltage for
no data insertion
V
30
V
30
V
30
0.3
3.0
5.0
Insertion switch input voltage for
data insertion
Pin 30
0.9
4.0
V
V
Insertion switch input voltage for OSD Note 2
Pin 30
RGB processing
Saturation control curve
See figure 5
Saturation control range (step 1 to 127)
Saturation attenuation (step 0 to 127)
Contrast control curve
Pins 21, 22, 23
Pins 21, 22, 23
G
G
22
50
dB
dB
sat.
sat.
See figure 6
Pins 21, 22, 23
See figure 7
Contrast control range (step 0 to 127)
Brightness control curve
G
contr.
35
dB
Brightness control range (step 0 to 127)
R, B – drive control range (step 0 to 63)
RGB cut off control curve
Pins 21, 22, 23
Pins 21, 23
V
2
V
21,22,23
G
6.0
dB
21,23
See figure 8
RGB cut off control range (step 0 to 255)
Pins 21, 22, 23
Pins 21, 22, 23
V
1.7
2.0
2.3
V
21,22,23
RGB output signal ratio between
V(Pin 25) = 3.6 V and V(Pin 25) = 2.2 V
(Beam current limiting)
G
25
–26
dB
TELEFUNKEN Semiconductors
13 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Electrical Characteristics (continued)
Parameters
Test Conditions / Pins
Symbol Min.
Typ. Max.
Unit
RGB processing – Outputs
RGB output signals (peak-to-peak value)
Pins 21, 22, 23
Contrast max
v
v
1.7
3.0
2.0
3.4
2.3
V
V
21,22,23
Max. RGB output signals
(peak-to-peak value)
21,22,23
Pins 21, 22, 23
Pins 21, 22, 23
Pins 21, 22
RGB output black level
V
2.6
3.0
0
3.4
V
21,22,23
Black level difference R–G
Black level difference G–B
Black level difference R–B
V –V
oR oG
–100
–100
–100
+100
+100
+100
mV
mV
mV
Pins 22, 23
V
–V
0
oG oB
Pins 21, 23
V –V
oR oB
0
RGB output frequency characteristic
3 dB bandwidth
f
BW
from
Pins 21, 22, 23
with 4.43 MHz trap
with 3.58 MHz trap
without trap
CVBS-1, CVBS-2
3.1
2.6
8
MHz
CVBS-1, CVBS-2, Y(SVHS)
–(R–Y), –(B–Y) input
RGB insertion inputs
4
10
Horizontal deflection
Minimal current during sync pulse
No sync input signal
I
–0.1
15.7
mA
52min
Note 3
Pin 52
Horizontal free running frequency
No sync input signal
Pin 7
f
kHz
osc
Horizontal catching range
PHI1 time constant change
Pin 7
f
350
7.5
1.6
Hz
dB
V
Note 4
Pin 9
Pin 4
Sandcastle pulse level during vertical
blanking
V
4
4
4
Sandcastle pulse level during horizontal
blanking
Pin 4
V
2.9
V
Sandcastle pulse level during BGP
Burst gate pulse (BGP) position
Pin 4
V
4.5
2
V
s
Time difference between
the beginning of BGP
and the end of sync
t
1
pulse
Pin 4
Pin 4
Pin 6
BGP width
t
6
s
V
s
w
Horizontal pulse level
Horizontal pulse position
V
oH
4.0
8.5
Time between the start
of the horizontal out and
the beginning of the
sync pulse (Pin 52)
Pin 6
t
2
Horizontal pulse width
Pin 6
t
w
26
s
14 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Electrical Characteristics (continued)
Parameters
Horizontal processing
Test Conditions / Pins
Symbol Min.
Typ.
Max.
Unit
Horizontal stop function
Horizontal shift range
HPD = 1 Pin 6
V
4.0
1.5
V
s
o
Hshift = max, min
Pin 6
t
Hsh
Vertical deflection
Reference voltage
Pin 12
V
ref
4
V
Vertical oscillator free running frequency
– search
– forced 50 Hz
No sync input signal
Pin 14
f
o
44
48
55
Hz
Hz
Hz
– forced 60 Hz
Vertical oscillator locking range
Pin 14
n
l
233
352.5 lines/
field
Vertical drive out common mode current
Vertical drive out amplitude
Vertical processing
Pins 13, 14
Pins 13, 14
I
–200
75
A
A
13,14
I
13,14
Vertical slope control curve
Vertical slope control range
See figure 9
Vslope = max, min
Pin 11
V
%
%
%
15
20
15
11
Vertical size control curve
Vertical size control range
See figure 10
Vsize = max, min
V
13,14
Pins 13, 14
S-correction control curve
S-correction control range
See figure 11
Scorr. = max, min
V
13,1
4
Pins 13, 14
Vertical shift control curve
Vertical shift control range
See figure 12
Vshift = max, min
V
V
%
%
5
13,14
Pins 13, 14
Vertical amplitude reduction for
compressed mode
COMP = 1
25
13,14
Pins 13, 14
Notes
1.
2.
e.g.: R output level ratio = 20 log [ v
/ v
] [dB]
R (VMUTE(ON))
R (VMUTE(OFF))
Required input voltage to insert ”black level” at the RGB outputs, so that OSD (on screen display) signals
can be added to the outputs
3.
4.
Measure the current at Pin 52 for a vertical period at Pin 11 of 233 lines per field
Measure the Pin 9 output current peak-to-peak amplitude
PHI1 time constant change = 20 log [i
= 0 /
PHI1T
= 1] [dB]
iPHI1T
TELEFUNKEN Semiconductors
15 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Control Ranges of Luminance, Chrominance and R/G/B Processing
4.5
+6
4.0
max.
3.5
3.0
2.5
2.0
1.5
nom.
min.
0
–6
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
20
40
60
Steps
80
100 120
95 10281
f ( MHz )
95 10284
Figure 7. Brightness control range
Figure 4. Sharpness control range
4.5
4.0
3.5
3.0
2.5
2.0
1.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
40
80
120 160 200 240
Steps
0
20
40
60
Steps
80
100 120
95 10285
95 10283
Figure 8. Cut-off control range
Figure 5. Saturation control range
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
20
40
60
Steps
80
100 120
95 10282
Figure 6. Contrast control range
16 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Control Ranges of Deflection
Note: T = 1 vertical period
100
75
100
75
50
50
25
25
0
0
–25
–50
–75
–25
–50
–75
–100
–100
T/2
T
T/2
T
95 10286
Time
95 10288
Time
Figure 9. Vertical slope control range
Figure 11. S-correction control range
100
100
75
75
50
50
25
25
0
0
–25
–50
–75
–100
–25
–50
–75
–100
T/2
T
T/2
T
95 10287
Time
95 10289
Time
Figure 10. Vertical size control range
Figure 12. Vertical shift control range
TELEFUNKEN Semiconductors
17 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Internal Pin Configuration
8 V
8 V
95 11291
H OUT
33 k
8 V
200 A
200
2.8 V
5.2 V
4
VBLK
BGP
200
6
60
A
60 A
Figure 15. Horizontal output
8 V
3.3 V
95 11296
300
7
Figure 13. Sandcastle-pulse output
600 k
300
8 V
800 A
80 A
125 A
95 11287
Figure 16. Horizontal oscillator
8 V
4 V
48 k
6 k
9
5.5 V
5
125 A
500 A
350 A
PH1T
H
4
95 11289
95 11286
Figure 14. Mute output
Figure 17. PHI1 loop filter
18 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
8 V
7 V
8 V
10
13
5 V
125 A
2 A
100 A
HFBP
95 11293
95 11290
Figure 21. Vertical drive (positive)
Figure 18. PHI2 loop filter
8 V
7 V
8 V
100 k
14
11
100 A
VOUT
VPE
3
A
19
(21
for 60 Hz)
A
A
+
VSL
2 V
95 11292
95 11295
Figure 22. Vertical drive (negative)/vertical pulse
Figure 19. Vertical sawtooth capacitor
8 V
15
12
4 V
100 A
95 11283
95 11294
Figure 20. Reference current (Iref)
Figure 23. Vs (digital)
TELEFUNKEN Semiconductors
19 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
5 V
5 V
2.5 V
60
A
30 A
1 V
27, 28, 29
3 V
40 k
3.5 V
BGP
16 k
10 k
19
2 V
ACL
30
A
90
A
95 11239
5 mA
95 11242
Figure 27. B/G/R input
5 V
Figure 24. ACL filter
8 V
30 A
220 A
50
30
1 V
21, 22, 23
95 11240
95 11243
Figure 28. Insertion switch
Figure 25. R/G/B output
5 V
5 V
60 A
40 k
30
A
1 V
3 V
3.5 V
BGP
31, 32
16 k
25
90
A
60
A
10 k
95 11238
95 11241
Figure 26. BCL input
Figure 29. –(B-Y)/–(R–Y) input
20 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
33
8 V
5 V
5 V
5.6 V
20 k
11 pF
1.3 k
100
36
250 A
50 A
90 A
95 11280
Figure 30. Crystal 4.43 MHz
5 V
95 11282
Figure 33. SECAM reference output
5 V
34
3 V
38
4 k
BGP
560 A
100 A
20 A
50 k
2.5 V
BGP
95 11278
95 11250
Figure 31. APC filter
35
Figure 34. Ident filter (frequency)
5 V
5 V
5 V
200
100
39, 40
1.3 k
8 pF
250 A
250 A
50 A
Secam
95 11279
95 11281
Figure 32. Crystal 3.58 MHz
Figure 35. –(R-Y)/–(B–Y) output
TELEFUNKEN Semiconductors
21 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
5 V
5 V
2.9 V
41
44,45
100
BGP
120 A
50 k
2.6 V
100 k
ISA / ISB
95 11249
95 11245
Figure 36. Ident filter (PAL phase)
Figure 39. CVBS-1/CVBS-2 input
5 V
5 V
42
2.9 V
100
3 k
A
3 k
3 V
46
100
60 A
210 A
BLK
3
95 11244
ISA / ISB
Figure 37. Black peak hold
95 11246
Figure 40. Y(SVHS) input
5 V
5 V
100
43
47
100
170 A
100 A
40 k
2.4 V
ISA / ISB
95 11248
95 11247
Figure 38. CVBS-SCART output
Figure 41. C(SVHS) input
22 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
5 V
8 V
10 A
48
40 k
50
2.3 V
330 A
95 11297
95 11285
Figure 44. SCL (I2C-Bus)
8 V
Figure 42. CVBS-TXT output
8 V
95 11288
10 A
49
2.3 V
ACKN
1 k
6.5 V
95 11284
52
1 k
Figure 43. SDA (I2C–Bus)
Figure 45. Sync separation input
TELEFUNKEN Semiconductors
23 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Figure 46. Basic application circuit
24 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Package Information
Package SDIP52
Dimensions in mm
15.49
14.99
46.6 max
46.4 max
14.1
13.8
0.6 min
4.7 max
0.3 max
3.3
0.5
0.4
1.1
1.0
0.8
0.7
1.778
17.0
15.2
44.45
52
27
technical drawings
according to DIN
specifications
96 11965
1
26
TELEFUNKEN Semiconductors
25 (26)
Rev. A1, 28-Jan-97
Preliminary Information
U4930B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of
continuous improvements to eliminate the use of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain
such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or
unauthorized use.
TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
26 (26)
TELEFUNKEN Semiconductors
Rev. A1, 28-Jan-97
Preliminary Information
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