28973-DSH-001-A_15 [TE]
Single-Chip SDSL/HDSL Transceiver;
| 型号： | 28973-DSH-001-A_15 |
| 厂家： | 
TE CONNECTIVITY |
| 描述： | Single-Chip SDSL/HDSL Transceiver |
| 文件： | 总119页 (文件大小：974K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.
RS8973
Single-Chip SDSL/HDSL Transceiver
The RS8973 is a full-duplex 2B1Q transceiver based on Conexant’s HDSL technology,
with a built-in frequency synthesizer to support variable rate SDSL applications. It offers
2320 kbps operation, low power consumption, and pin-for-pin compatibility with
Bt8970 and Bt8960.
The RS8973 is a highly integrated device that includes all of the active circuitry
needed for a complete 2B1Q transceiver. In the receive portion of the device, a variable
gain amplifier optimizes the signal level according to the dynamic range of the
analog-to-digital converter. Once the signal is digitized, sophisticated adaptive echo
cancellation, equalization, and detection DSP algorithms reproduce the originally
transmitted far-end signal.
In the transmitter, the transmit source and scrambler operation are programmable
through the microcomputer interface. A highly linear digital-to-analog converter with
programmable gain sets the transmission power for optimal performance. A pulse
shaping filter and a low-distortion line driver generate the signal characteristics needed
to drive a large range of subscriber lines at low distortion.
The integrated frequency synthesizer is ideal for variable rate SDSL applications. The
RS8973 can be programmed to operate at data rates ranging from 144 kbps to
2320 kbps, using a single crystal as a reference clock source.
Distinguishing Features
•
Supports data rates ranging from
144 kbps to 2320 kbps
•
•
Integrated frequency synthesizer
Meets ETSI TS 101 135 (formerly
ETR 152) pulse template, output
power and PSD specifications at 784,
1168 and 2320 kbps data rates,
using the same external support
circuit
•
•
Meets ANSI T1/E1.4/94-006 pulse
template, output power and PSD
specifications at 784 kbps.
Pin-for-pin and software compatible
with Bt8970 and Bt8960
•
•
Supports automatic rate adaptation
Single-chip 2B1Q transceiver
solution
•
•
Low power consumption (under
685 mW at 784 kbps operation)
Glueless interface to Motorola and
Intel processors
The RS8973 is fully compliant with standards for HDSL 2B1Q transmission. Key to
variable rate applications, it can meet the PSD, output power, and pulse shape
requirements, as specified in ETSI TS 101 135 (formerly ETR 152) with the same
support circuit. Therefore, a single design using the RS8973 can be configured through
a simple software command to operate at either 784, 1168, or 2320 kbps and will still
meet these ETSI requirements. No hardware changes are required.
•
•
Flexible monitoring and control
Backwards compatible with Bt8952,
Bt8960, and Bt8970 software API
commands
•
•
ZipStartup™ available for faster link
establishment
RS8953B companion SDSL/HDSL
framers available
JTAG/IEEE Std 1149.1 compliant
100-pin PQFP package
Startup and performance monitoring operations are controlled through the
microprocessor interface. C-language source code supporting these operations is
supplied under a no-fee license agreement from Conexant. The RS8973 includes a
glueless interface to both Intel and Motorola microprocessors.
•
•
•
Functional Block Diagram
–40 °C to +85 °C operation
Applications
•
•
•
•
•
•
•
•
•
Variable rate data access systems
Data access concentrators
E1 and T1 HDSL transport
Internet connectivity
Voice and/or data Pair Gain systems
N × 64 data transport
ISDN BRI concentrators
Cellular base station data links
Campus modems
Variable
Gain
Amplifier
Analog-
to-Digital
Converter
Digital
Signal
Processor
Recovered
Data and
Clock
Analog
Receive
Framer/
Channel
Unit
Clock
Synthesizer
Interface
MPU
Bus
Microcomputer
Interface
Program-
mable
Gain
Pulse
Shaping
Filter
Analog
Transmit
Line
Driver
Transmit
Data
DAC
Data Sheet
Preliminary Information
N8973DSD
June 15, 1999
Ordering Information
Model Number
Package
Operating Temperature
RS8973EPF
100-Pin Plastic Quad Flat Pack
–40 °C to +85 °C
Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is
assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant
products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without
notice.
Conexant and “What’s Next in Communications Technologies” are trademarks of Conexant Systems, Inc.
Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
© 1999 Conexant Systems, Inc.
Printed in U.S.A.
All Rights Reserved
Reader Response: To improve the quality of our publications, we welcome your feedback. Please send comments or
suggestions via e-mail to Conexant Reader Response@conexant.com. Sorry, we can't answer your technical
questions at this address. Please contact your local Conexant sales office or local field applications engineer if you
have technical questions.
N8973DSD
Conexant
Preliminary Information
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1.0
System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Functional Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Receive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Timing Recovery and Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Microcomputer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Test and Diagnostic Interface (JTAG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3 Regenerator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
2.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Transmit Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
Symbol Source Selector/Scrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Variable Gain Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Pulse-Shaping Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Analog CT Reconstruction Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2 Receive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.1
2.2.2
2.2.3
Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4
2.2.3.5
2.2.3.6
2.2.3.7
Digital Front-End. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Offset Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
DC Level Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Signal Level Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Overflow Detection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Far-End Level Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Far-End Level Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.4
Impulse Shortening Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
N8973DSD
Conexant
Preliminary Information
iii
Table of Contents
RS8973
Single-Chip SDSL/HDSL Transceiver
2.2.5
Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.2.5.1
2.2.5.2
Linear Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Nonlinear Echo Canceller (NEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.2.6
Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.2.6.1
2.2.6.2
2.2.6.3
2.2.6.4
2.2.6.5
Digital Automatic Gain Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Feed Forward Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Error Predictor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Decision Feedback Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Microcoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.7
Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.7.1
2.2.7.2
2.2.7.3
2.2.7.4
2.2.7.5
2.2.7.6
Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Error Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Scrambler Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Sync Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Detector Meters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3 Timing Recovery and Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.1
2.3.2
2.3.3
Timing Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Crystal Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Clock Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.4 Channel Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.5 Microcomputer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.5.1
2.5.2
Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Microcomputer Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.5.2.1
2.5.2.2
2.5.2.3
RAM Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Multiplexed Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Separated Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
Interrupt Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Scratch Pad Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.6 Test and Diagnostic Interface (JTAG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
iv
Conexant
Preliminary Information
N8973DSD
RS8973
Table of Contents
Single-Chip SDSL/HDSL Transceiver
3.0
3.0
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
0x00—Global Modes and Status Register (global_modes). . . . . . . . . . . . . . . . . . . . . . . . 3-7
0x01—Serial Monitor Source Select Register (serial_monitor_source). . . . . . . . . . . . . . . 3-8
0x02—Interrupt Mask Register Low (mask_low_reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
0x03—Interrupt Mask Register High (mask_high_reg) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
0x04—Timer Source Register (timer_source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
0x05—IRQ Source Register (irq_source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
0x06—Channel Unit Interface Modes Register (cu_interface_modes) . . . . . . . . . . . . . . 3-11
0x07—Receive Phase Select Register (receive_phase_select) . . . . . . . . . . . . . . . . . . . . 3-12
0x08—Linear Echo Canceller Modes Register (linear_ec_modes) . . . . . . . . . . . . . . . . . 3-12
0x09—Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes) . . . . . . . . . . . . 3-13
0x0A—Decision Feedback Equalizer Modes Register (dfe_modes). . . . . . . . . . . . . . . . . 3-13
0x0B—Transmitter Modes Register (transmitter_modes) . . . . . . . . . . . . . . . . . . . . . . . 3-14
0x0C—Timer Restart Register (timer_restart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
0x0D—Timer Enable Register (timer_enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
0x0E—Timer Continuous Mode Register (timer_continuous). . . . . . . . . . . . . . . . . . . . . 3-16
0x0F—Miscellaneous/Test Register (misc_test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
0x10, 0x11—Startup Timer 1 Interval Register (sut1_low, sut1_high) . . . . . . . . . . . . . . 3-16
0x12, 0x13—Startup Timer 2 Interval Register (sut2_low, sut2_high) . . . . . . . . . . . . . . 3-16
0x14, 0x15—Startup Timer 3 Interval Register (sut3_low, sut3_high) . . . . . . . . . . . . . . 3-17
0x16, 0x17—Startup Timer 4 Interval Register (sut4_low, sut4_high) . . . . . . . . . . . . . . 3-17
0x18, 0x19—Meter Timer Interval Register (meter_low, meter_high). . . . . . . . . . . . . . . 3-17
0x1A, 0x1B—SNR Alarm Timer Interval Register (snr_timer_low, snr_timer_high) . . . . 3-17
0x1C, 0x1D—General Purpose Timer 3 Interval Register (t3_low, t3_high) . . . . . . . . . . 3-17
0x1E, 0x1F—General Purpose Timer 4 Interval Register (t4_low, t4_high) . . . . . . . . . . . 3-17
0x20—Clock Frequency Select Register (clock_freq_select) . . . . . . . . . . . . . . . . . . . . . 3-18
0x21—ADC Control Register (adc_control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
0x22—PLL Modes Register (pll_modes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
0x23—Test Register (test_reg23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
0x24, 0x25—Timing Recovery PLL Phase Offset Register
(pll_phase_offset_low, pll_phase_offset_high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
0x26, 0x27—Receiver DC Offset Register (dc_offset_low, dc_offset_high) . . . . . . . . . . 3-20
0x28—Transmitter Calibration Register (tx_calibrate) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
0x29—Transmitter Gain Register (tx_gain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
0x2A, 0x2B—Noise-Level Histogram Threshold Register
(noise_histogram_th_low, noise_histogram_th_high) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
0x2C, 0x2D—Error Predictor Pause Threshold Register
(ep_pause_th_low, ep_pause_th_high). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
0x2E—Scrambler Synchronization Threshold Register (scr_sync_th) . . . . . . . . . . . . . . 3-22
0x30, 0x31—Far-End High Alarm Threshold Register
(far_end_high_alarm_th_low, far_end_high_alarm_th_high) . . . . . . . . . . . . . . . . . . . . . 3-22
N8973DSD
Conexant
Preliminary Information
v
Table of Contents
RS8973
Single-Chip SDSL/HDSL Transceiver
0x32, 0x33—Far-End Low Alarm Threshold Register
(far_end_low_alarm_th_low, far_end_low_alarm_th_high) . . . . . . . . . . . . . . . . . . . . . . 3-22
0x34, 0x35—SNR Alarm Threshold Register (snr_alarm_th_low, snr_alarm_th_high) . . 3-22
0x36, 0x37—Cursor Level Register (cursor_level_low, cursor_level_high). . . . . . . . . . . 3-22
0x38, 0x39—DAGC Target Register (dagc_target_low, dagc_target_high) . . . . . . . . . . . 3-22
0x3A—Symbol Detector Modes Register (detector_modes). . . . . . . . . . . . . . . . . . . . . . 3-23
0x3B—Peak Detector Delay Register (peak_detector_delay) . . . . . . . . . . . . . . . . . . . . . 3-24
0x3C—Digital AGC Modes Register (dagc_modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
0x3D—Feed Forward Equalizer Modes Register (ffe_modes). . . . . . . . . . . . . . . . . . . . . 3-25
0x3E—Error Predictor Modes Register (ep_modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
0x40, 0x41—Phase Detector Meter Register (pdm_low, pdm_high). . . . . . . . . . . . . . . . 3-26
0x42—Overflow Meter Register (overflow_meter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
0x44, 0x45—DC Level Meter Register (dc_meter_low, dc_meter_high) . . . . . . . . . . . . . 3-27
0x46, 0x47—Signal Level Meter Register (slm_low, slm_high) . . . . . . . . . . . . . . . . . . . 3-27
0x48, 0x49—Far-End Level Meter Register (felm_low, felm_high) . . . . . . . . . . . . . . . . . 3-27
0x4A, 0x4B—Noise Level Histogram Meter Register
(noise_histogram_low, noise_histogram_high). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
0x4C, 0x4D—Bit Error Rate Meter Register (ber_meter_low, ber_meter_high). . . . . . . . 3-28
0x4E—Symbol Histogram Meter Register (symbol_histogram) . . . . . . . . . . . . . . . . . . . 3-28
0x50, 0x51—Noise Level Meter Register (nlm_low, nlm_high) . . . . . . . . . . . . . . . . . . . 3-29
0x5E, 0x5F— PLL Frequency Register (pll_frequency_low, pll_frequency_high). . . . . . . 3-29
0x70—LEC Read Tap Select Register (linear_ec_tap_select_read) . . . . . . . . . . . . . . . . . 3-29
0x71—LEC Write Tap Select Register (linear_ec_tap_select_write) . . . . . . . . . . . . . . . . 3-29
0x72—NEC Read Tap Select Register (nonlinear_ec_tap_select_read) . . . . . . . . . . . . . . 3-30
0x73—NEC Write Tap Select Register (nonlinear_ec_tap_select_write) . . . . . . . . . . . . . 3-30
0x74—DFE Read Tap Select Register (dfe_tap_select_read) . . . . . . . . . . . . . . . . . . . . . 3-30
0x75—DFE Write Tap Select Register (dfe_tap_select_write). . . . . . . . . . . . . . . . . . . . . 3-30
0x76—Scratch Pad Read Tap Select (sp_tap_select_read). . . . . . . . . . . . . . . . . . . . . . . 3-31
0x77—Scratch Pad Write Tap Select (sp_tap_select_write) . . . . . . . . . . . . . . . . . . . . . . 3-31
0x78—Equalizer Read Select Register (eq_add_read) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
0x79—Equalizer Write Select Register (eq_add_write) . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
0x7A—Equalizer Microcode Read Select Register (eq_microcode_add_read). . . . . . . . . 3-33
0x7B—Equalizer Microcode Write Select Register (eq_microcode_add_write) . . . . . . . . 3-33
0x7C–0x7F—Access Data Register (access_data_byte3:0) . . . . . . . . . . . . . . . . . . . . . . 3-33
4.0
Interconnection Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Transmission Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.1
4.1.2
4.1.3
Compromise Hybrid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Impedance-Matching Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Line Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2 DC Blocking Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
vi
Conexant
Preliminary Information
N8973DSD
RS8973
Table of Contents
Single-Chip SDSL/HDSL Transceiver
4.3 Voltage Reference and Compensation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.4 Crystal/Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
5.0
Electrical and Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.4 Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.5 Channel Unit Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.6 Microcomputer Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.7 Test and Diagnostic Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.8 Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.9 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.10 Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.11 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Appendix A: Acronym List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
N8973DSD
Conexant
Preliminary Information
vii
Table of Contents
RS8973
Single-Chip SDSL/HDSL Transceiver
viii
Conexant
Preliminary Information
N8973DSD
RS8973
List of Figures
Single-Chip SDSL/HDSL Transceiver
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 4-1.
Figure 4-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Figure 5-10.
Figure 5-11.
Figure 5-12.
Figure 5-13.
Figure 5-14.
Figure 5-15.
Figure 5-16.
Figure 5-17.
Figure 5-18.
Figure 5-19.
Figure 5-20.
Figure 5-21.
Figure 5-22.
Figure 5-23.
Figure 5-24.
HDSL T1/E1 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Regenerator System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Transmit Section Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
First-Order Echo Cancellation Using the Variable Gain Amplifier. . . . . . . . . . . . . . . . . . . . . 2-5
Receiver Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Digital Front-End Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Timing Recovery and Clock Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Serial Sign-Bit First Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Parallel Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Parallel Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Line Interface Interconnection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Crystal Oscillator Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
MCLK Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Clock Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Channel Unit Interface Timing, Parallel Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Channel Unit Interface Timing, Parallel Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Channel Unit Interface Timing, Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
MCI Write Timing, Intel Mode (MOTEL = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
MCI Write Timing, Motorola Mode (MOTEL = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
MCI Read Timing, Intel Mode (MOTEL = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
MCI Read Timing, Motorola Mode (MOTEL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Internal Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
SMON Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Transmit Pulse Template for Two- and Three-Pair Systems; Normalized Pulse Mask. . . . 5-18
Transmit Pulse Template for One-Pair Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Upper Bound of the Average PSD of a 392 kbaud System . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Upper Bound of the Average PSD of a 584 kbaud System . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Upper Bound of the Average PSD of a 1160 kbaud System . . . . . . . . . . . . . . . . . . . . . . . 5-21
Transmitter Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Standard Output Load (Totem Pole and Three-State Outputs) . . . . . . . . . . . . . . . . . . . . . 5-22
Open-Drain Output Load (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Input Waveforms for Timing Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Output Waveforms for Timing Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Output Waveforms for Three-state Enable and Disable Tests . . . . . . . . . . . . . . . . . . . . . . 5-24
100-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
N8973DSD
Conexant
Preliminary Information
ix
List of Figures
RS8973
Single-Chip SDSL/HDSL Transceiver
x
Conexant
Preliminary Information
N8973DSD
RS8973
List of Tables
Single-Chip SDSL/HDSL Transceiver
List of Tables
Table 1-1.
Table 1-2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 3-1.
Table 3-2.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
Table 4-6.
Table 4-7.
Table 4-8.
Table 4-9.
Table 4-10.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 5-10.
Table 5-11.
Table 5-12.
Table 5-13.
Table 5-14.
Table 5-15.
Table 5-16.
Table 5-17.
Table 5-18.
Table 5-19.
Table 5-20.
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Symbol Source Selector/Scrambler Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Four-Level Bit-to-Symbol Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Two-Level Bit-to-Symbol Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Two-Level Symbol-to-Bit Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Four-Level Symbol-to-Bit Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
JTAG Device Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Address Map of Shared Register Fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Compromise Hybrid Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Antialias Filter Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Line Transformer Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Line Transformer Application-Specific Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Recommended Line Transformer Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
DC Blocking Capacitor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Compensation Capacitor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Bias Current Resistor Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Recommended Crystal Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
MCLK Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
HCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
QCLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Channel Unit Interface Timing Requirements, Parallel Master Mode. . . . . . . . . . . . . . . . . . . 5-6
Channel Unit Interface Switching Characteristics, Parallel Master Mode. . . . . . . . . . . . . . . . 5-6
Channel Unit Interface Timing Requirements, Parallel Slave Mode . . . . . . . . . . . . . . . . . . . . 5-7
Channel Unit Interface Switching Characteristics, Parallel Slave Mode . . . . . . . . . . . . . . . . . 5-7
Channel Unit Interface Timing Requirements, Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Channel Unit Interface Switching Characteristics, Serial Mode . . . . . . . . . . . . . . . . . . . . . . . 5-8
Microcomputer Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Microcomputer Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Test and Diagnostic Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Test and Diagnostic Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Receiver Requirements and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Transmitter Analog Requirements and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Transmit Pulse Template for Two- and Three-Pair Systems . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Transmit Pulse Template for One-Pair Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
N8973DSD
Conexant
Preliminary Information
xi
List of Tables
RS8973
Single-Chip SDSL/HDSL Transceiver
xii
Conexant
Preliminary Information
N8973DSD
1
1.0 System Overview
1.1 Functional Summary
The RS8973 High-bit-rate Digital Subscriber Line (HDSL) transceiver is an
integral component of Conexant's HDSL chipset. System performance of the
chipset allows 2-pair T1, 1-pair E1, 2-pair E1, and 3-pair E1 transmission. With
its built-in frequency synthesizer, it can easily be configured through software for
variable rate Symmetric DSL over Single Pair (SDSL) applications, using a single
10.24 MHz crystal/clock as reference. It can operate at data rates between
144 kbps and 2320 kbps. The major building blocks of a typical HDSL T1/E1
terminal are shown in Figure 1-1.
Figure 1-1. HDSL T1/E1 Terminal
Transformer
and
Hybrid
HDSL
Twisted
Pair
RS8973
Transceiver
T1/E1
RS8953B/
Bt8953A
T1/E1 HDSL
Channel
Unit
Receive
Bt8370
T1/E1
Framer
Line
Transformer
and
Hybrid
HDSL
Twisted
Pair
RS8973
Transceiver
T1/E1
and LIU
Transmit
Line
HDSL
Twisted
Pair
Transformer
and
Hybrid
RS8973
Transceiver
OPTIONAL SECOND, THIRD PAIR
N8973DSD
Conexant
Preliminary Information
1-1
1.0 System Overview
1.1 Functional Summary
RS8973
Single-Chip SDSL/HDSL Transceiver
The RS8973 comprises five major functions: a transmit section, a receive
section, a timing recovery and clock interface, a microcomputer interface, and a
test and diagnostic interface. Figure 1-2 details the connections within and
between each of these functional blocks.
Figure 1-2. Detailed Block Diagram
Receive Section
RXP
RXN
Receive
Channel
Unit
Digital
Front
End
IS
RQ[1]/RDAT
RQ[0]/BCLK
Echo
Canceller
Equalizer
Detector
ADC
VGA
Filter
RXBP
RXBN
Interface
RBCLK
Timing
Recovery/
PLL
HCLK
QCLK
Microcomputer
Interface and
System Control
Clock
Synthesizer
XTALI/MCLK
AD[7:0]
ADDR[7:0]
MUXED
MOTEL
WR/R/W
RD/DS
CS
Crystal
Amplifier
Control
and
Status
XTALO
XOUT
Registers
RBIAS
Microcomputer
Interface
VCOMO
VCOMI
Voltage
Reference
Generator
VCCAP
ALE
VRXP,VRXN
VTXP,VTXN
RST
Timers
READY
IRQ
Diag-
nostics
SMON
TMS
TDI
TCK
TDO
JTAG
Transmit Section
TBCLK
Analog
CT
Reconstruc-
tion Filter
Transmit
Channel
Unit
TXP
TXN
Symbol
Source/
Scrambler
Pulse-
Shaping
Filter
Variable-
Gain
DAC
TQ[1]/TDAT
TQ[0]
Line
Driver
Interface
1-2
Conexant
Preliminary Information
N8973DSD
RS8973
1.0 System Overview
1.1 Functional Summary
Single-Chip SDSL/HDSL Transceiver
1.1.1 Transmit Section
The source of transmitted symbols is programmable through the microcomputer
interface. The primary choices include external 2B1Q-encoded data presented to
the TQ[1,0]/TDAT pins of the channel unit interface, internally looped-back
receive symbols from the detector, or a constant “all 1s” source. The symbols are
then optionally scrambled. Isolated pulses can also be generated to support the
testing of pulse templates.
The digital symbols are transformed to an analog signal by means of the DAC,
which is highly linear to maximize the echo cancellation and detection properties
of the signal. In addition, the transmit power level of the DAC can be adjusted by
means of the Transmitter Gain Register [tx_gain; 0x29] to optimize performance.
The Transmitter Calibration Register [tx_calibrate; 0x28] contains the nominal
setting for the transmitter gain, which is calibrated and hard-coded at the factory.
The pulse-shaping filters, along with the analog continuous time (CT)
reconstruction filter, then condition the signal to minimize crosstalk to adjacent
subscriber lines. This filtering enables the output signal to meet requirements of
ETSI TS 101 135 (formerly ETR 152) specifications for pulse shape, power
spectral density and output power at 784 kbps, 1168 kbps, and 2320 kbps without
any changes required to external components, including the line transformer.
Finally, the differential line driver provides the current driving capabilities and
low-distortion characteristics needed to drive a large range of subscriber lines.
1.1.2 Receive Section
The differential variable gain amplifier (VGA) receives the data from the
subscriber line. Balancing inputs (RXBP, RXBN) are provided to accommodate
first-order transmit echo cancellation through an external hybrid. The gain is
programmable so that the dynamic range of the analog-to-digital converter (ADC)
can be utilized according to the attenuation of the subscriber line.
Digitized receive data is passed to the digital signal processor (DSP) portion
of the RS8973. After DC offset cancellation, the impulse shortening (IS) filter
eliminates long tails caused by the line transformer. A replica of the transmit
signal is subtracted from the total receive signal by a digital echo canceller. The
resultant far-end signal is then conditioned by an equalization stage consisting of
automatic gain control (AGC), a feed-forward equalizer, a decision-feedback
equalizer, and an error predictor. A mode-dependent detector is then used to
recover the 2B1Q-encoded data from the equalized signal. The channel unit
interface then provides an optional descrambling function, followed by parallel or
serial output of the sign, and magnitude bits on pins RQ[1,0]/RDAT. A number of
meters are implemented within the receiver to provide average level indications at
various points in the receive signal path. The receive section also performs remote
unit clock recovery through an on-chip phase lock loop (PLL) circuit.
N8973DSD
Conexant
Preliminary Information
1-3
1.0 System Overview
1.1 Functional Summary
RS8973
Single-Chip SDSL/HDSL Transceiver
1.1.3 Timing Recovery and Clock Interface
The clock interface includes a crystal amplifier and a clock synthesizer module to
reduce the external components needed for clock generation. The crystal
frequency should be 10.24 MHz.
The Clock Synthesizer generates the required internal clock from this
reference clock based on the data rate, as specified by the Clock Frequency Select
Register [clk_select [7:0]; 0x20] and PLL Modes Register [clk_select [9,8];
0x22]. When configured as a remote unit, the PLL module recovers the incoming
data clock and outputs it on the QCLK pin (on the BCLK pin for serial mode
operation). The HCLK output, which is synchronized to the QCLK signal, can be
configured to cycle at 16, 32, or 64 times the symbol rate.
1.1.4 Microcomputer Interface
The microcomputer interface (MCI) provides access to a 256-byte address space
within the transceiver. A combination of direct and indirect addressing methods
are used to access all internal locations. The MCI is designed to interface with
both Intel- and Motorola-style processors with no additional glue logic. A
MOTEL control pin is provided to configure the bus interface control/handshake
lines to conform to common Motorola/Intel conventions. A MUXED control pin
is provided to configure the bus interface address and data lines for multiplexed
or independent data/address bus operation. Little-endian data formatting (least
significant byte of a multibyte word stored at the lowest byte-address location) is
used in all cases, regardless of MOTEL pin selection. A READY control pin is
provided to support wait-state insertion. An Interrupt Request (IRQ) output pin
supports low-latency responses to time-critical events within the transceiver.
Eight 16-bit timers and 10 measurement meters are integrated into the
transceiver. The timers support various metering functions within the receiver
section and off-load the external microcomputer from complex timing operations
associated with startup procedures. Control and monitoring access to the timers
and meters is provided through the MCI.
1.1.5 Test and Diagnostic Interface (JTAG)
The test and diagnostic interface comprises a test access port and a serial monitor
output (SMON). The test access port conforms to IEEE Std 1149.1-1990, (IEEE
Standard Test Access Port and Boundary Scan Architecture). Also referred to as
JTAG, this interface provides direct serial access to each of the transceiver’s I/O
pins. This capability can be used during an in-circuit board test to increase the
testability and reduce the cost of the in-circuit test process.
The serial monitor output can be viewed as a real-time virtual probe for
looking at the transceiver’s internal signals. The programmable signal source is
shifted out serially at 16 times the symbol rate. Most of the receive signal path is
accessible through this output.
1-4
Conexant
Preliminary Information
N8973DSD
RS8973
1.0 System Overview
1.2 Pin Descriptions
Single-Chip SDSL/HDSL Transceiver
1.2 Pin Descriptions
The RS8973 is packaged in a 100-pin plastic quad flat pack (PQFP). The pin
assignments are shown in Figure 1-3. Pin labels, numbers, and I/O assignments
are listed in Table 1-1.
Figure 1-3. Pin Diagram
VDD1
CS
RD/DS
WR/R/W
ALE
IRQ
READY
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
DGND
DGND
VDD2
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RXBN
RXBP
RXN
RXP
AGND
AGND
TXN
AGND
VAA
TXP
NC
NC
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
ATEST2
ATEST1
VAA
RS8973
AD[7]
VAA
MOTEL
MUXED
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
SMON
VDD1
AGND
VTXN
VTXP
VCCAP
VCOMO
VCOMI
RBIAS
VAA
VAA
AGND
VRXN
VRXP
N8973DSD
Conexant
Preliminary Information
1-5
1.0 System Overview
1.2 Pin Descriptions
RS8973
Single-Chip SDSL/HDSL Transceiver
Table 1-1. Pin Descriptions
Pin
Pin
Label
Pin
I/O
Pin
Pin Label
I/O
Pin
I/O
Pin
Pin Label
I/O
Label
1
VDD1
CS
–
I
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ADDR[2]
ADDR[1]
ADDR[0]
SMON
VDD1
I
I
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
VRXP
VRXN
AGND
VAA
OA
OA
–
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AGND
RXP
–
IA
IA
IA
IA
–
2
3
RD/DS
WR/R/W
ALE
I
I
RXN
4
I
O
–
–
–
–
I
–
RXBP
5
I
VAA
–
RXBN
VAA
6
IRQ
OD
OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
DGND
DGND
VDD2
RBIAS
VCOMI
VCOMO
VCCAP
VTXP
VTXN
AGND
VAA
OA
OA
OA
OA
OA
OA
–
7
READY
AD[0]
AGND
VDD1
–
8
–
9
AD[1]
RST
DGND
TQ[1]/TDAT
TQ[0]
–
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AD[2]
HCLK
O
O
–
–
O
I
I
AD[3]
XOUT
I
AD[4]
DGND
VDD1
QCLK
O
O
O
I
AD[5]
–
RQ[1]/RDAT
RQ[0]/BCLK
RBCLK
TBCLK
DTEST5
DTEST6
TDO
AD[6]
XTALO
XTALI/MCLK
VPLL
VAA
–
DGND
DGND
VDD2
ATEST1
ATEST2
NC
IA
IA
OA
OA
IA
IA
OA
–
–
–
–
I
I
–
PGND
I
AD[7]
I/O
I
DTEST1
DTEST2
DTEST3
VPLL
NC
I
MOTEL
MUXED
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
I
NC
O
I
I
I
NC
TDI
I
–
–
I
TXP
TMS
I
I
PGND
VAA
TCK
I
I
DTEST4
AGND
AGND
TXN
–
VDD2
–
I
–
–
OA
–
DGND
DGND
–
I
AGND
AGND
–
1-6
Conexant
Preliminary Information
N8973DSD
RS8973
1.0 System Overview
1.2 Pin Descriptions
Single-Chip SDSL/HDSL Transceiver
Signal definitions are provided in Table 1-2. This is the coding used in the I/O
column:
O
= digital output
OA = analog output
OD = open-drain output
I
= digital input
IA = analog input
I/O = bidirectional
NC = no connect
Table 1-2. Hardware Signal Definitions (1 of 4)
Pin Label
Signal Name
I/O
Definition
Microcomputer Interface (MCI)
MOTEL
Motorola/Intel
I
Selects between Motorola and Intel handshake conventions for the RD/DS and
WR/R/W signals.
MOTEL = 1 for Motorola protocol: DS, R/W
MOTEL = 0 for Intel protocol: RD, WR
ALE
Address Latch
Enable
I
Falling-edge-sensitive input. The value of AD[7:0] when MUXED = 1, or
ADDR[7:0] when MUXED = 0, is internally latched on the falling edge of ALE.
CS
Chip Select
I
I
Active-low input used to enable read/write operations on the MCI.
RD/DS
Read/Data Strobe
Bimodal input for controlling read/write access on the MCI.
When MOTEL = 1 and CS = 0, RD/DS behaves as an active-low data strobe
DS. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data
is internally latched from AD[7:0] on the rising edge of DS when R/W = 0.
When MOTEL = 0 and CS = 0, RD/DS behaves as an active-low read strobe
RD. Internal data is output on AD[7:0] when RD = 0. Write operations are not
controlled by RD in this mode.
WR / R/W
Write/
I
Bimodal input for controlling read/write access on the MCI.
Read/Write
When MOTEL = 1 and CS = 0, WR/R/W behaves as a read/write select line
R/W. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data
is internally latched from AD[7:0] on the rising edge of DS when R/W = 0.
When MOTEL = 0 and CS = 0, WR/R/W behaves as an active-low write strobe
WR. External data is internally latched from AD[7:0] on the rising edge of WR.
Read operations are not controlled by WR in this mode.
AD[7:0]
Address-Data[7:0]
I/O
An 8-bit, bidirectional multiplexed address-data bus. AD[7] = MSB, AD[0] =
LSB. Usage is controlled using MUXED.
ADDR[7:0]
MUXED
Address Bus (not
multiplexed)[7:0]
I
I
Provides a glueless interface to microcomputers with separate address and data
buses. ADDR[7] = MSB, ADDR[0] = LSB. Usage is controlled using MUXED.
Addressing Mode
Select
Controls the MCI addressing mode.
When MUXED = 1, the MCI uses AD[7:0] as a multiplexed signal for address
and data.
When MUXED = 0, the MCI uses ADDR[7:0] as the address input, and
AD[7:0] for data only.
READY
IRQ
Ready
OD
OD
Active-low, open-drain output that indicates the MCI is ready to transfer data.
Can be used to signal the microcomputer to insert wait states.
Interrupt Request
Active-low, open-drain output that indicates requests for interrupt. Asserted
whenever at least one unmasked interrupt flag is set. Remains inactive
whenever no unmasked interrupt flags are present.
N8973DSD
Conexant
Preliminary Information
1-7
1.0 System Overview
1.2 Pin Descriptions
RS8973
Single-Chip SDSL/HDSL Transceiver
Table 1-2. Hardware Signal Definitions (2 of 4)
Pin Label
RST
Signal Name
Reset
I/O
Definition
I
Asynchronous, active-low, level-sensitive input that places the transceiver in an
inactive state by setting the power-down mode bit of the Global Modes and
Status Register [global_modes; 0x00], and zeroing the clk_freq [7:0] bits of the
Clock Frequency Select Register [clock_freq;0x20], clk_freq[9,8] bits of the PLL
Modes Register [pll_modes; 0x22], and the hclk_freq[1,0] bits of the Serial
Monitor Source Select Register [serial_monitor_source; 0x01]. All RAM
contents are lost. Does not affect the state of the test access port, which is reset
automatically at power-up only.
Channel Unit Interface
RQ[1]/
RDAT
Receive Quat 1/
Receive Data
O
O
RQ[1]/RDAT and RQ[0]/BCLK are bimodal outputs that represent the sign and
magnitude bits of the received quaternary output symbol in parallel channel unit
modes (RQ[1], RQ[0]), and the serial-data and bit-clock outputs in serial
channel unit modes (RDAT, BCLK). Behavior of these outputs is configurable
through the Channel Unit Interface Modes Register [CU_interface_modes;
0x06] for parallel master, parallel slave, serial magnitude-bit-first, and serial
sign-bit-first operations.
RQ[0]/ BCLK Receive Quat 0/ Bit
Clock
For parallel mode operation:
RQ[1] = Sign bit output
RQ[0] = Magnitude bit output
Both outputs are updated at the symbol rate on the rising edge of QCLK
(master mode) or the rising/falling edge (programmable) of RBCLK (slave
mode).
For serial mode operation:
RDAT = Serial quaternary data output
BCLK = Bit-rate (two times symbol rate) clock output
RDAT is updated at the bit rate on the rising edge of BCLK
TQ[1]/ TDAT
TQ[0]
Transmit Quat 1/
Transmit Data
I
I
TQ[1]/TDAT and TQ[0] are bimodal inputs that represent the sign and magnitude
bits of the quaternary input symbol to be transmitted in parallel channel unit
modes (TQ[1], TQ[0]), and the serial data input in serial channel unit modes
(TDAT). Interpretation of these inputs is configurable through the Channel Unit
Interface Modes Register [CU_Interface_modes; 0x06] for parallel master,
parallel slave, serial magnitude-bit-first and serial sign-bit-first operations.
For parallel mode operation:
Transmit Quat 0
TQ[1] = Sign bit input
TQ[0] = Magnitude bit input
Both inputs are sampled at the symbol rate on the falling edge of QCLK
(master mode) or the rising/falling edge (programmable) of TBCLK (slave
mode).
For serial mode operation:
TDAT = Serial quaternary data input
TQ0 = Don’t care (tie or pull up to supply rail)
TDAT is sampled at the bit rate (two times the symbol rate) on the falling
edge of BCLK.
QCLK
Quaternary Clock
O
Runs at the symbol rate. It defines the data on the TQ and RQ interfaces. QCLK
is also used to frame transmit/receive quats in serial mode.
1-8
Conexant
Preliminary Information
N8973DSD
RS8973
1.0 System Overview
1.2 Pin Descriptions
Single-Chip SDSL/HDSL Transceiver
Table 1-2. Hardware Signal Definitions (3 of 4)
Pin Label
Signal Name
Transmit
I/O
Definition
TBCLK
I
Functions as the transmit baud-rate clock input. It must be frequency-locked to
QCLK. This input is used only when the channel unit interface is in parallel slave
mode. If it is unused, it should be tied to VDD2 or DGND.
Baud-Rate Clock
RBCLK
ReceiveBaud-Rate
Clock
I
Functions as the receive baud-rate clock input. It must be frequency-locked to
QCLK. This input is used only when the channel unit interface is in parallel slave
mode. If it is unused, it should be tied to VDD2 or DGND.
Analog Transmit Interface
TXP, TXN
Transmit Positive,
Negative
OA
Differential transmit line driver outputs. These signals are used to drive the
subscriber line after passing through the hybrid and line transformer.
Analog Receive Interface
RXP, RXN
Receive Positive,
Negative
IA
IA
Differential receiver inputs. RXP and RXN receive the signal from the subscriber
line.
RXBP, RXBN
Receive Balance
Positive, Negative
Differential receiver balance inputs. RXBP and RXBN are used to subtract the
echo of the signal being transmitted on the subscriber line. They should be
connected to the TXP, TXN output pins through the hybrid circuit. This signal is
subtracted from the signal being received by the RXP and RXN inputs in the
VGA.
Voltage Reference Generator Interface
RBIAS
Resistor Bias
OA
Connection point for external bias resistor.
VCOMO
Common Mode
Voltage Outputs
OA
OA
OA
Common mode voltage for the analog circuitry. This pin should be connected to
an external filtering capacitor.
VCOMI
VCCAP
Common Mode
Voltage Inputs
Common mode voltage for the analog circuitry. This pin should be connected to
an external filtering capacitor.
Voltage
Compensation
Capacitor
Analog voltage compensation capacitor. This pin should be connected to an
external filtering capacitor.
VRXP, VRXN
VTXP, VTXN
Receiver Voltage
Reference
Positive, Negative
OA
OA
Analog receive circuitry reference voltages. These pins should be connected to
external filtering capacitors.
Transmit Voltage
Reference
Analog transmit circuitry reference voltages. These pins should be connected to
external filtering capacitors.
Positive, Negative
Clock Interface
XTALI/
MCLK
Crystal In/Master
Clock
I
A bimodal input that can be used as the crystal input or as the master clock
input. The frequency of the crystal or clock should be 10.24 MHz.
XTALO
Crystal Output
O
O
Connection point for the crystal. If an external clock is connected to
XTALI/MCLK, XTALO should be left floating.
HCLK
High Speed Clock
Out
HCLK can be configured to run at 16, 32, or 64 times the symbol rate. Upon
reset, it is set to 16 times the symbol rate. This clock will be phase locked to the
incoming data when the RS8973 is configured as the remote unit.
XOUT
Crystal Clock Out
O
Buffered-crystal oscillator output.
N8973DSD
Conexant
Preliminary Information
1-9
1.0 System Overview
1.2 Pin Descriptions
RS8973
Single-Chip SDSL/HDSL Transceiver
Table 1-2. Hardware Signal Definitions (4 of 4)
Pin Label
Signal Name
I/O
Definition
Test and Diagnostic Interface
TDI
JTAG Test Data
Input
I
JTAG test data input per IEEE Std 1149.1-1990. Used for loading all serial
instructions and data into internal test logic. Sampled on the rising edge of TCK.
TDI can be left unconnected if it is not being used because it is pulled up
internally.
TMS
TDO
JTAG Test Mode
Select
I
JTAG test mode select input per IEEE Std 1149.1-1990. Internally pulled-up
input signal used to control the test-logic state machine. Sampled on the rising
edge of TCK. TMS can be left unconnected if it is not being used because it is
pulled up internally.
JTAG Test Data
Output
O
JTAG test data output per IEEE Std 1149.1-1990. Three-state output used for
reading all serial configuration and test data from internal test logic. Updated on
the falling edge of TCK.
TCK
JTAG Test Clock
Input
I
JTAG test clock input per IEEE Std 1149.1-1990. Used for all test interface and
internal test logic operations. If unused, TCK should be pulled low.
SMON
Serial Monitor
O
Serial data output used for real-time monitoring of internal signal-path registers.
The source register is selected through the Serial Monitor Source Select
Register [serial_monitor_source; 0x01]. The 16-bit words are shifted out, LSB
first, at 16 times the symbol rate. The rising edge of QCLK defines the start LSB
of each word. The output is updated on the rising edge of an internal clock
running at 16 times QCLK.
DTEST[1:4]
DTEST[5, 6]
ATEST[1,2]
Digital Tests 1–4
Digital Test 5, 6
Analog Test 1, 2
I
I
Active-high test inputs used by Conexant to enable internal test modes. These
inputs should be tied to digital ground (DGND).
Active-low test inputs used by Conexant to enable internal test modes. These
inputs should be tied to the I/O buffer power supply (VDD2).
IA
Analog test inputs used by Conexant for internal test modes. These inputs
should be left floating (No Connect, NC).
Power and Ground
VDD1
VDD2
VPLL
PGND
DGND
VAA
Core Logic Power
Supply
–
–
–
–
–
–
–
Dedicated supply pins powering the digital core logic functions.
Connect to 3.3 V.
I/O Buffer Power
Supply
Dedicated supply pins powering the digital I/O buffers. Connect to 5 V.
PLL Power Supply
Dedicated supply pins powering the PLL and the crystal amplifier.
Connect to 5 V.
PLL Ground
Dedicated ground pins for the PLL and the crystal amplifier. Must be held at the
same potential as DGND and AGND.
Digital Ground
Dedicated ground pins for the digital circuitry. Must be held at same potential as
AGND and PGND.
Analog Power
Supply
Dedicated supply pins powering the analog circuitry.
AGND
Analog Ground
Dedicated ground pins for the analog circuitry. Must be held at the same
potential as DGND and PGND.
1-10
Conexant
Preliminary Information
N8973DSD
RS8973
1.0 System Overview
Single-Chip SDSL/HDSL Transceiver
1.3 Regenerator Configuration
1.3 Regenerator Configuration
Figure 1-4 shows the interconnection between two RS8973s for a single loop
regenerator system. Bt8953A/RS8953B provides an internal cross-connect data
path between REG-R and REG-C.
Figure 1-4. Regenerator System Block Diagram
REG–R
RS8973
REG–C
RS8973
Bt8953A/
RS8953B
To COT
To RT
HCLK (35)
HCLK (35)
XTALO (39)
XTALI/MCLK (40)
XTALO (39)
NC
XTALI/MCLK (40)
10.24 MHz
HCLK on REG–R is configured to run at 16 times the symbol rate, which is
the power-on default.
The reg_clk_en bit of Miscellaneous/Test Register (0x0F) is reset (0) on
REG–R.
The reg_clk_en bit of Miscellaneous/Test Register (0x0F) is set (1) on
REG–C. In this mode, the internal clock synthesizer is bypassed.
N8973DSD
Conexant
Preliminary Information
1-11
1.0 System Overview
RS8973
1.3 Regenerator Configuration
Single-Chip SDSL/HDSL Transceiver
1-12
Conexant
Preliminary Information
N8973DSD
2
2.0 Functional Description
2.1 Transmit Section
The transmit section block diagram is shown in Figure 2-1. It comprises five
major functions: a symbol source selector/scrambler, a variable gain
digital-to-analog converter (DAC), a pulse-shaping filter, an analog CT
reconstruction filter, and a line driver.
Figure 2-1. Transmit Section Block Diagram
Transmit
Channel Unit
Interface
TQ[1,0]
Pulse-
Shaping
Filter
Analog CT
Reconstruction
Filter
Symbol
Source/
Scrambler
Variable-Gain
DAC
Line
Driver
TXP
TXN
Isolated Pulses
Detector Loopback
Ones (1s)
Control
Registers
N8973DSD
Conexant
Preliminary Information
2-1
2.0 Functional Description
2.1 Transmit Section
RS8973
Single-Chip SDSL/HDSL Transceiver
2.1.1 Symbol Source Selector/Scrambler
The input source selector/scrambler can be configured through the Transmitter
Modes Register [transmitter_modes; 0x0B] data_source [2:0] bits. It selects the
source of the data to be transmitted and determines whether the data is scrambled.
The symbol source selector/scrambler modes are described in Table 2-1.
Table 2-1. Symbol Source Selector/Scrambler Modes
data_source[2:0]
Symbol Source Selector/Scrambler Mode
000
Isolated pulse. Level selected by isolated_pulse[1,0]. The meter timer must be enabled and in
continuous mode. The pulse repetition interval is determined by the meter timer countdown interval.
001
Four-level scrambled detector loopback. Sign and magnitude bits from the receiver detector are
scrambled and looped back to the transmitter. Feedback polynomial determined by the htur_lfsr control
bit.
010
011
100
Four-level unscrambled data. Transmits the four-level (2B1Q) sign and magnitude bits from the transmit
channel unit transmit interface without scrambling.
Four-level scrambled 1s. Transmits a scrambled, constant high-logic level as a four-level (2B1Q) signal.
Feedback polynomial determined by the htur_lfsr control bit.
Alternating symbol mode. Outputs symbols of alternating polarity. Level is selected by
isolated_pulse [1:0]. The meter timer must be enabled and in continuous mode. The half period of the
output signal is defined by the meter timer countdown interval.
101
110
Four-level scrambled data. Scrambles and transmits the four-level (2B1Q) sign and magnitude bits from
the channel unit transmit interface. Feedback polynomial determined by the htur_lfsr control bit.
Two-level unscrambled data. Constantly forces the magnitude bit from the transmit channel unit
interface to a logic 0, and transmits the resulting two-level signal (as determined by the sign bit)
without scrambling. Valid output levels are limited to + 3 and – 3.
111
Two-level scrambled 1s. Transmits a scrambled, constant high-logic level as a two-level signal.
Feedback polynomial determined by the htur_lfsr control bit. Scrambler is run at the symbol rate
(half-bit rate) to produce the sign bit of the transmitted signal, while the magnitude bit is sourced with a
constant logic 0. Valid output levels are limited to + 3 and – 3.
The bit stream is converted into symbols for the four-level cases, as shown in
Table 2-2.
Table 2-2. Four-Level Bit-to-Symbol Conversions
First Input Bit
(Sign)
Second Input Bit
(Magnitude)
Output Symbol
0
0
1
1
0
1
1
0
– 3
– 1
+ 1
+ 3
2-2
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
2.1 Transmit Section
Single-Chip SDSL/HDSL Transceiver
In two-level mode, the magnitude bit is forced to a 0. This forces the symbols
to be + 3 and – 3, as shown in Table 2-3.
Table 2-3. Two-Level Bit-to-Symbol Conversions
First Input Bit
(Sign)
Second Input Bit
(Magnitude)
Output Symbol
0
1
Don’t Care
Don’t Care
– 3
+ 3
The scrambler is essentially a 23-bit-long Linear Feedback Shift Register
(LFSR). The feedback points are programmable for central office and remote
terminal applications using the htur_lfsr bit of the Transmitter Modes Register.
The LFSR polynomials for local (HTU-C/LTU) and remote (HTU-R/NTU) unit
operations are:
local x–23 x–5
1
remote x–23 x–18
1
The scrambler operates differently depending on whether a two-level or
four-level mode is specified. In two-level scrambled-1s mode, the LFSR is
clocked once per symbol; in four-level mode, the LFSR is clocked twice per
symbol.
The Transmitter Modes Register can also be used to zero the output of the
transmitter using the transmitter_off control bit.
The RS8973 can generate isolated pulses to support the testing of pulse
templates. When in the isolated pulse mode, the output consists of a single pulse
surrounded by 0s.
NOTE: Zero is not a valid 2B1Q level and occurs only in this special mode or
when the transmitter is off. The repetition rate of the pulses is controlled by
the meter timer. Any of the four 2B1Q levels can be chosen through the
Transmitter Modes Register’s isolated_pulse[1,0] control bits.
2.1.2 Variable Gain Digital-to-Analog Converter
A four-level DAC is integrated into the RS8973 to convert the output of the
symbol source to analog form. The normalized values of these four analog levels
are + 3, + 1, – 1 and – 3. Each represents a symbol, or quat.
To provide precise adjustment of transmitted power, the level of the DAC can
be adjusted. The Transmitter Gain Register [tx_gain; 0x29] sets the level.
During the manufacturing of the RS8973, process variations can cause
changes in transmitter levels. The Transmitter Calibration Register [tx_calibrate;
0x28] contains a read-only value which nulls this variation. The value in this
register is determined for each RS8973 device during production testing. Upon
initialization, the Transmitter Gain Register should be loaded based on the
Transmitter Calibration Register.
If there are other sources of transmit power variation (e.g., a nonstandard
hybrid or attenuative lightening protection), the transmitter gain must be adjusted
to include these effects. The range of adjustment of the transmitter gain is from
– 1.60 dB to 1.40 dB.
N8973DSD
Conexant
Preliminary Information
2-3
2.0 Functional Description
2.1 Transmit Section
RS8973
Single-Chip SDSL/HDSL Transceiver
2.1.3 Pulse-Shaping Filter
The pulse-shaping filter is used to filter the quats output from the variable-gain
DAC. This filter, when combined with other filtering in the signal path, produces
a transmitted signal on the line that meets the power spectral density, the
transmitted power, and the pulse-shaping requirements, as specified in
Chapter 5.0, Electrical and Mechanical Specifications.
2.1.4 Analog CT Reconstruction Filter
The analog CT reconstruction filter removes the discrete-time images from the
transmit signal before it is amplified by the line driver.
2.1.5 Line Driver
The line driver buffers the output of the CT reconstruction filter to drive diverse
loads. The output of the line driver is differential.
2-4
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
2.2 Receive Section
Single-Chip SDSL/HDSL Transceiver
2.2 Receive Section
Like the transmit section, the receive section consists of both analog and digital
circuitry. The VGA provides the interface to the analog signals received from the
line and the hybrid. The ADC then digitizes the analog signal so it can be further
processed in the DSP section of the receiver. The receiver DSP section includes
front-end processing, echo cancellation, equalization, and symbol detection.
2.2.1 Variable Gain Amplifier
The VGA has two purposes. The first is to provide a dual-differential analog input
so the pseudo-transmit signal created by the hybrid can be subtracted from the
signal received from the line transformer. This subtraction provides first-order
echo cancellation, which results in a first-order approximation of the signal
received from the line. Figure 2-2 illustrates the recommended echo-cancellation
circuit interconnections. All off-chip circuitry, including the hybrid and anti-alias
filters, consists entirely of passive components. Further echo cancellation occurs
in the receiver DSP.
Figure 2-2. First-Order Echo Cancellation Using the Variable Gain Amplifier
RXP
RXN
+
–
+
–
Line
Transformer
Anti-alias
Filter
To
ADC
Line
(Twisted Pair)
TXP
TXN
+
–
Line
Driver
+
–
Line
RXBP
RXBN
Impedance
Matching
Resistors
+
–
+
–
Anti-alias
Filter
Gain[2:0]
Hybrid
Off-Chip Circuitry
On-Chip Circuitry
The second purpose of the VGA is to provide programmable gain of the
received signal prior to passing it to the ADC. This reduces the resolution
required for the ADC. There are six gain settings ranging from 0 dB to 15 dB (this
is the gain setting range in relative terms; the physical settings range from – 3 dB
to 12 dB). The gain is controlled through the gain[2:0] control bits in the ADC
Control Register [adc_control; 0x21]. See Chapter 3.0, Registers, for a more
detailed description of the gain[2:0] control bits.
2.2.2 Analog-to-Digital Converter
The ADC provides 16 bits of resolution. The analog input from the variable gain
amplifier is converted into digital data and output at the symbol rate.
N8973DSD
Conexant
Preliminary Information
2-5
2.0 Functional Description
2.2 Receive Section
RS8973
Single-Chip SDSL/HDSL Transceiver
2.2.3 Digital Signal Processor
The DSP includes five Least Mean Squared (LMS) filters:
•
•
•
•
•
Echo Canceller (EC)
Digital Automatic Gain Controller (DAGC)
Feed Forward Equalizer (FFE)
Error Predictor (EP)
Decision Feedback Equalizer (DFE).
These filters are used to equalize the received signal so that the symbols
transmitted from the far-end can be reliably recovered. The DSP uses symbol rate
sampling for all processing functions. Figure 2-3 shows the interconnections and
relationships to the digital front-end and the detector.
Figure 2-3. Receiver Digital Signal Processing
Detector
–
SLM
FELM
PKD
Channel
Unit
Digital
Front-End
IS
FILTER
Interface
DAGC
FFE
Slicer
–
–
–
–
–
NEC
EP
Transmit
Symbol
LEC
DFE
Echo Canceller
Equalizer
2-6
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
2.2 Receive Section
Single-Chip SDSL/HDSL Transceiver
2.2.3.1 Digital
Front-End
Prior to the main signal processing, the input signal must be adjusted for any DC
offset. The front-end module also monitors the input signal level, which includes
measuring DC and AC input signal levels, detecting and counting overflows, and
detecting alarms based on the far-end signal level. Figure 2-4 summarizes the
features of the digital front-end module.
Figure 2-4. Digital Front-End Block Diagram
High Threshold
from MCI
Echo-Free
Absolute
Signal
from NEC
high_felm
Interrupt
Comparator
Comparator
Value
low_felm
Interrupt
Accumulator
Low Threshold
from MCI
Far-End
Alarms
Result
Register
Far-End
Level Meter
+
r, To EC
ADC Data
–
Absolute
Value
Accumulator
DC Offset
from MCI
Result
Accumulator
Register
Result
Register
DC Level
Meter
Signal Level
Meter
Overflow
Counter
Overflow
Detector
Result
Register
Overflow Monitor
N8973DSD
Conexant
Preliminary Information
2-7
2.0 Functional Description
2.2 Receive Section
RS8973
Single-Chip SDSL/HDSL Transceiver
2.2.3.2 Offset
Adjustment
A nonzero DC level on the input can be corrected by a DC offset value
[dc_offset_low, dc_offset_high; 0x26, 0x27], which is subtracted from the input.
The DC offset is a 16-bit number and is programmed through the microcomputer
interface.
2.2.3.3 DC Level Meter
The DC level meter provides the monitoring needed for adaptive offset
compensation. The offset-adjusted input signal is accumulated over the meter
timer interval [meter_low, meter_high; 0x18, 0x19]. The 16 MSBs are placed into
the DC Level Meter Registers [dc_meter_low, dc_meter_high; 0x44, 0x45].
2.2.3.4 Signal Level
Meter
The Signal Level Meter provides the monitoring needed for adjusting the analog
gain circuit located before the ADC. The absolute value of the offset adjusted
input signal is accumulated over the meter timer interval [meter_low, meter_high;
0x18, 0x19]. The 16 MSBs are placed in the Signal Level Meter Registers
[slm_low, slm_high; 1; 0x46, 0x47].
2.2.3.5 Overflow
Detection
and Monitoring
The overflow sensor detects ADC overflows. The overflow monitor counts the
number of overflows, as indicated by the overflow sensor during the meter timer
interval [meter_low, meter_high; 0x18, 0x19]. The counter is limited to 8 bits. In
the case of 256 or more overflows during the measurement interval, the counter
will hold at 255. The counter is loaded into the Overflow Meter Register
[overflow_meter; 0x42] at the end of each measurement interval.
2.2.3.6 Far-End Level
Meter
The Far-end Level Meter monitors the output of the echo canceller, which is
called the far-end signal because the echo of the transmitted signal is subtracted
from it. This value is accumulated over the meter timer interval [meter_low,
meter_high; 0x18, 0x19]. The 16 MSBs are placed into the Far-End Level Meter
Register [felm_low, felm_high; 0x48, 0x49].
2.2.3.7 Far-End Level
Alarm
The result of the far-end level meter is compared to two thresholds. When these
are exceeded, an interrupt is sent to the microcomputer interface if the
corresponding FELM interrupt is enabled. The thresholds are determined by the
value in the Far-End High Alarm Threshold Registers
[far_end_high_alarm_th_low, far_end_high_alarm_th_high; 0x30, 0x31] and the
Far-End Low Alarm Threshold Registers [far_end_low_alarm_th_low,
far_end_low_alarm_th_high; 0x32, 0x33].
The interrupts high_felm and low_felm are bits 2 and 1, respectively, of the
IRQ Source Register [irq_source; 0x05]. The interrupts high_felm and low_felm
can be masked by writing a 1 to bits 2 and 1, respectively, of the Interrupt Mask
Register High [mask_high_reg; 0x03].
2.2.4 Impulse Shortening Filter
The impulse shortening (IS) filter is a high pass filter which pre-equalizes the
channel and eliminates long tails caused by the transformer.
2-8
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
2.2 Receive Section
Single-Chip SDSL/HDSL Transceiver
2.2.5 Echo Canceller
The echo canceller (EC) removes images of the transmitted symbols from the
received signal and consists of two blocks: a linear and nonlinear echo canceller.
The organization of the blocks is displayed in Figure 2-3, Receiver Digital Signal
Processing.
2.2.5.1 Linear Echo
Canceller
The linear echo canceller (LEC) is a conventional LMS, finite impulse response
(FIR) filter, which removes linear images of the transmitted symbols from the
received signal. It consists of a 120-tap FIR filter with 32-bit adapted
coefficients.
When LEC is enabled, the last data tap of the echo canceller is treated
specially; the data value is set to a constant 1. This serves to cancel any DC offset
that may be present.
These modes, used less often, can also be enabled through the MCI:
•
•
•
A freeze coefficient mode disables the coefficient updates.
A special mode zeros all of the coefficients.
An additional mode zeros the output of the FIR with no effect on the
coefficients.
•
Individual EC coefficients can be read and written through the MCI.
2.2.5.2 Nonlinear Echo
Canceller (NEC)
The nonlinear echo canceller (NEC) reduces the residual echo power in the echo
canceller output caused by nonlinear effects in the transmitter, receiver, analog
hybrid circuitry, or line cables.
The delay of the transmit-symbol input to the NEC can be specified through
the MCI, Nonlinear Echo Canceller Mode Register [nonlinear_ec_modes; 0x09].
This allows the NEC to operate on the peak of the echo regardless of differing
delays in the echo path.
These modes, used less often, can also be enabled through the MCI:
•
•
•
A freeze coefficient mode disables the coefficient updates.
A special mode zeros all of the coefficients.
An additional mode zeros the output of the look-up table with no effect on
the coefficients.
•
The 64 14-bit, individual NEC coefficients can be read and written
through the MCI.
2.2.6 Equalizer
Four LMS filters are used in the equalizer to process the echo canceller output so
that received symbols can be reliably recovered. The filters are a digital automatic
gain controller, a feed forward equalizer, an error predictor, and a decision
feedback equalizer. Their interconnections are shown in Figure 2-3, Receiver
Digital Signal Processing.
2.2.6.1 Digital
Automatic Gain Control
The digital automatic gain control (DAGC) scales the echo-free signal to the
optimum magnitude for subsequent processing.
Two other modes, used less often, can also be enabled through the MCI:
•
•
A freeze coefficient mode disables the coefficient update.
The DAGC gain coefficient can be read or written through the MCI.
N8973DSD
Conexant
Preliminary Information
2-9
2.0 Functional Description
2.2 Receive Section
RS8973
Single-Chip SDSL/HDSL Transceiver
2.2.6.2 Feed Forward
Equalizer
The feed forward equalizer (FFE) removes precursors from the received signal.
The FFE can be operated in a special adapt last mode. In this mode, which is
useful during startup, only the last coefficient is updated. The last coefficient is
multiplied with the oldest data sample (sample #7).
Other modes, used less often, can be enabled through the MCI:
•
•
•
A freeze coefficient mode disables the coefficient updates.
A special mode zeros all of the coefficients.
Individual FFE coefficients can be read and written through the MCI.
2.2.6.3 Error Predictor
The error predictor (EP) improves the performance of the equalizer by
prognosticating errors before they occur.
Other modes, used less often, can be enabled through the MCI:
•
•
•
A freeze coefficient mode disables the coefficient updates.
A special mode zeros all of the coefficients.
Individual EP coefficients can be read and written through the MCI.
2.2.6.4 Decision
Feedback Equalizer
The decision feedback equalizer (DFE) removes postcursors from the received
signal.
Other modes, used less often, can be enabled through the MCI:
•
•
•
A freeze coefficient mode disables the coefficient updates.
A zero coefficients mode zeros all of the coefficients.
A zero filter output mode zeros the output of the FIR with no effect on the
coefficients.
•
Individual DFE coefficients can be read and written through the MCI.
2.2.6.5 Microcoding
The DAGC, FFE, and EP filters are implemented using an internal
microprogrammable DSP, optimized for LMS filters. Internal DSP
micro-instructions are stored in an on-chip RAM. This microcode RAM is loaded
after power-up through the MCI when the transceiver is initialized.
2.2.7 Detector
The detector converts the equalized received signal into a 2B1Q symbol and
produces two error signals used in adapting the receiver equalizers. The signal
detection uses two sub-blocks, a slicer, and a peak detector. Additionally, the
detector contains a scrambler and bit error rate (BER) meter for use during the
start-up sequence.
2.2.7.1 Slicer
The slicer thresholds the equalized signal to produce a 2B1Q symbol. The input
to the slicer is the FFE output minus the DFE and EP outputs.
The slicer can operate in two modes: two-level and four-level. In the two-level
mode, which is used during start-up when the only transmitted symbols are + 3 or
– 3, the slicer threshold is set at zero.
In the four-level mode, the cursor level is specified through the MCI. It is a
16-bit, 2s complement number, but must be positive and less than 0x2AAA for
proper operation.
2.2.7.2 Peak Detector
The peak detector (PKD) is used only during the two-level transmission part of
start-up. It operates on the echo-free signal. A signal is detected to be a + 3 if it is
higher than both of its neighbors, or a – 3 if it is lower than both of its neighbors.
If neither of the peaked conditions exist, the output of the slicer is used.
2.2.7.3 Error Signals
The detector computes two error signals for use in the equalizer: a 16-bit slicer
and a 16-bit equalizer.
2-10
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
2.2 Receive Section
Single-Chip SDSL/HDSL Transceiver
2.2.7.4 Scrambler
Module
The scrambler can operate as either a scrambler or as a descrambler. The
scrambler block is used during the scrambled-1s part of the start-up sequence.
This provides an error-free signal for equalizer adaptation. This scrambler is
essentially a 23-bit-long Linear Feedback Shift Register (LFSR). The feedback
point depends on whether the transceiver is being used in a central-office or
remote-terminal application.
When the LFSR is operating as a descrambler, the input source is the detector
output. The symbol is converted to a bit stream as shown in Table 2-4 for the
two-level case.
Table 2-4. Two-Level Symbol-to-Bit Conversion
Input Symbol
Output Bit
– 3
+ 3
0
1
The symbol is converted to a bit stream as shown in Table 2-5 for the
four-level case.
Table 2-5. Four-Level Symbol-to-Bit Conversion
First Output Bit
(Sign)
Second Output Bit
(Magnitude)
Input Symbol
– 3
– 1
+ 1
+ 3
0
0
1
1
0
1
1
0
The LFSR operates in the same way in both cases, except that in the two-level
case it is clocked once per symbol, and in the four-level case it is clocked twice
per symbol.
When operating as a scrambler, the LFSR must first be locked to the far-end
source. Once locked, it is then able to replicate the far-end input sequence when
its input is held at all 1s. The locking sequence is controlled internally, initiated
through the MCI by setting the lfsr_lock bit of the detector_modes register. The
locking sequence consists of the following four steps:
1. Operate the LFSR as a descrambler for 23 bits.
2. Operate the LFSR as a scrambler for 127 bits. The sync detector is active
during this period.
3. Go to Step 1 if synchronization was not achieved; otherwise, continue to
Step 4.
4. Send an interrupt to the microcomputer if unmasked, indicating successful
locking, and continue operating as a scrambler.
The sequence continues until the lfsr_lock control bit is cleared by the
microcomputer.
N8973DSD
Conexant
Preliminary Information
2-11
2.0 Functional Description
2.2 Receive Section
RS8973
Single-Chip SDSL/HDSL Transceiver
2.2.7.5 Sync Detector
The sync detector compares the output of the scrambler with the output of the
symbol detector. The number of equivalent bits is accumulated for 128
comparisons. The result is then compared to a Scrambler Synchronization
Threshold Register [scr_sync_th; 0x2E], a lock is declared, and the sync bit of the
irq_source register is set if the count is greater than the threshold. For a count less
than or equal to the threshold, no lock condition is declared and the sync bit is
unaffected.
2.2.7.6 Detector Meters
BER Meter
The detector consists of five meters: a BER meter, a symbol histogrammer, a
noise-level meter, a noise-level histogram meter, and an SNR alarm meter.
The BER meter provides an estimate of the bit error rate when the received
symbols are known to be scrambled 1s. When the LFSR is operating as a
descrambler, the meter counts the number of 1s on the descrambler output. When
the LFSR is operating as a scrambler, the BER meter counts the number of equal
scrambler and symbol detector outputs. The counter operates over the meter timer
interval [meter_low, meter_high; 0x18, 0x19]. The counter is saturated to 16 bits.
At the end of the measurement interval the counter is loaded into the Bit Error
Rate Meter Registers [ber_meter_low, ber_meter_high; 0x4C, 0x4D].
Symbol Histogrammer
The symbol histogrammer computes a coarse histogram of the received symbols.
It operates by counting the number of 1s received during the meter timer interval
[meter_low, meter_high; 0x18, 0x19]. That is, at the start of the measurement
interval a counter is cleared. For each detector output which is + 1 or – 1, the
counter is incremented. If the detector output is + 3 or – 3, the count is held at its
previous value. The count is saturated to 16 bits. At the end of the measurement
interval, the 8 MSBs of the counter are loaded into the Symbol Histogram Meter
Register [symbol_histogram; 0x4E]. This can be used during start-up to detect the
transition from two-level to four-level signalling.
Noise Level Meter
The noise level meter estimates the noise at the input to the slicer. It operates by
accumulating the absolute value of the slicer error over meter timer interval
[meter_low, meter_high; 0x18, 0x19]. At the end of the measurement interval, the
16 MSBs of the 32-bit accumulator are loaded into the Noise Level Meter
Register [nlm_low, nlm_high; 0x50, 0x51].
Noise Level Histogram Meter
The noise level histogram meter counts the number of high noise-level conditions
which occur during each meter countdown interval. A high noise-level condition
is defined as the absolute value of the slicer error signal exceeding the threshold
specified in the noise level histogram threshold register [0x2A,2B].
SNR Alarm
The SNR alarm provides a rapid indication of impulse noise disturbances and loss
of signal so that corrective action can be taken. The alarm is based on a second
noise level meter. The meter is the same as the preceding noise level meter except
it operates on a dedicated timer, the SNR alarm timer. The absolute value of the
slicer error is accumulated during the timer period. At the end of the
measurement interval, the 16 MSBs of the accumulator are compared against the
SNR Alarm Threshold Register [snr_alarm_th_low, snr_alarm_th_high; 0x34,
0x35]. If the result is greater than this threshold, an interrupt is set in the
irq_source register. The threshold is set through the MCI.
2-12
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
Single-Chip SDSL/HDSL Transceiver
2.3 Timing Recovery and Clock Interface
2.3 Timing Recovery and Clock Interface
The timing recovery and clock interface block consists of the timing recovery
circuit, the crystal amplifier, and the clock synthesizer, as detailed in Figure 2-5.
The main purpose of this circuitry is to generate the internal clocks, including
BCLK and QCLK, from the 10.24 MHz input MCLK, based on the selected data
rate, and to recover the clock from received data. Control fields include the
following:
•
•
•
Clock Frequency Select Register [clk_select; 0x20]
PLL Modes Register [clk_select; 0x22]
hclk_freq[1,0] bits of the Serial Monitor Source Select Register
[serial_monitor_source; 0x01]
•
•
PLL Modes Register [pll_modes; 0x22]
Timing Recovery PLL Phase Offset Register [pll_phase_offsset_low,
pll_phase_offset_high; 0x24, 0x25]
•
PLL Frequency Register [pll_frequency_low, pll_frequency_high; 0x5E,
0x5F].
See Chapter 3.0, Registers, for descriptions of these control fields.
N8973DSD
Conexant
Preliminary Information
2-13
2.0 Functional Description
RS8973
2.3 Timing Recovery and Clock Interface
Single-Chip SDSL/HDSL Transceiver
Figure 2-5. Timing Recovery and Clock Interface Block Diagram
Phase Detector
Meter Register
[0x40, 0x41]
Control
Registers
Detected
Symbol
QCLK (87)
HCLK (35)
Timing
Recovery
Circuit
Equalizer
Error
Clock
Synthesizer
XOUT (36)
Crystal
Amplifier
XTALI (40)
XTALO (39)
C11
Y1
C10
Y1 = 10.24 MHz
(For all data rates)
2-14
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
Single-Chip SDSL/HDSL Transceiver
2.3 Timing Recovery and Clock Interface
2.3.1 Timing Recovery Circuit
The timing recovery circuit uses the RS8973’s internal detected symbol and
equalizer error signals to regenerate the received data symbol clock (QCLK). The
HCLK output is synchronized with the edges of the symbol clock (QCLK), unlike
the XOUT output, which is a buffered output of the crystal amplifier. HCLK can
be programmed for rates of 16, 32, or 64 times the symbol rate.
The timing recovery circuit includes a phase detector meter that measures the
average value of a phase correction signal. This information can be used during
start-up to set the phase offset in the Receive Phase Select Register
[receive_phase_select; 0x07]. The output of the phase detector is accumulated
over the meter timer interval [meter_low, meter_high; 0x18, 0x19]. At the end of
the measurement interval, the value is loaded into the Phase Detector Meter
Register [pdm_low, pdm_high; 0x40, 0x41].
The user can also bypass the timing recovery circuit and directly specify the
frequency through the PLL Frequency Register [pll_frequency_low,
pll_frequency_high; 0x5E, 0x5F].
2.3.2 Crystal Amplifier
The crystal amplifier reduces the support circuitry needed for the RS8973 by
eliminating the need for an external crystal oscillator (XO). A crystal of
10.24 MHz frequency can be connected directly to the XTALI and XTALO pins.
The crystal amplifier can also accommodate an external clock input by
connecting the external clock to the XTALI input pin.
2.3.3 Clock Synthesizer
The clock synthesizer takes the 10.24 MHz input clock as a reference and
generates internal clocks required for data rates ranging from 144 kbps to
2320 kbps. The appropriate internal clock frequency can be selected by
specifying the data rate in the Clock Frequency Select Register [clk_select [7:0];
0x20] and PLL Modes Register [clk_select [9,8]; 0x22].
N8973DSD
Conexant
Preliminary Information
2-15
2.0 Functional Description
2.4 Channel Unit Interface
RS8973
Single-Chip SDSL/HDSL Transceiver
2.4 Channel Unit Interface
The quaternary signals of the channel unit interface have four modes which are
programmable through bits 0 and 1 of the Channel Unit Interface Modes Register
[cu_interface_modes; 0x06]. They are serial sign-bit first, serial magnitude-bit
first, parallel master, and parallel slave.
In serial mode, a Bit-Rate Clock (BCLK) is output at twice the symbol rate.
The sign and magnitude bits of the receive data are output through RDAT on the
rising edge of BCLK. The sign and magnitude bits of the transmit data are
sampled on the falling edge of BCLK at the TDAT input. The sign bit is
transferred first, followed by the magnitude bit of a given symbol in sign-bit first
mode, while the opposite occurs in magnitude-bit first mode. The clock
relationships for serial sign-bit first mode are illustrated in Figure 2-6.
Figure 2-6. Serial Sign-Bit First Mode
BCLK
Bit-Rate Clock
QCLK
Sign0
Sign0
Magnitude0
Magnitude0
Sign1
Sign1
Magnitude1
Magnitude1
Sign2
Sign2
RDAT
TDAT
In parallel master mode, the sign and magnitude receive data is output through
RQ[1] and RQ[0], respectively, on the rising edge of QCLK. The quaternary
transmit data is sampled on the falling edge of QCLK. This clock and data
relationship is illustrated in Figure 2-7.
Figure 2-7. Parallel Master Mode
QCLK
Sign1
Sign0
Sign2
RQ[1]/TQ[1]
RQ[0]/TQ[0]
Magnitude0
Magnitude1
Magnitude2
2-16
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
2.4 Channel Unit Interface
Single-Chip SDSL/HDSL Transceiver
The parallel slave mode uses RBCLK and TBCLK inputs to synchronize data
transfer. RBCLK and TBCLK must be frequency-locked to QCLK, though the
use of two internal FIFOs allows an arbitrary phase relationship to QCLK. TQ[1]
and TQ[0] are sampled on the active edge of TBCLK, as programmed through the
MCI. RQ[1] and RQ[0] are output on the active edge of RBCLK, also as
programmed through the MCI. Figure 2-8 shows the clock relationships, when
TBCLK is programmed to be falling-edge active and RBCLK is rising-edge
active.
Figure 2-8. Parallel Slave Mode
TBCLK
Sign1
Sign0
Sign2
TQ[1]
TQ[0]
Magnitude0
Magnitude1
Magnitude2
RBCLK
RQ[1]
RQ[0]
Sign1
Sign0
Sign2
Magnitude0
Magnitude1
Magnitude2
N8973DSD
Conexant
Preliminary Information
2-17
2.0 Functional Description
2.5 Microcomputer Interface
RS8973
Single-Chip SDSL/HDSL Transceiver
2.5 Microcomputer Interface
The microcomputer interface provides operational mode control and status
through internal registers. A microcomputer write sets the operating modes to the
appropriate registers. A read to a register verifies the operating mode or provides
the status. The MCI can be programmed to generate an interrupt on certain
conditions.
2.5.1 Source Code
Conexant provides portable C-source code under a no-cost licensing agreement.
This source code provides a start-up procedure, as well as diagnostic and system
monitoring functions.
2.5.2 Microcomputer Read/Write
The MCI uses either an 8-bit-wide multiplexed address-data bus, or an 8-bit-wide
data bus and a separate 8-bit-wide address bus for external data communications.
The interface provides access to the internal control and status registers,
coefficients, and microcode RAM. The interface is compatible with Intel or
Motorola microcomputers, and is configured with the inputs, MOTEL and
MUXED.
•
•
MOTEL high selects Motorola-type microcomputer and uses control
signals ALE, CS, DS, and R/W. MOTEL low selects Intel-type
microcomputer and uses control signals ALE, CS, RD, and WR.
MUXED high configures the interface to use the multiplexed address-data
bus with both the address and data on the AD[7:0] pins. MUXED low
configures the interface to use separate address and data bus with the data
on the AD[7:0] pins and the address on the ADDR[7:0] pins.
•
The READY pin is provided to indicate when the RS8973 is ready to
transfer data and can be used by the microcomputer to insert wait states in
read or write cycles.
The MCI provides access to a 256-byte internal address space. The registers in
this address space provide configuration, control, status, and monitoring
capabilities.
Meter values are read lower-byte, then upper-byte. When the lower-byte is
read, the upper-byte is latched at the corresponding value. This ensures that
multiple byte values correspond to the same reading.
Most information can be directly read or written; however, the filter
coefficients require an indirect access.
2-18
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
2.5 Microcomputer Interface
Single-Chip SDSL/HDSL Transceiver
2.5.2.1 RAM Access
Registers
The internal RAM of the scratch pad, LEC, NEC, DFE, equalizer, and microcode
are accessed indirectly. They all share a common data register which is used for
both read and write operations: Access Data Register [access_data_byte[3:0];
[0x7C–0x7F]. Each RAM has an individual read select and write select register.
Writes to these registers specify the location to access and trigger the actual RAM
read or write.
To perform a read, the address of the desired RAM location is first written to
the corresponding read tap select register. Two symbol periods afterward, the
individual bytes of that location are available for reading from the Access Data
Register.
To perform a write, the value to be written is first stored in the Access Data
Register. The address of the affected RAM location is then written to the
corresponding write tap select register. When writing the same value to multiple
locations, it is not necessary to rewrite the Access Data Register.
To ensure reliable access to the embedded RAM, internal read and write
operations are performed synchronous to the symbol clock. This limits access to
the internal RAM to one every other cycle.
When reading or writing multiple filter coefficients, it may be desirable to
freeze adaptation so that all values correspond to the same state.
2.5.2.2 Multiplexed
Address/Data Bus
The timing for a read or write cycle is stated explicitly in Chapter 5.0, Electrical
and Mechanical Specifications. During a read operation, an external
microcomputer places an address on the address-data bus, which is then latched
on the falling edge of ALE. Data are placed on the address-data bus after CS and
RD, or CS and DS go low. The read cycle is completed with the rising edge of CS
or RD or DS.
A write operation latches the address from the address-data bus at the falling
edge of ALE. The microcomputer places data on the address-data bus after CS,
and WR or CS and DS go low. Motorola MCI has R/W falling edge preceding the
falling edge of CS and DS. The rising edge of R/W occurs after the rising edge of
CS and DS. Data are latched from the address-data bus on the rising edge of CS
or WR or DS.
2.5.2.3 Separated
Address/
The timing for a read or write cycle using the separated address and data buses is
essentially the same as over the multiplexed bus. The one exception is that the
address must be driven onto the ADDR[7:0] bus rather than the AD[7:0] bus.
Data Bus
2.5.3 Interrupt Request
The 12 interrupt sources consist of 8 timers, a far-end signal high alarm, a far-end
signal low alarm, a SNR alarm, and a scrambler synchronization detector. All of
the interrupts are requested on a common pin, IRQ. Each interrupt can be
individually enabled or disabled through the Interrupt Mask Registers
[mask_low_reg, mask_high_reg; 0x02, 0x03]. The cause of an interrupt is
determined by reading the Timer Source Register [timer_source; 0x04] and the
IRQ Source Register [irq_source; 0x05].
The timer interrupt status is set only when the timer transitions to zero. Alarm
interrupts cannot be cleared while the alarm is active. In other words, it cannot be
cleared while the condition still exists.
IRQ is an open-drain output and must be tied to a pull-up resistor. This allows
IRQ to be tied to a common interrupt request.
N8973DSD
Conexant
Preliminary Information
2-19
2.0 Functional Description
2.5 Microcomputer Interface
RS8973
Single-Chip SDSL/HDSL Transceiver
2.5.4 Reset
The reset input (RST) is an active-low input that places the transceiver in an
inactive state by setting the mode bit (0) in the Global Modes and Status Register
[global_modes; 0x00]. An internal supply monitor circuit ensures that the
transceiver is in an inactive state upon initial application of power to the chip.
2.5.5 Registers
2.5.6 Timers
The RS8973 has many directly addressable registers that include control and
monitoring functions. Write operations to undefined registers have unpredictable
effects. Read operations from undefined registers have undefined results.
Eight timers are integrated into the RS8973 to control the various on-chip meters
and to aid the microcomputer in stepping through the events of the start-up
sequence.
The structure of each timer includes down counter, zero detect logic, and
control circuitry, which determines when the counter is reloaded or decremented.
For each of the 8 timers, there is a 2-byte timer interval register that
determines the value from which the timer decrements. There are three 8-bit
registers:
•
•
•
Timer Restart Register [timer_restart; 0x0C]
Timer Enable Register [timer_enable; 0x0D]
Timer Continuous Mode Register [timer_continuous; 0x0E].
These registers control the operation of the timers. Each bit of the 8-bit
registers corresponds to a timer. Each logic-high bit in timer_restart acts as an
event that causes the corresponding timer to reload. Each logic-high bit in
timer_enable acts to enable the corresponding timer. Each logic-high bit in
timer_continuous acts to reload the counter after timing out.
Each counter is loaded with the value in its interval register. The counter
decrements until it reaches zero. Upon reaching zero, an interrupt is generated if
enabled by the Interrupt Mask Low Register [mask_low_reg, mask_high_reg;
0x02, 0x03]. The interrupt is edge-triggered so that only one interrupt is caused
by a single time-out.
A prescaler can precede the timer. This increases the time span available at the
expense of resolution. Only the start-up timers have prescalers. Table 2-6 provides
summary information on the timers.
2-20
Conexant
Preliminary Information
N8973DSD
RS8973
2.0 Functional Description
2.5 Microcomputer Interface
Single-Chip SDSL/HDSL Transceiver
Table 2-6. Timers
Timer Name
Purpose
Clock Rate
Control Bits
Startup Timer 1
Startup Timer 2
Startup Events
Startup Events
Startup Events
Startup Events
SNR Measurement
Measurement
Symbol rate ÷ 1024
Symbol rate ÷ 1024
Symbol rate ÷ 1024
Symbol rate ÷ 1024
Symbol rate
sut 1
sut 2
sut 3
sut 4
snr
Startup Timer 3
Startup Timer 4
SNR Alarm Timer
Meter Timer
Symbol rate
meter
t3
General Purpose Timer 3
General Purpose Timer 4
Miscellaneous
Miscellaneous
Symbol rate
Symbol rate
t4
Four timers are provided for use in timing start-up events. These timers share a
single prescaler, which divides the symbol clock by 1024 and supplies this slow
clock to the four counters. The timers are Startup Timer 1, Startup Timer 2,
Startup Timer 3, and Startup Timer 4. Each one is independent, with separate
interval timer values and interrupts.
Two timers control the measurement intervals for the various meters: the SNR
Alarm Timer and the Meter Timer. The SNR Alarm Timer is used only by the low
SNR, while the Meter Timer is used by all other meters, excluding the low SNR
meter. Their respective interrupts are set when each of these two timers expires.
There are no prescalers for these timers; they count at the symbol rate. Both
timers are normally used in the continuous mode.
Two identical timers are provided for general use: General Purpose Timer 3
and General Purpose Timer 4. There are no prescalers for these timers; they count
at the symbol rate. Each timer signals an interrupt when it expires.
2.5.7 Scratch Pad Memory
The scratch pad memory consists of 64 bytes of RAM available to the external
microcomputer. This is used by Conexant-supplied software to minimize system
memory requirements.
N8973DSD
Conexant
Preliminary Information
2-21
2.0 Functional Description
RS8973
2.6 Test and Diagnostic Interface (JTAG)
Single-Chip SDSL/HDSL Transceiver
2.6 Test and Diagnostic Interface (JTAG)
To access individual chips for PCB verification, special circuitry is incorporated
within the transceiver, which complies with IEEE Std 1149.1-1990, Standard Test
Access Port and Boundary Scan Architecture set by the Joint Test Action Group
(JTAG).
JTAG has four dedicated pins that comprise the test access port (TAP):
1. Test Mode Select (TMS)
2. Test Clock (TCK)
3. Test Data Input (TDI)
4. Test Data Out (TDO)
Verification of the integrated circuit’s connection to other modules on the
printed circuit board can be achieved through these four TAP pins.
JTAG’s approach to testability uses boundary scan cells placed at each digital
pin, both inputs and outputs. All scan cells are interconnected in a boundary-scan
register which applies or captures test data used for functional verification of the
PC board interconnection. JTAG is particularly useful for board testers using
functional testing methods.
The boundary-scan cells at each digital pin provide the ability to apply and
capture the respective logic levels. Since all of the digital pins are interconnected
as a long shift register, the TAP logic has access and control of all necessary pins
to verify connectivity. For mixed signal ICs, the chip boundary definition is
expanded to include the on-chip interface between digital and analog circuitry.
During a power-up sequence, internal supply-monitor circuitry ensures that each
pin is initialized to operate as a 2B1Q transceiver, instead of JTAG test mode.
The JTAG standard defines an optional device identification register. This
register is included and contains a revision number, a part number, and a
manufacturer’s identification code specific to Conexant (see Table 2-7). Access to
this register is through the TAP controller through a standard JTAG instruction.
A variety of verification procedures can be performed through the TAP
controller. Board connectivity can be verified at all digital pins through a set of
two instructions accessible through the use of a state machine, standard to all
JTAG controllers. Refer to the IEEE Std 1149.1 specification for details
concerning the Instruction Register and JTAG state machine. A Boundary Scan
Description Language (BSDL) file for the RS8973 is also available from the
factory upon request.
Table 2-7. JTAG Device Identification Register
Version(1)
Part Number
Manufacturer ID
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
0
1
1
0
1
0x0
0x230D (RS8973)
16 bits
0x0D6
11 bits
TDO
4 bits
NOTE(S):
(1) Consult factory for current version number.
2-22
Conexant
Preliminary Information
N8973DSD
3
3.0 Registers
3.1 Conventions
Unless otherwise noted, the following conventions apply to all applicable register
descriptions:
•
•
•
•
For storage of multiple-bit data fields within a single byte-wide register,
the LSBs of the field are located at the lower register-bit positions, whereas
the MSBs are located at the higher positions.
If only a single data field is stored in a byte-wide register, the field is
justified so that the LSB of the field is located in the lowest register-bit
position, bit 0.
For storage of multiple-byte data words across multiple byte-wide
registers, the LSBs of the word are located at the lower byte-address
locations, while the MSBs are located at the higher byte-address locations.
When writing to any control or data register with less than all 8-bit
positions defined, a logical 0 value must be assigned to each
unused/undefined/reserved position. Writing a logical 1 value to any of
these positions may cause undefined behavior.
•
•
When reading from any control/status or data register with less than all
8-bit positions defined, an indeterminate value is returned from each
unused/undefined/reserved position.
Register values are not affected by RST pin assertion, except for the mode
bit of the Global Modes and Status Register [global_modes; 0x00], the
hclk_freq[1,0] field of the Serial Monitor Source Select Register
[serial_monitor_source; 0x01] and the clk_freq[1,0] field of the PLL
Modes Register [pll_modes; 0x22]. After RST pin assertion, all device
parameters should be reinitialized.
•
The initial values of all registers and RAM are undefined after power is
applied. Exceptions include the mode bit of the Global Modes and Status
Register, the hclk_freq[1,0] field of the Serial Monitor Source Select
Register, the clk_freq[9,8] field of PLL Modes Register, and the Clock
Frequency Select Register. In addition, the JTAG state is reset when power
is applied.
•
•
The register and bit mnemonics used here are based on the mnemonics
used in the Conexant bit pump software.
Writing to unspecified registers may cause unpredictable behavior.
N8973DSD
Conexant
Preliminary Information
3-1
3.0 Registers
RS8973
3.2 Register Summary
Single-Chip SDSL/HDSL Transceiver
y
1(fo5)
lbe
a
lb3-1.gRisrteT
a
T
3.2RgisteSumar
3-2
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.2 Register Summary
(2of5)
ble
a
bl3-1.RgisterT
a
T
N8973DSD
Conexant
Preliminary Information
3-3
3.0 Registers
RS8973
3.2 Register Summary
Single-Chip SDSL/HDSL Transceiver
(3of5)
ble
a
bl3-1.RgisterT
a
T
3-4
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.2 Register Summary
(4of5)
ble
a
bl3-1.RgisterT
a
T
N8973DSD
Conexant
Preliminary Information
3-5
3.0 Registers
RS8973
3.2 Register Summary
Single-Chip SDSL/HDSL Transceiver
(of5)
ble
a
bl3-1.RgisterT
a
T
3-6
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
3
3.3 Register Description
0x00—Global Modes and Status Register (global_modes)
7
6
5
4
3
2
1
0
hw_revision[3] hw_revision[2] hw_revision[1] hw_revision[0]
part_id[2]
part_id[1]
part_id[0]
mode
hw_revision[3:0] Chip Revision Number—Read-only unsigned binary field encoded with the chip revision
number. Smaller values represent earlier versions, while larger values represent later versions.
The zero value represents the original prototype release. Consult factory for current values and
revision.
part_id[2:0]
Part ID—Read-only binary field set to binary 011, identifying the part as RS8973.
The following table shows Part IDs for different DSL transceivers:
part_id[2]
part_id[1]
part_id[0]
Device Name
0
0
0
0
0
0
1
1
0
1
0
1
Bt8952
Bt8960
Bt8970
RS8973
mode
Power Down Mode—Read/write control bit. When set, stops all filter processing and zeros the
transmit output for reduced power consumption. All RAM contents are preserved. The mode
bit is automatically set by RST assertion and upon initial power application. It can be cleared
only by writing a logic 0, at which time filter processing and transmitter operation can proceed.
N8973DSD
Conexant
Preliminary Information
3-7
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x01—Serial Monitor Source Select Register (serial_monitor_source)
7
6
5
4
3
2
1
0
hclk_freq[1]
hclk_freq[0]
smon[5]
smon[4]
smon[3]
smon[2]
smon[1]
smon[0]
hclk_freq[1,0]
HCLK Frequency Select—Read/write binary field selects the frequency of the HCLK output.
hclk_freq[1]
hclk_freq[0]
HCLK Frequency
0
0
Upon assertion of the RST pin and power-on detection, hclk_freq[1,0]
is set to 00. Symbol Frequency (F
) × 16.
QCLK
Upon assertion of the RST pin and power-on detection,
hclk_freq[1,0] is set to 00.
0
1
1
1
0
1
Symbol Frequency (F
) × 16
QCLK
Symbol Frequency (F
) × 32
QCLK
Symbol Frequency (F
) × 64
QCLK
smon[5:0]
Serial Monitor Source Select—Read/write binary field selects the Serial Monitor (SMON)
output source.
smon[5:0]
Source
Decimal
Binary
0 – 47
48
00 0000 – 10 1111
11 0000
Equalizer register file
Digital front-end output/IS input
Linear echo replica
49
11 0001
50
11 0010
DFE subtractor output
51
11 0011
EP subtractor output/slicer input
Timing recovery phase detector output/loop filter input
Timing recovery loop filter output/frequency synthesizer input
52
11 0100
53
11 0101
3-8
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x02—Interrupt Mask Register Low (mask_low_reg)
Independent read/write mask bits for each of the Timer Source Register [timer_source; 0x04] interrupt flags. A
logical 1 represents the masked condition. A logical 0 represents the unmasked condition. All mask bits behave
identically with respect to their corresponding interrupt flags. Setting a mask bit prevents the corresponding
interrupt flag from affecting the IRQ output. Clearing a mask allows the interrupt flag to affect IRQ output.
Unmasking an active interrupt flag will immediately cause the IRQ output to go active, if currently inactive.
Masking an active interrupt flag will cause IRQ to go inactive, if no other unmasked interrupt flags are set.
7
6
5
4
3
2
1
0
t4
t3
snr
meter
sut4
sut3
sut2
sut1
t4
General Purpose Timer 4
General Purpose Timer 3
SNR Alarm Timer
Meter Timer
t3
snr
meter
sut4
sut3
sut2
sut1
Startup Timer 4
Startup Timer 3
Startup Timer 2
Startup Timer 1
0x03—Interrupt Mask Register High (mask_high_reg)
Independent read/write mask bits for each of the IRQ Source Register [irq_source; 0x05] interrupt flags.
Individual mask bit behavior is identical to that specified for Interrupt Mask Register Low [mask_low_reg;
0x02].
7
6
5
4
3
2
1
0
—
—
—
—
sync
high_felm
low_felm
low_snr
sync
Sync Indication
high_felm
low_felm
low_snr
Far-End Level Meter High Alarm
Far-End Level Meter High Alarm
Signal-to-Noise Ratio Low Alarm
N8973DSD
Conexant
Preliminary Information
3-9
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x04—Timer Source Register (timer_source)
Independent read/write (zero only) interrupt flags, one for each of eight internal timers. Each flag bit is set and
stays set when its corresponding timer value transitions from 1 to 0. If unmasked, this event causes the IRQ
output to be activated. Flags are cleared by writing them with a logical 0 value. Once a flag is cleared, a
steady-state timer value of 0 does not reassert the flag. Clearing an unmasked flag causes the IRQ output to
return to the inactive state, if no other unmasked interrupt flags are set.
7
6
5
4
3
2
1
0
t4
t3
snr
meter
sut4
sut3
sut2
sut1
t4
General Purpose Timer 4
General Purpose Timer 3
SNR Alarm Timer
Meter Timer
t3
snr
meter
sut4
sut3
sut2
sut1
Startup Timer 4
Startup Timer 3
Startup Timer 2
Startup Timer 1
0x05—IRQ Source Register (irq_source)
Independent read/write (0 only) interrupt flags, one for each of four internal sources. Each flag bit is set and
stays set when its corresponding source indicates that a valid interrupt condition exists. If unmasked, this event
causes the IRQ output to be activated. Writing a logical 0 to an interrupt flag whose underlying condition no
longer exists causes the flag to be immediately cleared. Attempting to clear a flag whose underlying condition
still exists does not immediately clear the flag, but allows it to remain set until the underlying condition expires,
at which time the flag is cleared automatically. The clearing of an unmasked flag causes the IRQ output to return
to an inactive state, if no other unmasked interrupt flags are set.
7
6
5
4
3
2
1
0
—
—
—
—
sync
high_felm
low_felm
low_snr
sync
Sync Indication—Active when the sync detector is enabled and its accumulated equivalent
comparison is greater than the threshold value stored in the Scrambler Sync Threshold
Register [scr_sync_th; 0x2E].
high_felm
low_felm
low_snr
Far-End Level Meter High Alarm—Active when the far-end level meter value is greater than
the threshold stored in the Far-End High Alarm Threshold Registers
[far_end_high_alarm_th_low, far_end_high_alarm_th_high; 0x30–0x31].
Far-End Level Meter Low Alarm—Active when the far-end level meter value is less than the
threshold stored in the Far-End Low Alarm Threshold Registers [far_end_low_alarm_th_low,
far_end_low_alarm_th_high; 0x32–0x33].
Signal-to-Noise Ratio Low Alarm—Active when the SNR Alarm meter value is greater than
the threshold stored in the SNR Alarm Threshold Registers [snr_alarm_th_low,
snr_alarm_th_high; 0x34–0x35].
3-10
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x06—Channel Unit Interface Modes Register (cu_interface_modes)
7
6
5
4
3
2
1
0
—
—
—
tbclk_pol
rbclk_pol
fifos_mode
interface_mode[1] interface_mode[0]
tbclk_pol
rbclk_pol
fifos_mode
Transmit Baud Clock Polarity—Read/write control bit defines the polarity of the TBCLK
input while in the parallel slave interface mode. When tbclk_pol is set, TQ[1,0] is sampled on
the falling edge of TBCLK; when cleared, TQ[1,0] is sampled on the rising edge.
Receive Baud Clock Polarity—Read/write control bit defines the polarity of the RBCLK input
while in the parallel slave interface mode. When rbclk_pol is set, RQ[1,0] is updated on the
falling edge of RBCLK; when cleared, RQ[1,0] is updated on the rising edge.
FIFO’s Mode—Read/write control bit used to stagger the transmit and receive the FIFO’s read
and write pointers while in the parallel slave interface mode. A logical 1 forces the pointers to
a staggered position; a logical 0 allows them to operate normally. To maximize phase-error
tolerance, fifos_mode must be first set, then cleared once after QCLK-TBCLK-RBCLK
frequency lock is achieved.
interface_
mode[1,0]
Interface Mode—Read/write binary field specifies one of four operating modes for the
channel unit interface.
Interface
Mode
Pin Functions
Mode
91
90
88
89
85
86
[1:0]
00
Parallel master—Parallel quat transfer
synchronized to QCLK out.
Not
used
Not
used
RQ[1]
RQ[0]
TQ[1]
TQ[0]
01
Parallel slave—Parallel quat transfer
synchronized to separate TBCLK and
RBCLK inputs.
TBCLK
RBCLK
RQ[1]
RDAT
RQ[0]
BCLK
TQ[1]
TDAT
TQ[0]
10
11
Serial, magnitude first—Serial quat
transfer synchronized to BCLK out;
magnitude-bit first, followed by sign
bit.
Not
used
Not
used
Not
used
Serial, sign first—Serial quat transfer
synchronized to BCLK out; sign-bit
first, followed by magnitude bit.
Not
used
Not
used
RDAT
BCLK
TDAT
Not
used
N8973DSD
Conexant
Preliminary Information
3-11
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x07—Receive Phase Select Register (receive_phase_select)
7
6
5
4
3
2
1
0
—
imp_short[2]
imp_short[1]
imp_short[0]
rphs[3]
rphs[2]
rphs[1]
rphs[0]
imp_short[2:0]
rphs[3:0]
Impulse Shortening Filter—Read/write binary field that determines the coefficient of the
impulse shortening filter. It must be set per the software provided by Conexant.
Receive Phase Select—Read/write binary field that defines the relative phase relationship
between QCLK and the sampling point of the ADC. The rising edges of QCLK correspond to
the ADC sampling points when rphs equals 0000. Each binary increment of rphs represents a
one-sixteenth QCLK period delay in the sampling point relative to QCLK.
0x08—Linear Echo Canceller Modes Register (linear_ec_modes)
7
6
5
4
3
2
1
0
adapt_
coefficients
—
—
enable_dc_tap
zero_coefficients
zero_output
adapt_gain[1]
adapt_gain[0]
enable_dc_tap
Enable DC Tap—Read/write control bit which, when set, forces a constant + 1 value into the
last data tap of the LEC. This condition enables cancellation of any residual DC offset present
at the input to the LEC. When cleared, the last data tap operates normally, as the oldest
transmit data sample.
adapt_coefficents Adapt Coefficients—Read/write control bit which enables coefficient adaptation when set;
disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is
disabled.
zero_coefficients Zero Coefficients—Read/write control bit that continuously zeros all coefficients when set;
allows normal coefficient updates if enabled, when cleared. This behavior differs slightly from
the similar function (zero_coefficients) of the FFE and EP filters.
zero_output
Zero Output—Read/write control bit which, when set, zeros the echo replica before
subtraction from the input signal. Achieves the affect of disabling or bypassing the echo
cancellation function. Does not disable coefficient adaptation. When cleared, normal echo
canceller operation is performed.
adapt_gain[1,0]
Adaptation Gain—Read/write binary field which specifies the adaptation gain.
adapt_gain[1,0]
Normalized Gain
00
01
10
11
1
4
64
512
3-12
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x09—Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes)
7
6
5
4
3
2
1
0
adapt_
coefficients
negate_symbol symbol_delay[2] symbol_delay[1] symbol_delay[0]
zero_coefficients
zero_output
adapt_gain
negate_symbol
Negate Symbol—Read/write control bit which, when set, inverts (2s complement) the receive
signal path at the output of the nonlinear echo canceller. When cleared, the signal path is
unaffected. This function is independent of all other NEC mode settings.
symbol_delay[2:0] Symbol Delay—Read/write binary field which specifies the number of symbol delays inserted
in the transmit symbol input path.
adapt_coefficients Adapt Coefficients—Same function as LEC Modes Register [linear_ec_modes; 0x08].
zero_coefficients Zero Coefficients—Same function as LEC Modes Register.
zero_output
adapt_gain
Zero Output—Same function as LEC Modes Register.
Adaptation Gain—Read/write control bit which specifies the adaptation gain. When
adapt_gain is set, the adaptation gain is eight times higher than when cleared.
0x0A—Decision Feedback Equalizer Modes Register (dfe_modes)
7
6
5
4
3
2
1
0
adapt_
coefficients
—
—
—
—
zero_coefficients
zero_output
adapt_gain
adapt_coefficents Adapt Coefficients—Read/write control bit which enables coefficient adaptation when set;
disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is
disabled.
zero_coefficients Zero Coefficients—Read/write control bit which continuously zeros all coefficients when set;
allows normal coefficient updates, if enabled, when cleared.
zero_output
adapt_gain
Zero Output—Read/write control bit which, when set, zeros the filter output before subtraction
from the FFE output. Achieves the affect of disabling or bypassing the equalization function.
Does not disable coefficient adaptation. When cleared, the normal equalizer operation is
performed.
Adaptation Gain—Read/write control bit which specifies the adaptation gain. When
adapt_gain is set, the adaptation gain is eight times higher than when cleared.
N8973DSD
Conexant
Preliminary Information
3-13
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x0B—Transmitter Modes Register (transmitter_modes)
7
6
5
4
3
2
1
0
—
isolated_pulse[1] isolated_pulse[0] transmitter_off
htur_lfsr
data_source[2] data_source[1] data_source[0]
isolated_pulse[1,0] Isolated Pulse Level Select—Read/write binary field that selects one of four output pulse
levels while in the isolated pulse or alternating symbol transmitter mode.
isolated_pulse[1,0]
Output Pulse Level
00
01
10
11
– 3
– 1
+ 3
+ 1
transmitter_off
htur_lfsr
Transmitter Off—Read/write control bit that zeros the output of the transmitter when set;
allows normal transmitter operation (as defined by data_source[2:0]) when cleared.
Remote Unit (HTU-R/NT) Polynomial Select—Read/write control bit selects one of two
feedback polynomials for the transmit scrambler. When set, this bit selects the remote unit
transmit polynomial (x– 23 + x– 18 + 1) ; when cleared, it selects the local unit (HTU-C/LT)
polynomial (x– 23 + x– 5 + 1) .
data_source[2:0] Data Source—Read/write binary field that selects the data source and mode of the transmitter
output. The transmitter must be enabled (transmitter_off = 0) for these modes to be active.
data_source [2:0]
Transmitter Mode
000
Isolated pulse. Level selected by isolated_pulse[1:0]. The meter timer must be enabled and in the
continuous mode. The pulse repetition interval is determined by the meter timer countdown interval.
001
Four-level scrambled detector loopback. Sign and magnitude bits from the receiver detector are
scrambled and looped back to the transmitter. Feedback polynomial determined by the htur_lfsr control
bit.
010
011
100
Four-level unscrambled data. Transmits the four-level (2B1Q) sign and magnitude bits from the channel
unit transmit interface without scrambling.
Four-level scrambled 1s. Transmits a scrambled, constant high-logic level as a four-level (2B1Q) signal.
Feedback polynomial determined by the htur_lfsr control bit.
Alternating symbol mode. Outputs symbols of alternating polarity. Level is selected by
isolated_pulse[1:0]. The meter timer must be enabled and in continuous mode. The half period of the
output signal is defined by the meter timer countdown interval.
101
110
Four-level scrambled data. Scrambles and transmits the four-level (2B1Q) sign and magnitude bits from
the channel unit transmit interface. Feedback polynomial determined by the htur_lfsr control bit.
Two-level unscrambled data. Constantly forces the magnitude bit from the channel unit transmit interface
to a logical 0 and transmits the resulting two-level signal (as determined by the sign bit) without
scrambling. Valid output levels limited to + 3, – 3.
111
Two-level scrambled 1s. Transmits a scrambled, constant high-logic level as a two-level signal. The
feedback polynomial is determined by the htur_lfsr control bit. The scrambler is run at the symbol rate
(half-bit rate) to produce the sign bit of the transmitted signal while the magnitude bit is sourced with a
constant logical 0. Valid output levels are limited to + 3, – 3.
3-14
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x0C—Timer Restart Register (timer_restart)
Independent read/write restart bits, one for each of the eight internal timers. Setting an individual bit causes the
associated timer to be reloaded with the contents of its interval register. For the four symbol-rate timers (meter,
snr, t3, t4), reloading occurs within 1 symbol period. For the four start-up timers (sut1–4), reloading occurs
within 1024 symbol periods. Once the timer is reloaded, the restart bit is automatically cleared. If a restart bit is
set and then cleared (by writing a logical 0) before the reload actually takes place, no timer reload occurs. Once
reloaded, if enabled in the Timer Enable Register [timer_enable; 0x0D], the timer begins counting down toward
zero; otherwise, it holds at the interval register value.
7
6
5
4
3
2
1
0
t4
t3
snr
meter
sut4
sut3
sut2
sut1
t4
General Purpose Timer 4
General Purpose Timer 3
SNR Alarm Timer
Meter Timer
t3
snr
meter
sut4
sut3
sut2
sut1
Startup Timer 4
Startup Timer 3
Startup Timer 2
Startup Timer 1
0x0D—Timer Enable Register (timer_enable)
Independent read/write enable bits, one for each of the eight internal timers. When any individual bit is set, the
corresponding timer is enabled for counting down from its current value toward 0. For the four symbol-rate
timers (meter, snr, t3, t4), counting begins within 1 symbol period. For the four start-up timers (sut1-4), counting
begins within 1024 symbol periods. When an enable bit is cleared, the timer is disabled from counting and holds
its current value. If an enable bit is set and then cleared before a count actually takes place, no timer countdown
occurs.
7
6
5
4
3
2
1
0
t4
t3
snr
meter
sut4
sut3
sut2
sut1
t4
General Purpose Timer 4
General Purpose Timer 3
SNR Alarm Timer
Meter Timer
t3
snr
meter
sut4
sut3
sut2
sut1
Startup Timer 4
Startup Timer 3
Startup Timer 2
Startup Timer 1
N8973DSD
Conexant
Preliminary Information
3-15
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x0E—Timer Continuous Mode Register (timer_continuous)
Independent read/write mode bits, one for each of the eight internal timers. When any individual bit is set, the
corresponding timer is placed in the continuous count mode. While in this mode, after reaching the 0 count, an
enabled timer will reload the contents of its interval register and continue counting. When a mode bit is cleared,
the timer is taken out of the continuous mode. While in this configuration, after reaching the zero count, an
enabled timer will simply stop counting and remain at 0.
7
6
5
4
3
2
1
0
t4
t3
snr
meter
sut4
sut3
sut2
sut1
For a description of bit-fields, refer to the description given above for register 0x0D—Timer Enable Register
(timer_enable).
0x0F—Miscellaneous/Test Register (misc_test)
A 1-byte read/write register that is automatically initialized to 0x00 upon RST assertion and initial power
application.
7
6
5
4
3
2
1
0
res[6]
res[5]
reg_clk_en
res[4]
res[3]
res[2]
res[1]
async_mode
res[6:1]
Reserved Bits—Read/write binary field that is automatically initialized to 0x00 upon RST
assertion and initial power application.
reg_clk_en
Regenerator Clock Enable—When set, it bypasses the frequency synthesizer and timing
recovery. In this mode, the symbol rate equals MCLK ÷ 16. Normally this bit is reset and
should be set only for the transceiver configured as REG–C in a regenerator configuration.
Refer to Section 1.3, Regenerator Configuration.
async_mode
Asynchronous Mode—Read/write control bit that selects asynchronous MCI timing mode,
when set. When reset it selects synchronous mode MCI timing. Refer to
Table 5-13, Microcomputer Interface Timing Requirements, and Table 5-14, Microcomputer
Interface Switching Characteristics, for MCI timing requirements and switching
characteristics.
0x10, 0x11—Startup Timer 1 Interval Register (sut1_low, sut1_high)
A 2-byte read/write register that stores the countdown interval for Startup Timer 1 in unsigned binary format.
Each increment represents 1024 symbol periods. The contents of this register are automatically loaded into its
associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the continuous
mode.
0x12, 0x13—Startup Timer 2 Interval Register (sut2_low, sut2_high)
A 2-byte read/write register that stores the countdown interval for Startup Timer 2 in unsigned binary format.
Each increment represents 1024 symbol periods. The contents of this register are automatically loaded into its
associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the continuous
mode.
3-16
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x14, 0x15—Startup Timer 3 Interval Register (sut3_low, sut3_high)
A 2-byte read/write register that stores the countdown interval for Startup Timer 3 in unsigned binary format.
Each increment represents 1024 symbol periods. The contents of this register are automatically loaded into its
associated timer after the timer_restart bit is set, or after the timer counts down to zero while in the continuous
mode.
0x16, 0x17—Startup Timer 4 Interval Register (sut4_low, sut4_high)
A 2-byte read/write register that stores the countdown interval for Startup Timer 4 in unsigned binary format.
Each increment represents 1024 symbol periods. The contents of this register are automatically loaded into its
associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the continuous
mode.
0x18, 0x19—Meter Timer Interval Register (meter_low, meter_high)
A 2-byte read/write register that stores the countdown interval for the Meter Timer in unsigned binary format.
Each increment represents one symbol period. The contents of this register are automatically loaded into its
associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the continuous
mode.
0x1A, 0x1B—SNR Alarm Timer Interval Register (snr_timer_low, snr_timer_high)
A 2-byte read/write register that stores the countdown interval for the SNR Alarm Timer in unsigned binary
format. Each increment represents one symbol period. The contents of this register are automatically loaded into
its associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the
continuous mode.
0x1C, 0x1D—General Purpose Timer 3 Interval Register (t3_low, t3_high)
A 2-byte read/write register that stores the countdown interval for General Purpose Timer 3 in unsigned binary
format. Each increment represents one symbol period. The contents of this register are automatically loaded into
its associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the
continuous mode.
0x1E, 0x1F—General Purpose Timer 4 Interval Register (t4_low, t4_high)
A 2-byte read/write register that stores the countdown interval for General Purpose Timer 4 in unsigned binary
format. Each increment represents one symbol period. The contents of this register are automatically loaded into
its associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the
continuous mode.
N8973DSD
Conexant
Preliminary Information
3-17
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x20—Clock Frequency Select Register (clock_freq_select)
7
6
5
4
3
2
1
0
clk_freq[7]
clk_freq[6]
clk_freq[5]
clk_freq[4]
clk_freq[3]
clk_freq[2]
clk_freq[1]
clk_freq[0]
clk_freq[7:0]
Read/write binary field, which along with clk_freq[9,8] of the PLL Modes Register (0x22),
specifies the data rate used by the clock synthesizer to generate the appropriate internal clock.
clk_freq = 18 to 290
data rate = clk_freq × 8 kbps (144 kbps to 2320 kbps)
The power-on default is clk_freq = 0 which selects the internal clock corresponding to
1280 kbps.
0x21—ADC Control Register (adc_control)
7
6
5
4
3
2
1
0
cont_time[1]
cont_time[0]
loop_back[1]
loop_back[0] switch_cap_pole
gain[2]
gain[1]
gain[0]
cont_time[1,0]
Continuous Time Control—Read/write binary field that controls the cut-off frequency of the
analog RC reconstruction filter, according to the data rates.
cont_time[1,0]
Data Rate Range
800 to 1200 kbps
Less than 800 kbps
Above 1200 kbps
Reserved
00
01
10
11
The “00” setting of the continuous_time control bits enables an output pulse shape that
conforms to the ETSI HDSL specifications at 1168 kbps.
The “01” setting enables an output pulse shape that conforms to the ANSI and ETSI HDSL
specifications at 784 kbps.
The “10” setting enables an output pulse shape that conforms to the ETSI HDSL
specifications at 2320 kbps.
loop_back[1,0]
Loopback Control—Read/write binary field that specifies if loopback is enabled, and the type
of loopback that is enabled. During transmitting loopback, the differential receiver inputs
(RXP, RXN) are disabled. The loopback path is intended to go from the transmitter outputs
(TXP, TXN) through the external hybrid circuit and back into the differential receiver balance
inputs (RXBP, RXBN). During silent loopback, the transmitter is turned off. The output of the
pulse-shaping filter in the transmit section is internally connected to the input of the ADC in
the receive section.
loop_back[1,0]
Function
00
01
10
11
Normal Operation (Loopback Disabled)
Hybrid Inputs Disabled (RXBP, RXBN)
Transmitting Loopback
Silent Loopback
3-18
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
switch_cap_pole
Switch Cap Pole Control—Read/write control bit, specifies the pulse shaping filter
characteristics. When switch_cap_pole is set, it enables output pulse shape conforming to
ETSI specifications for 2320 kbps operation. When reset, it enables output pulse shape for
other data rates.
gain[2:0]
Gain Control—Read/write binary field that specifies the gain of the VGA.
gain[2:0]
000
VGA Gain
0 dB
001
3 dB
010
6 dB
011
9 dB
100
101
110
111
12 dB
15 dB
15 dB
15 dB
0x22—PLL Modes Register (pll_modes)
7
6
5
4
3
2
1
0
phase_detector_ phase_detector_
gain[1] gain[0]
clk_freq[9]
clk_freq[8]
—
freeze_pll
pll_gain[1]
pll_gain[0]
clk_freq[9,8]
Clock Frequency Select—See description for 0x20—Clock Frequency Select Register
(clock_freq_select).
phase_detector_
gain[1,0]
Phase Detector Gain—Read/write binary field that specifies one of three gain settings for the
timing-recovery phase detector function.
phase_detector_gain[1,0]
Normalized Gain
00
01
10
11
1
2
4
Reserved
freeze_pll
Freeze PLL—Read/write control bit. When set, this bit zeros the proportional term of the loop
compensation filter and disables accumulator updates, causing the PLL to hold its current
frequency. When this bit is cleared, proportional term effects and accumulator updates are
enabled, allowing the PLL to track the phase of the incoming data.
pll_gain[1,0]
PLL Gain—Read/write binary field that specifies the gain (proportional and integral
coefficients) of the loop compensation filter.
Normalized
Normalized
pll_gain[1:0]
Proportional Coefficients
Integral Coefficients
00
01
10
11
1
4
16
64
1
32
256
4096
N8973DSD
Conexant
Preliminary Information
3-19
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x23—Test Register (test_reg23)
A 3-byte read/write register used for device testing by Conexant. This register is automatically initialized to
0x000000 upon RST assertion and initial power application. This register must be initialized according to the
software provided by Conexant.
0x24, 0x25—Timing Recovery PLL Phase Offset Register (pll_phase_offset_low,
pll_phase_offset_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The value of this register is
subtracted from the output of the timing-recovery phase detector after the phase-detector meter, but before the
loop compensation filter.
0x26, 0x27—Receiver DC Offset Register (dc_offset_low, dc_offset_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The value of this register is
subtracted from the receiver signal path at the output of the ADC block, ahead of the DC level and signal level
meters.
0x28—Transmitter Calibration Register (tx_calibrate)
7
6
5
4
3
2
1
0
—
—
tx_calibrate[3]
tx_calibrate[2]
tx_calibrate[1]
tx_calibrate[0]
—
—
tx_calibrate[3:0]
Transmit Calibrate—4-bit, 2s-complement, read-only field containing the nominal setting for
the transmitter gain. The value of the Transmit Calibration Register is set during
manufacturing testing by Conexant, and corresponds to the value required to operate the
RS8973 at a nominal 13.5 dBm transmit power, assuming the recommended transformer
coupling/hybrid circuit is used. Users can override this calibration by writing their own value
into the Transmitter Gain Register [tx_gain; 0x29].
3-20
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x29—Transmitter Gain Register (tx_gain)
7
6
5
4
3
2
1
0
—
—
tx_gain[3]
tx_gain[2]
tx_gain[1]
tx_gain[0]
—
—
tx_gain[3:0]
Transmit Gain—A 4-bit, 2s-complement, read/write field controlling the transmitter gain.
Upon initialization, the value in the Transmitter Calibration Register [tx_calibrate; 0x28] can
be written into this register by software, to set the transmitter gain to the nominal value.
Alternatively, the user can set it to another desired value. The transmitter gain settings are
relative to the setting that provides a nominal output power of 13.5 dBm.
tx_gain[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Relative Transmitter Gain (dB)
–1.60
–1.36
–1.13
–0.91
–0.69
–0.48
–0.27
–0.07
0.13
0.32
0.51
0.70
0.88
1.05
1.23
1.40
0x2A, 0x2B—Noise-Level Histogram Threshold Register (noise_histogram_th_low,
noise_histogram_th_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the absolute
value of the slicer error signal produced by the detector. A count of error samples that exceeds this threshold
(greater than) is accumulated in the noise-level histogram meter.
0x2C, 0x2D—Error Predictor Pause Threshold Register (ep_pause_th_low,
ep_pause_th_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the absolute
value of the slicer error signal produced by the detector. The result of this comparison (slicer error greater than
this threshold) is used to initiate a pause condition by zeroing the output of the error predictor correction signal
before subtraction from the receive signal path. Error predictor coefficient updates are not affected. The pause
condition lasts for a fixed 5-symbol period from the time the threshold was last exceeded.
N8973DSD
Conexant
Preliminary Information
3-21
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x2E—Scrambler Synchronization Threshold Register (scr_sync_th)
A 7-bit read/write register representing an unsigned binary number. The contents of this register are used to test
for scrambler synchronization during the automatic-scrambler synchronization mode of the symbol detector.
The test passes when the count of equivalent scrambler and detector output bits is greater than the value of this
register. When the auto-scrambler sync mode is not enabled, the contents of this register are not used.
7
6
5
4
3
2
1
0
—
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x30, 0x31—Far-End High Alarm Threshold Register (far_end_high_alarm_th_low,
far_end_high_alarm_th_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of
the far-end level meter. If the meter reading is greater than this threshold, the high_felm interrupt flag is set in
the IRQ Source Register [irq_source; 0x05].
0x32, 0x33—Far-End Low Alarm Threshold Register (far_end_low_alarm_th_low,
far_end_low_alarm_th_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of
the far-end level meter. If the meter reading is less than this threshold, the low_felm interrupt flag is set in the
IRQ Source Register [irq_source; 0x05].
0x34, 0x35—SNR Alarm Threshold Register (snr_alarm_th_low, snr_alarm_th_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of
the SNR alarm meter. If the meter reading is greater than this threshold, the low_snr interrupt flag is set in the
IRQ Source Register [irq_source; 0x05].
0x36, 0x37—Cursor Level Register (cursor_level_low, cursor_level_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x2AAA (one-third of the maximum positive value). The value
of this register represents the expected level of a noise-free + 1 receive symbol at the slicer input. It is multiplied
by 2 to produce the positive and negative slicing levels, in addition to 0, used by the symbol detector in
four-level slicing mode. This value is also used to scale the detector output when computing the equalizer error
and slicer error signals. The detected symbol (– 3, – 1, + 1, + 3) is multiplied by the value of this register to
produce the scaled output.
0x38, 0x39—DAGC Target Register (dagc_target_low, dagc_target_high)
A 2-byte read/write register interpreted as a 16-bit, 2s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is subtracted from the
absolute value of the receive signal at the output of the DAGC function. The difference is used as the error input
to the DAGC while in the self-adaptation mode. In the DAGC’s equalizer-error adaptation mode, the contents of
this register are not used.
3-22
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x3A—Symbol Detector Modes Register (detector_modes)
7
6
5
4
3
2
1
0
enable_peak_
detector
output_mux_
control[1]
output_mux_
control[0]
scr_out_to_dfe
two_level
lfsr_lock
htur_lfsr
descr_on
enable_peak_
detector
Enable Peak Detector—Read/write control bit that enables the peak detection function when
set; disables the function when cleared. When enabled, the peak detector output overrides the
slicer output if the peak detection criteria are met. If the criteria are not met, or if the function
is disabled, the slicer output is used and peak detector output is ignored.
output_mux_
control[1,0]
Output Multiplexer Control—Read/write binary field that selects the source of the detector
output connected to the channel unit receive interface.
output_mux_control[1,0]
Detector Output to CU Receive Interface
Same as scr_out_to_dfe selection
Transmitter loopback output from CU
transmit interface
00
01
10
11
Scrambler/descrambler output
Reserved
scr_out_to_dfe
two_level
Scrambler Output to DFE—Read/write control bit that selects the source of the detector output
connected to the DFE and timing recovery module inputs and the transmitter’s detector
loopback input. When set, this bit selects the scrambler/descrambler function; when cleared, it
selects the slicer/peak detector output.
Two-Level Mode—Read/write control bit that selects two-level mode when set, four-level
mode when cleared. Affects the slicer and the scrambler/descrambler function. In two-level
mode, the slicer uses a single threshold set at zero to recover sign bits only; all magnitude
information is lost. Scrambler/descrambler updates are slowed to the symbol rate (half the
normal bit rate) to process only sign information as well; all magnitude output bits are sourced
with a constant logic zero value, producing two-level symbols constrained to +3 and –3 values.
In four-level mode, the slicer uses two thresholds derived from the Cursor Level Register
[cursor_level_low, cursor_level_high; 0x36–0x37], as well as the zero threshold, to recover
both sign and magnitude information. The scrambler/descrambler is updated at the full bit rate
to process both sign and magnitude bits as well.
N8973DSD
Conexant
Preliminary Information
3-23
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
lfsr_lock
LFSR Lock—Read/write control bit that enables the auto-scrambler synchronization mode
(lfsr_lock) in the detector when set and disables this mode when cleared. Affects the behavior
of the scrambler/descrambler function, overriding the descr_on setting. When enabled, the
scrambler/descrambler is forced into the descrambler mode for 23 cycles. It is then switched to
the scrambled-1s mode for 128 cycles. While in this mode, the outputs of the scrambler and the
slicer/peak detector are compared against one another. The number of equivalent bits (equal
comparisons) is accumulated and compared to the value of the Scrambler Synchronization
Threshold Register [scr_sync_th; 0x2E].
At any time during the 128 cycles, if the count exceeds the threshold (greater than), the sync
interrupt flag is set in the IRQ source register [irq_source; 0x05] and the process terminates
with the scrambler/descrambler left in the scrambled-1s mode. (The sync interrupt flag cannot
be cleared while lfsr_lock remains high.) After 128 cycles, if the threshold is not exceeded, the
accumulator is cleared, the scrambler/descrambler re-enters the descrambler mode for another
23 cycles, and the process repeats until either sync is achieved or this mode is disabled. Once
disabled, the sync interrupt flag can be cleared (if active) and the scrambler/descrambler
returns to the mode specified by descr_on.
htur_lfsr
descr_on
Remote Unit (HTU-R/NT) Polynomial Select—Read/write control bit that selects one of two
feedback polynomials for the scrambler/descrambler. When set, this bit selects the remote unit
– 23
– 5
(HTU-R/NT) receive polynomial (x
+ x + 1); when cleared, it selects the local unit
+ 1).
– 23
– 18
(HTU-C/LT) polynomial (x
+ x
Descrambler/Scrambler Select—Read/write control bit that configures the
scrambler/descrambler function as a descrambler when set, and as a scrambler when cleared.
As a scrambler, this bit enables the scrambler/descrambler to generate a scrambled-all-1s
sequence (constant high logic-level input); all incoming data is ignored. In the auto-scrambler
synchronization mode (lfsr_lock = 1), this selection is overwritten though the value of the
control bit is unaffected.
0x3B—Peak Detector Delay Register (peak_detector_delay)
A 4-bit read/write register interpreted as an unsigned binary number. Specifies a number of additional symbol
delays inserted in the peak detector input path of the symbol detector. Must be set to a value that equalizes the
total path delay in each of the peak detector and slicer input paths according to the following formula: peak
detector delay register value = DAGC delays + FFE delays – fixed peak detector input delays. The DAGC and
FFE delays are not fixed, but result from the microprogrammed implementation of these functions. The value
should be set according to software supplied by Conexant.
7
6
5
4
3
2
1
0
—
—
—
—
D[3]
D[2]
D[1]
D[0]
3-24
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x3C—Digital AGC Modes Register (dagc_modes)
7
6
5
4
3
2
1
0
eq_error_
adaptation
—
—
—
—
—
adapt_coefficients
adapt_gain
eq_error_
adaptation
Equalizer Error Adaptation—Read/write control bit that selects between the equalizer-error
adaptation mode when set, and the self-adaptation mode when cleared. Equalizer error
adaptation uses the equalizer error signal produced by the slicer as the DAGC error input
signal. In self-adaptation, the value of the DAGC Target Register [dagc_target_low,
dagc_target_high; 0x38–0x39] is subtracted from the absolute value of the receive signal at the
output of the DAGC, and this difference is used as the error input signal.
adapt_coefficients Adapt Coefficients—Read/write control bit that enables coefficient adaptation when set;
disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is
disabled.
adapt_gain
Adaptation Gain—Read/write control bit that specifies the adaptation gain. When this bit is
set, the adaptation gain is eight times higher than when cleared.
0x3D—Feed Forward Equalizer Modes Register (ffe_modes)
7
6
5
4
3
2
1
0
adapt_
coefficients
—
—
—
—
adapt_last_coeff zero_coefficents
adapt_gain
adapt_last_coeff Adapt Last Coefficient—Read/write control bit that enables adaptation of the last (oldest)
coefficient only when set; allows all coefficient adaptation when cleared. Overall coefficient
adaptation must be enabled (adapt_coefficients = 1) for this behavior to occur. If coefficient
adaptation is disabled (adapt_coefficients = 0), the value of this control bit is not used.
zero_coefficients Zero Coefficients—Read/write control bit that, with coefficient adaptation enabled
(adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal
coefficient updates when cleared. If coefficient adaptation is disabled (adapt_coefficients = 0),
this control bit has no affect. This behavior differs slightly from the similar function
(zero_coefficients) of the LEC, NEC, and DFE filters. Whenever this bit is set, it must be
accompanied by adapt_coefficients (set) for a 2-symbol time period.
adapt_coefficents Adapt Coefficients—Read/write control bit that enables coefficient adaptation when set;
disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is
disabled. This overall coefficient adaptation must be enabled for adapt_last_coeff to have an
affect.
adapt_gain
Adaptation Gain—Read/write control bit that specifies the adaptation gain. When set, the
adaptation gain is four times higher than when cleared.
N8973DSD
Conexant
Preliminary Information
3-25
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x3E—Error Predictor Modes Register (ep_modes)
7
6
5
4
3
2
1
0
adapt_
coefficients
—
—
—
—
zero_output
zero_coefficients
adapt_gain
zero_output
Zero Output—Read/write control bit that, when set, zeros the error predictor correction signal
before subtraction at the slicer. Achieves the affect of disabling, or bypassing, the error
predictor function. Does not disable coefficient adaptation. When cleared, normal error
predictor operation is performed.
zero_coefficients Zero Coefficients—Read/write control bit that, with coefficient adaptation enabled
(adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal
coefficient updates when cleared. If coefficient adaptation is disabled (adapt_coefficients = 0),
this control bit has no affect. This behavior differs slightly from the similar function
(zero_coefficients) of the LEC, NEC, and DFE filters. Whenever this bit is set, it must be
accompanied by adapt_coefficients (set) for a 2-symbol time period.
adapt_coefficents Adapt Coefficients—Read/write control bit that enables coefficient adaptation when set and
disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is
disabled.
adapt_gain
Adaptation Gain—Read/write control bit that specifies the adaptation gain. When this bit is
set, the adaptation gain is four times higher than when cleared.
0x40, 0x41—Phase Detector Meter Register (pdm_low, pdm_high)
A 2-byte read-only register containing the 16 MSBs of the 26-bit, 2s-complement phase detector meter
accumulator. This meter sums the output of the timing recovery module’s phase detector over each Meter Timer
countdown interval, before being offset by the Phase Offset Register [pll_phase_offset_low,
pll_phase_offset_high; 0x24, 0x25]. Automatically loaded at the end of each interval, the meter register must be
read low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5F).
7
6
5
4
3
2
1
0
D[17]
D[25]
D[16]
D[24]
D[15]
D[23]
D[14]
D[22]
D[13]
D[21]
D[12]
D[20]
D[11]
D[19]
D[10]
D[18]
0x42—Overflow Meter Register (overflow_meter)
A single-byte read-only register containing all 8 bits of the unsigned overflow meter accumulator. This meter
counts the number of ADC overflow conditions which occur during each meter timer countdown interval,
limited to a maximum count of 255 (0xFF). The meter register is automatically loaded at the end of each
countdown interval.
7
6
5
4
3
2
1
0
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
3-26
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x44, 0x45—DC Level Meter Register (dc_meter_low, dc_meter_high)
A 2-byte read-only register containing the 16 MSBs of the 32-bit, 2s-complement DC-level meter accumulator.
This meter sums the value of the receive signal input path—after DC offset correction but before echo
cancellation—over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the
meter register must be read low byte first, followed by high byte, unseparated by any other meter access
(addresses 0x40 to 0x5F).
7
6
5
4
3
2
1
0
D[23]
D[31]
D[22]
D[30]
D[21]
D[29]
D[20]
D[28]
D[19]
D[27]
D[18]
D[26]
D[17]
D[25]
D[16]
D[24]
0x46, 0x47—Signal Level Meter Register (slm_low, slm_high)
A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned signal-level meter accumulator. This
meter sums the absolute value of the receive signal input path—after DC offset correction but before echo
cancellation (same point as the DC level meter)—over each Meter Timer countdown interval. Automatically
loaded at the end of each interval, the meter register must be read low byte first, followed by high byte,
unseparated by any other meter access (addresses 0x40 to 0x5F).
7
6
5
4
3
2
1
0
D[23]
D[31]
D[22]
D[30]
D[21]
D[29]
D[20]
D[28]
D[19]
D[27]
D[18]
D[26]
D[17]
D[25]
D[16]
D[24]
0x48, 0x49—Far-End Level Meter Register (felm_low, felm_high)
A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned far-end level meter accumulator. This
meter sums the absolute value of the receive signal path—after echo cancellation but before the DAGC
function—over each Meter Timer countdown interval. Automatically loaded at the end of each interval, this
meter register must be read low byte first, followed by high byte, unseparated by any other meter access
(addresses 0x40 to 0x5F).
7
6
5
4
3
2
1
0
D[23]
D[31]
D[22]
D[30]
D[21]
D[29]
D[20]
D[28]
D[19]
D[27]
D[18]
D[26]
D[17]
D[25]
D[16]
D[24]
N8973DSD
Conexant
Preliminary Information
3-27
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x4A, 0x4B—Noise Level Histogram Meter Register (noise_histogram_low,
noise_histogram_high)
A 2-byte read-only register containing all 16 bits of the unsigned noise-level histogram meter accumulator. This
meter counts the number of high-noise-level conditions which occur during each Meter Timer countdown
interval. A high-noise-level condition is defined as the absolute value of the slicer error signal exceeding
(greater than) the threshold specified in the Noise-level Histogram Threshold Register [0x2A, 2B].
Automatically loaded at the end of each countdown interval, this meter register must be read low byte first,
followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5F).
7
6
5
4
3
2
1
0
D[7]
D[15]
D[6]
D[14]
D[5]
D[13]
D[4]
D[12]
D[3]
D[11]
D[2]
D[10]
D[1]
D[9]
D[0]
D[8]
0x4C, 0x4D—Bit Error Rate Meter Register (ber_meter_low, ber_meter_high)
A 2-byte read-only register containing all 16 bits of the unsigned BER meter accumulator. This meter counts the
number of error-free bits recovered by the detector during each Meter Timer countdown interval. An error-free
bit is defined as a match (equal comparison) of the detector’s slicer/peak detector output and its
scrambler/descrambler output, when operating as a scrambler. When the scrambler/descrambler is operated as a
descrambler, the meter simply counts the number of logical 1s produced by the descrambler. The meter register
is automatically loaded at the end of each countdown interval, and must be read low byte first, followed by high
byte, unseparated by any other meter access (addresses 0x40 to 0x5F).
7
6
5
4
3
2
1
0
D[7]
D[15]
D[6]
D[14]
D[5]
D[13]
D[4]
D[12]
D[3]
D[11]
D[2]
D[10]
D[1]
D[9]
D[0]
D[8]
0x4E—Symbol Histogram Meter Register (symbol_histogram)
A single-byte read-only register containing 8 MSBs of the 16-bit unsigned symbol histogram meter
accumulator. This meter counts the number of + 1 or – 1 symbols detected during each Meter Timer countdown
interval. No increment occurs when a + 3 or – 3 symbol is detected. The meter register is automatically loaded
at the end of each countdown interval.
7
6
5
4
3
2
1
0
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
3-28
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x50, 0x51—Noise Level Meter Register (nlm_low, nlm_high)
A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned noise-level meter accumulator. This
meter sums the absolute value of the detector’s slicer-error signal over each Meter Timer countdown interval.
Automatically loaded at the end of each interval, the meter register must be read the low byte first, followed by
high byte, unseparated by any other meter access (addresses 0x40 to 0x5F).
7
6
5
4
3
2
1
0
D[23]
D[31]
D[22]
D[30]
D[21]
D[29]
D[20]
D[28]
D[19]
D[27]
D[18]
D[26]
D[17]
D[25]
D[16]
D[24]
0x5E, 0x5F— PLL Frequency Register (pll_frequency_low, pll_frequency_high)
A 2-byte read/write register comprising 16 MSBs of the 31-bit, 2s-complement timing recovery loop
compensation filter accumulator. Treated much like a meter register, the frequency register must be read low
byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5F). Writes must
occur in the same order, with the low byte written first, followed by the high byte. Write accesses can be
separated by any number of other read or write accesses.
7
6
5
4
3
2
1
0
D[22]
D[30]
D[21]
D[29]
D[20]
D[28]
D[19]
D[27]
D[18]
D[26]
D[17]
D[25]
D[16]
D[24]
D[15]
D[23]
0x70—LEC Read Tap Select Register (linear_ec_tap_select_read)
A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 119 decimal.
When written, it causes the selected 32-bit coefficient of the LEC to be subsequently loaded into the Access
Data Register [access_data_byte[3:0]; 0x7C–0x7F] within 2 symbol periods. Does not affect the value of the
coefficient. No other data access should occur between the time the Read Tap Select Register is written and the
time the Access Data Register is read, or the data may be corrupted.
7
6
5
4
3
2
1
0
—
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x71—LEC Write Tap Select Register (linear_ec_tap_select_write)
A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 119 decimal.
When written, it causes all 32 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] to be
subsequently written to the selected LEC coefficient within 2 symbol periods. Does not affect the value of the
access data register.
7
6
5
4
3
2
1
0
—
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
N8973DSD
Conexant
Preliminary Information
3-29
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x72—NEC Read Tap Select Register (nonlinear_ec_tap_select_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal.
When written, this register causes the selected 14-bit coefficient of the NEC to be subsequently loaded into the
lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within 2 symbol periods.
Does not affect the value of the coefficient. No other data access should occur between the time the Read Tap
Select Register is written and the time the Access Data Register is read, or the data may be corrupted.
7
6
5
4
3
2
1
0
—
—
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x73—NEC Write Tap Select Register (nonlinear_ec_tap_select_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal.
When written, this register causes the lowest-order 14 bits of the Access Data Register [access_data_byte[3:0];
0x7C–0x7F] to be subsequently written to the selected NEC coefficient within 2 symbol periods. Does not
affect the value of the access data register.
7
6
5
4
3
2
1
0
—
—
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x74—DFE Read Tap Select Register (dfe_tap_select_read)
A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 115 decimal.
When written, this register causes the selected 16-bit coefficient of the DFE to be subsequently loaded into the
lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within 2 symbol periods.
Does not affect the value of the coefficient. No other data access should occur between the time the Read Tap
Select Register is written and the time the Access Data Register is read, or the data may be corrupted.
7
6
5
4
3
2
1
0
—
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x75—DFE Write Tap Select Register (dfe_tap_select_write)
A 7-bit read/write register representing an unsigned binary address defined over a range of 0 to 115 decimal.
When written, this register causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0];
0x7C–0x7F] to be subsequently written to the selected DFE coefficient within 2 symbol periods. Does not
affect the value of the access data register.
7
6
5
4
3
2
1
0
—
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
3-30
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x76—Scratch Pad Read Tap Select (sp_tap_select_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal.
When written, this register causes the selected 8-bit scratch pad memory location to be subsequently loaded into
the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within 2 symbol periods.
Does not affect the value of the memory. No other data access should occur between the time the Read Tap
Select Register is written and the time the Access Data Register is read, or the data may be corrupted.
7
6
5
4
3
2
1
0
—
—
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x77—Scratch Pad Write Tap Select (sp_tap_select_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal.
When written, this register causes the lowest-order 8 bits of the Access Data Register [access_data_byte[3:0];
0x7C–0x7F] to be subsequently written to the selected scratch pad memory location within 2 symbol periods.
Does not affect the value of the access data register.
7
6
5
4
3
2
1
0
—
—
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
N8973DSD
Conexant
Preliminary Information
3-31
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
0x78—Equalizer Read Select Register (eq_add_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimal.
When written, this register causes the selected 16-bit location of the equalizer register file to be subsequently
loaded into the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within
2 symbol periods. Does not affect the value of the register file location. An address map of the shared register
file, as defined by the factory-delivered microcode, is displayed in Table 3-2. No other data access should occur
between the time the Read Tap Select Register is written and the time the Access Data Register is read, or the
data may be corrupted.
7
6
5
4
3
2
1
0
—
—
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Table 3-2. Address Map of Shared Register Fill
D[5:0]
Stored Parameter
Decimal
Binary
0–7
8–15
16–20
21–25
26
00 0000–00 0111
00 1000–00 1111
01 0000–01 0100
01 0101–01 1001
01 1010
FFE Coefficients 0–7
FFE Data Taps 0–7
EP Coefficients 0–4
EP Data Taps 0–4
DAGC Gain—Least-Significant Word
DAGC Gain—Most-Significant Word
DAGC Output
27
01 1011
28
01 1100
29
01 1101
FFE Output
30
01 1110
DAGC Input
31
01 1111
FFE Output, Delayed 1 Symbol Period
DAGC Error Signal
32
10 0000
33
10 0001
Equalizer Error Signal
Slicer Error Signal
34
10 0010
35–47
10 0011–10 1111
Reserved
3-32
Conexant
Preliminary Information
N8973DSD
RS8973
3.0 Registers
Single-Chip SDSL/HDSL Transceiver
3.3 Register Description
0x79—Equalizer Write Select Register (eq_add_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimal.
When written, this register causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0];
0x7C–0x7F] to be subsequently written to the selected equalizer register file location within 2 symbol periods.
Does not affect the value of the access data register. An address map of the shared register file, as defined by the
factory-delivered microcode, is displayed in Table 3-2, Address Map of Shared Register Fill.
7
6
5
4
3
2
1
0
—
—
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x7A—Equalizer Microcode Read Select Register (eq_microcode_add_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal.
When written, this register causes the selected 32-bit location of the equalizer microprogram store to be
subsequently loaded into the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within 2 symbol
periods. Does not affect the value of the microprogram store location. No other data access should occur
between the time the Read Tap Select Register is written and the time the Access Data Register is read, or the
data may be corrupted.
7
6
5
4
3
2
1
0
—
—
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x7B—Equalizer Microcode Write Select Register (eq_microcode_add_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal.
When written, this register causes all 32 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F]
to be subsequently written to the selected equalizer microprogram store location within 2 symbol periods. Does
not affect the value of the access data register. A factory-developed equalizer microcode is included with the
no-fee licensed HDSL transceiver software available from Conexant.
7
6
5
4
3
2
1
0
—
—
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0x7C–0x7F—Access Data Register (access_data_byte3:0)
A 4-byte read/write register that stores filter coefficient, equalizer register file, and equalizer microprogram
store contents during indirect accesses to these RAM-based locations. Writes to addresses 0x70 through 0x7B,
and uses the contents of this shared register as specified in each of the individual register descriptions.
N8973DSD
Conexant
Preliminary Information
3-33
3.0 Registers
RS8973
3.3 Register Description
Single-Chip SDSL/HDSL Transceiver
3-34
Conexant
Preliminary Information
N8973DSD
4
4.0 Interconnection Information
NOTE: This section replaces the RS8973 Application Note (N8973AN1A).
The configuration described in this section supports data rates ranging from
144 kbps and 2320 kbps, with the output signal conforming to ETS TS 101 135
(formerly ETR 152) specifications for pulse-shape, power spectral density and
output power at 784 kbps, 1168 kbps, and 2320 kbps.
Four types of interconnections are discussed:
1. Transmission line interface, including the compromise hybrid
2. DC blocking capacitor
3. Voltage reference and compensation circuitry
4. Crystal/clock interface
N8973DSD
Conexant
Preliminary Information
4-1
4.0 Interconnection Information
4.1 Transmission Line Interface
RS8973
Single-Chip SDSL/HDSL Transceiver
4.1 Transmission Line Interface
The transmission line interface consists of the compromise hybrid, two
impedance matching resistors and the line transformer. Figure 4-1, Line Interface
Interconnection Diagram, illustrates the interconnections.
Figure 4-1. Line Interface Interconnection Diagram
Antialiasing Filter
R7
RXP (77)
C5
R8
Line
RXN (78)
Transformer
L
1:2
15.4 Ω
Surge
TXP (71)
Protection
Line
Surge
Protection
Matching
Resistors
C10
15.4 Ω
Surge
Protection
TXN (74)
Secondary
Primary
Compromise Hybrid Circuit
R1
Antialiasing Filter
C1
R9
R11
RXBP (79)
R2
C2
C6
R10
R5
R6
RXBN (80)
C3
R3
C4
R4
R12
8973_038
4-2
Conexant
Preliminary Information
N8973DSD
RS8973
4.0 Interconnection Information
4.1 Transmission Line Interface
Single-Chip SDSL/HDSL Transceiver
4.1.1 Compromise Hybrid
The purpose of the compromise hybrid is to model the impedance of the
transmission line. This model generates an approximation of the transmitted
signal’s echo. The echo replica is then subtracted from the signal on the line
transformer to generate a first order approximation of the received signal. The
RS8973 includes a dual differential analog input to accommodate a hybrid using
only passive components.
Hybrid component values have been determined by means of calculations and
simulations that optimize the echo cancellation functions at the frequencies of
interest for the loops as specified in the ETS TS 101 135 (formerly ETR 152)
standards. In addition, maximum reach was taken into consideration for the
hybrid design.
To maximize digital echo cancellation within the RS8973, it is important that
the compromise hybrid transfer function be highly linear. Therefore, we
recommend that all capacitors used in the hybrid be NPO ceramic capacitors
because of their highly linear characteristics.
Although the RS8973 contains a digital echo canceller (EC), the hybrid is
needed to reduce the signal level input to the ADC. This eliminates ADC
overflow for short loops and increases the resolution of the digitized receive
signal for better digital signal processing performance. In addition, because the
digital EC cannot cancel out very low frequency signals, it is very important that
the analog EC cancel out most of the low frequency echo.
Table 4-1 lists compromise hybrid component values.
Table 4-1. Compromise Hybrid Component Values
Hybrid Components
Value
R1, R4
C1, C4
1.58 kΩ
2.3 nF
2.0 kΩ
1 nF
R2, R3
C2, C3
R5, R6
R11, R12
6.04 kΩ
5.1 kΩ
NOTE: All capacitors in the signal path should be film or NPO ceramic capacitors.
N8973DSD
Conexant
Preliminary Information
4-3
4.0 Interconnection Information
4.1 Transmission Line Interface
RS8973
Single-Chip SDSL/HDSL Transceiver
4.1.2 Impedance-Matching Resistors
Impedance-matching resistors are placed in the transmit path so that the
output impedance of the line interface more closely matches the impedance of the
transmission line and load. This maximizes the power transferred to the receiver
on the other end of the line. The load is assumed to be 135 Ω.
Anti-aliasing filters are built on-chip to filter out high frequencies that would
be aliased back into the passband as noise. These filters can be made of all
passive components. The cutoff frequency (fc) should be as low as possible to
achieve maximum attenuation of aliasing frequencies without filtering out the
desired signal. Because the highest frequency in the desired signal is equal to
one-half of the symbol rate, there should be no more than 1 dB of attenuation at
this frequency. Table 4-2 lists the component values recommended for the
antialiasing filters. Note that the other components in the hybrid affect the
frequency response of the antialiasing filters.
Table 4-2. Antialias Filter Component Values
Antialias Filter Components
Value
R7, R8
C5
1 kΩ
56pF
1 kΩ
56 pF
R9, R10
C6
4.1.3 Line Transformer
The line transformer provides DC isolation from the transmission line by
creating a high-pass filter. The winding ratio of the transformer must be 2:1 (line
side:circuit side) to generate the appropriate voltage level on the line. The primary
inductance (L) of the transformer (line side) is a very critical parameter. If L is
too high, the cutoff frequency of the filter will be too low and the RS8973 Echo
Canceller and Equalizer will not be able to cancel out the low frequency
components of the echo and inter-symbol interference. If L is too low, part of the
information in the signal will be filtered out, thereby decreasing the SNR ratio. In
addition, the line transformer must meet other requirements to maximize system
performance. See Table 4-3 for line transformer requirements.
Table 4-4 lists additional requirements that may be needed to specify the line
transformer, depending upon the application in which it is to be used. These
requirements have been submitted to several transformer vendors to expedite the
development process. A list of these transformer vendors along with their
associated transformer part numbers is listed in Table 4-5. These requirements
may need to be modified to match the needs of a specific system. For example, if
remote line powering is being used, the transformer must operate under a fairly
high DC current condition. The exact current specification will depend on several
factors including the voltage provided over the line, and the power consumption at
the remote end. The application-specific requirements should be reviewed to
ensure the transformer is not under- or over-specified. An over-specified
transformer may unnecessarily increase cost, while an under-specified
transformer may not perform adequately under all system conditions.
4-4
Conexant
Preliminary Information
N8973DSD
RS8973
4.0 Interconnection Information
4.1 Transmission Line Interface
Single-Chip SDSL/HDSL Transceiver
Table 4-3. Line Transformer Specifications
Parameter
Value
(1)
2:1 (±2%)
Turns Ratio
(2)
2 mH (±10%)
Primary Inductance
Return Loss (mid-band)
Return Loss (low-band)
Return Loss (high-band)
Longitudinal Balance (low-band)
Longitudinal Balance (high band)
Insertion Loss
16 dB (40 to 300 kHz)
–20 dB/decade (below 40 kHz)
–20 dB/decade (above 300 kHz)
53 dB (0.5 to 300 kHz)
–20 dB/decade (above 300 kHz)
0.5 dB at 40 kHz
Frequency Response
±0.1 dB
(36 to 580 kHz)
(3)
–70 dB at 36 kHz
Total Harmonic Distortion
NOTE(S):
(1)
Turns ratio is specified line side to circuit side (line side:circuit side). The line side windings are usually split to accommodate
a DC blocking capacitor.
The primary inductance is for the line side of the transformer.
(2)
(3)
Test condition: 14 dBm on line side (135 Ω load) with DC current present (if applicable).
Table 4-4. Line Transformer Application-Specific Specifications
Parameter
Requirement
Operating Temperature Range
DC Current
–40 °C to +85 °C
60 mA
Dielectric Strength
1500 VDC / 3000 VAC
—
Creepage and Clearance
Table 4-5. Recommended Line Transformer Suppliers
Supplier Phone
Supplier Name and Address
Number(s)
Part Number
Midcom, Inc.
50050
P.O. Box 1330
Watertown, SD 57201
(800) 643-2661
(605) 886-4385
Pulse Engineering
Application Engineering
1220 World Trade Dr.
San Diego, CA 92128
(619) 674-8100
—
Schott Corporation
1000 Parkers Lake Rd
Minneapolis, MN 55391
(612) 475-1173
—
N8973DSD
Conexant
Preliminary Information
4-5
4.0 Interconnection Information
4.2 DC Blocking Capacitor
RS8973
Single-Chip SDSL/HDSL Transceiver
4.2 DC Blocking Capacitor
A DC blocking capacitor is placed in series with the center split primary winding
(line side) of the line transformer to facilitate remote power feed or injection of
sealing current. See Table 4-6.
Table 4-6. DC Blocking Capacitor Value
Component
Value
C10
1 µF
4.3 Voltage Reference and Compensation
Circuitry
Compensation capacitors must be connected between all of the RS8973 voltage
reference pins and analog ground. The voltage reference signals, their associated
pin numbers, and the recommended compensation capacitor values are listed in
Table 4-7.
Table 4-7. Compensation Capacitor Values
Signal Name
Pin Number
Capacitor Value
VCOMO
VCOMI
VCCAP
VRXP
58
57
59
51
52
60
61
0.22 µF
0.22 µF
0.22 µF
0.22 µF
0.22 µF
0.22 µF
0.22 µF
VRXN
VTXP
VTXN
In addition to the compensation capacitors, an external resistor is needed to set
the bias current used in the RS8973. This resistor must be connected between the
RBIAS pin (pin 56) and analog ground. The recommended value of the resistor is
given in Table 4-8.
Table 4-8. Bias Current Resistor Value
Signal Name
Pin Number
Resistor Value
RBIAS
56
9.53 kΩ
4-6
Conexant
Preliminary Information
N8973DSD
RS8973
4.0 Interconnection Information
4.4 Crystal/Clock Interface
Single-Chip SDSL/HDSL Transceiver
4.4 Crystal/Clock Interface
A crystal or an external clock is needed to provide a reference clock for the
RS8973. If a crystal is used, it must be connected to the XTALI/MCLK and
XTALO pins along with two external capacitors as shown in Figure 4-2. The
recommended specification for the crystal is given in Table 4-9. A list of crystal
vendors and their associated part numbers is displayed in Table 4-10.
If an external clock is used, it must be connected to the XTALI/MCLK pin
(pin 40), and the XTALO pin (pin 39) must be left floating. The clock frequency
must be 10.24 MHz.
Figure 4-2. Crystal Oscillator Connection Diagram
XTALI / MCLK (40)
XTALO (39)
Y1
22 pF
22 pF
Table 4-9. Crystal Specification
Parameter
Nominal Frequency
Value
10.24 MHz
±10 ppm
±10 ppm
Frequency Tolerance at 25 °C
Temperature Frequency Stability
Aging
±10 ppm over 10 years
15.5 pF
Load Capacitance
NOTE(S): Individual frequency tolerance, temperature frequency stability, and aging
requirements can vary as long as the total tolerance is less than ±30 ppm.
Table 4-10. Recommended Crystal Suppliers
Supplier Phone
Supplier Name and Address
Part Number
Number
Ecliptek Corporation
3545 Cadillac Avenue
Costa Mesa, CA 92626
ECX-5173-10.240M
(714) 433-1200
General Electronic Devices
320 S. Pacific Street
HC49-10.240- .0155- .001/01
(760) 591-4170
San Marcos, CA 92069
N8973DSD
Conexant
Preliminary Information
4-7
4.0 Interconnection Information
4.4 Crystal/Clock Interface
RS8973
Single-Chip SDSL/HDSL Transceiver
4-8
Conexant
Preliminary Information
N8973DSD
5
5.0 Electrical and Mechanical Specifications
5.1 Absolute Maximum Ratings
Stresses above those listed in Table 5-1 may cause permanent damage to the
device. This is a stress rating only. Functional operation of the device at these or
any other conditions beyond those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5-1. Absolute Maximum Ratings
Symbol
Parameter
Minimum
–0.5
Maximum
Units
V
Supply voltage(1)–VDD2, VPLL, VAA
Supply voltage(1)–VDD1
V
+7
Supply
V
–0.5
4.6
V
Supply
Input voltage on any signal pin(2)
Storage temperature
V
–0.5
V
+ 0.5
V
I
DD2
T
–65
+125
+220
°C
°C
ST
T
Vapor-phase soldering temperature (1 minute)
—
VSOL
NOTE(S):
(1) V , V , relative to DGND. V relative to AGND.
DD1 DD2
AA
(2) Relative to DGND.
N8973DSD
Conexant
Preliminary Information
5-1
5.0 Electrical and Mechanical Specifications
5.2 Recommended Operating Conditions
RS8973
Single-Chip SDSL/HDSL Transceiver
5.2 Recommended Operating Conditions
The recommended operating conditions are described in Table 5-2.
Table 5-2. Recommended Operating Conditions
Symbol
Parameter
Digital core-logic supply voltage
Digital I/O-buffer supply voltage
Analog supply voltage
Minimum
3.0
Typical
3.3
5.0
5.0
5.0
—
Maximum Units
V
3.6
V
V
DD1
V
4.75
5.25
5.25
5.25
DD2
V
4.75
V
AA
V
PLL supply voltage
4.75
V
PLL
IH
High-level input voltage (1)
Low-level input voltage
DD2
V
2.0
V
+ 0.3
V
V
–0.3
—
+0.8
+ 0.3
V
IL
V
High-level input voltage for XTALI / MCLK
Low-level input voltage for XTALI / MCLK
Output capacitive loading(2)
0.9 × V
—
V
V
IHX
DD2
DD2
V
–0.3
—
—
0.1 × V
V
ILX
DD2
C
—
60
pF
°C
L
Ambient operating temperature(3)
T
–40
—
+85
A
(1) V (minimum) for the following inputs is 2.2 volts:
IH
WR/R/W
RST
RBCLK
TBCLK
(2) Capacitive loading over which all digital output switching characteristics are guaranteed.
(3) Still-air temperature range over which all electrical characteristics and timing requirements/characteristics are guaranteed.
5-2
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.3 Electrical Characteristics
Single-Chip SDSL/HDSL Transceiver
5.3 Electrical Characteristics
Typical characteristics measured at nominal operating conditions:
•
•
•
T = 25 °C
A
V
V
= 3.3 V
DD1
DD2/AA/PLL
= 5.0 V
Minimum/maximum characteristics guaranteed over extreme operating
conditions:
•
•
Min ≤ T ≤ max
A
Min ≤ V
≤ max
DD/AA
The parameters of the electrical characteristics are displayed in Table 5-3.
N8973DSD
Conexant
Preliminary Information
5-3
5.0 Electrical and Mechanical Specifications
5.3 Electrical Characteristics
RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-3. Electrical Characteristics
Symbol
Parameter
High-Level Output Voltage @ I = – 400 µA
Minimum
2.4
—
Typical
—
Maximum Units
V
—
0.4
V
OH
OH
V
Low-Level Output Voltage @ I = 6 mA (IRQ and READY)
—
V
OLL
OL
V
Low-Level Output Voltage @ I = 3 mA (All Other Outputs)
—
—
0.4
V
OL
OL
I
Input Leakage Current @ V ≤ V ≤ V
DD2
—
—
±10
±10
–400
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
10
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
pF
I
SS2
I
I
High-Impedance Output Leakage Current @ V ≤ V ≤ V
—
—
OZ
SS2
O
DD2
I
Resistive Pull-Up Current @ V = V (TDI and TMS)
–20
—
—
PR
I
SS2
5 V Supply Current @ F
= 72 kHz(1)
I
100
101
102
103
105
25
5V
QCLK
5 V Supply Current @ F
= 392 kHz(1)
= 584 kHz(1)
= 776 kHz(1)
= 1160 kHz(1)
= 72 kHz(2)
I
—
5V
QCLK
I
—
5 V Supply Current @ F
5V
QCLK
I
—
5 V Supply Current @ F
5V
QCLK
I
—
5 V Supply Current @ F
5V
QCLK
I
—
3.3 V Supply Current @ F
3.3 V Supply Current @ F
3V
QCLK
= 392 kHz(2)
= 584 kHz(2)
= 776 kHz(2)
= 1160 kHz(2)
= 72 kHz(3)
I
—
54
3V
QCLK
I
—
70
3.3 V Supply Current @ F
3V
QCLK
I
—
87
3.3 V Supply Current @ F
3V
QCLK
I
—
120
15
3.3 V Supply Current @ F
3V
QCLK
I
—
Power-Down Current @ F
PD5V
QCLK
= 1160 kHz(3)
= 72 kHz(4)
I
—
18
Power-Down Current @ F
PD5V
QCLK
I
—
1
Power-Down Current @ F
PD3V
QCLK
= 1160 kHz(4)
I
—
1
Power-Down Current @ F
PD3V
QCLK
C
Input Capacitance
High-Impedance Output Capacitance
—
—
I
C
—
—
10
pF
OZ
NOTE(S):
(1) I = I + I
+ I during normal operation.
AA
5V PLL DD2
(2) I = I
during normal operation.
3V DD1
(3) I
= I + I
+ I during power-down operation.
PD5V PLL DD2 AA
(4) I
= I
during power-down operation.
PD3V DD1
5-4
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.4 Clock Timing
Single-Chip SDSL/HDSL Transceiver
5.4 Clock Timing
Tables 5-4 through 5-6 list the clock timing requirements and switching
characteristics. Figures 5-1 and 5-2 illustrate MCLK timing requirements and
clock control timing, respectively.
Table 5-4. MCLK Timing Requirements
Symbol
Parameter
Minimum
Typical
Maximum
Units
MCLK Period(1)
1
97.653
35
97.656
—
97.659
—
ns
ns
ns
2
3
MCLK Pulse-Width Low
MCLK Pulse-Width High
35
—
—
NOTE(S):
(1) If an external clock is applied to XTALI/MCLK, it is referred to as MCLK. Max tolerance = ± 32 ppm.
Edge rates for MCLK are < 5 ns.
Figure 5-1. MCLK Timing Requirements
1
2
3
MCLK
Table 5-5. HCLK Switching Characteristics
Symbol
Parameter
Minimum
Typical
÷ 64
Maximum
Units
—
(1)
4
T
÷ 64
÷ 16
÷ 32
T
T
QCLK
÷ 64
÷ 16
÷ 32
HCLK Period (T
), hclk_freq[1:0] = ‘11’
QCLK
QCLK
HCLK
(1)
5
T
T
÷16
T
QCLK
—
HCLK Period (T
HCLK Period (T
), hclk_freq[1:0] = ‘00’ or ‘01’
QCLK
QCLK
HCLK
(1)
6
T
T
÷ 32
T
QCLK
—
), hclk_freq[1:0] = ‘10’
QCLK
QCLK
HCLK
7
8
HCLK Pulse-Width High
HCLK Pulse-Width Low
T
÷ 2 – 10
÷ 2 – 10
T
÷ 2
÷ 2
T
÷ 2 + 10
T ÷ 2 + 10
HCLK
ns
HCLK
HCLK
HCLK
T
T
ns
HCLK
HCLK
NOTE(S):
(1) The hclk_freq[1:0] control bits are located in the Serial Monitor Source Select Register [addr. 0x01].
N8973DSD
Conexant
Preliminary Information
5-5
5.0 Electrical and Mechanical Specifications
5.4 Clock Timing
RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-6. QCLK Switching Characteristics
Symbol
Parameter
Minimum
Maximum
Units
(1)
9
—
—
QCLK period (T
)
QCLK
10
11
QCLK pulse-width high
QCLK pulse-width low
T
÷ 2 – 20
T
÷ 2 + 20
÷ 2 + 20
ns
ns
QCLK
QCLK
T
÷ 2 – 20
T
QCLK
QCLK
12
13
QCLK hold after HCLK rising edge
QCLK delay after HCLK high
–20
—
ns
ns
20
NOTE(S):
(1) T
is defined as the time period of the symbol rate. The symbol rate is data rate ÷ 2.
QCLK
Figure 5-2. Clock Control Timing
4,5,6
7
HCLK
8
9
13
10
12
QCLK
11
5-6
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.5 Channel Unit Interface Timing
Single-Chip SDSL/HDSL Transceiver
5.5 Channel Unit Interface Timing
Tables 5-7 through 5-12 list channel unit interface timing requirements and
switching characteristics. Figures 5-3 through 5-5 illustrate channel unit interface
timing in parallel master mode, parallel slave mode, and serial mode, respectively.
Table 5-7. Channel Unit Interface Timing Requirements, Parallel Master Mode
Symbol
Parameter
Minimum
Maximum Units
14
15
TQ[1,0] setup prior to QCLK falling edge
TQ[1,0] hold after QCLK low
100
25
—
—
ns
ns
Table 5-8. Channel Unit Interface Switching Characteristics, Parallel Master Mode
Symbol
Parameter
Minimum
Maximum Units
16
17
RQ[1,0] hold after QCLK rising edge
RQ[1,0] delay after QCLK high
–50
—
—
50
ns
ns
Figure 5-3. Channel Unit Interface Timing, Parallel Master Mode
RQ[1,0]
16
17
QCLK
14
15
TQ[1,0]
N8973DSD
Conexant
Preliminary Information
5-7
5.0 Electrical and Mechanical Specifications
5.5 Channel Unit Interface Timing
RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-9. Channel Unit Interface Timing Requirements, Parallel Slave Mode
Symbol
Parameter
Minimum
Maximum Units
TBCLK, RBCLK Period(1)
18
19
T
T
—
—
—
ns
ns
QCLK
QCLK
TBCLK, RBCLK Pulse-Width High
TBCLK, RBCLK Pulse-Width Low
T
÷ 4
÷ 4
—
—
—
—
QCLK
20
T
QCLK
TQ[1,0] Setup prior to TBCLK Active Edge(2)
TQ[1,0] Hold after TBCLK High/Low(2)
21
25
25
22
NOTE(S):
(1) TBCLK and RBCLK must be frequency-locked to QCLK, though they may have independent phase relationships to QCLK and to
one another.
(2) TBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes 0x06].
Table 5-10. Channel Unit Interface Switching Characteristics, Parallel Slave Mode
Symbol
Parameter
RQ[1,0] hold after RBCLK active edge(1)
RQ[1,0] delay after RBCLK high/low(1)
Minimum
Maximum Units
23
24
0
—
ns
ns
—
100
NOTE(S):
(1) RBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes; 0x06].
Figure 5-4. Channel Unit Interface Timing, Parallel Slave Mode
18
RBCLK
19
20
24
23
RQ[1:0]
TBCLK
18
19
20
22
21
TQ[1:0]
5-8
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.5 Channel Unit Interface Timing
Single-Chip SDSL/HDSL Transceiver
Figure 5-4. Channel Unit Interface Timing, Parallel Slave Mode
NOTE(S): TBCLK and RBCLK polarities are programmable through the CU Interface Modes Register. The figure depicts both
clocks programmed to falling-edge active.
Table 5-11. Channel Unit Interface Timing Requirements, Serial Mode
Symbol
Parameter
Minimum
Maximum Units
25
26
TDAT setup prior to BCLK falling edge
TDAT hold after BCLK low
100
25
—
—
ns
ns
Table 5-12. Channel Unit Interface Switching Characteristics, Serial Mode
Symbol
27
Parameter
Minimum
÷ 2
Maximum
Units
—
BCLK period
T
T
÷ 2
QCLK
QCLK
28
BCLK pulse-width high
BCLK pulse-width low
T
÷ 4 – 20
÷ 4 – 20
T
÷ 4 + 20
÷ 4 + 20
QCLK
ns
QCLK
QCLK
29
T
T
ns
QCLK
30
31
32
33
BCLK hold after HCLK rising edge
BCLK delay after HCLK high
0
—
50
—
50
ns
ns
ns
ns
—
RDAT, QCLK hold after BCLK rising edge
RDAT, QCLK delay after BCLK high
–50
—
N8973DSD
Conexant
Preliminary Information
5-9
5.0 Electrical and Mechanical Specifications
5.5 Channel Unit Interface Timing
RS8973
Single-Chip SDSL/HDSL Transceiver
Figure 5-5. Channel Unit Interface Timing, Serial Mode
HCLK
27
31
28
30
BCLK
29
33
32
QCLK
RDAT
26
25
TDAT
5-10
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.6 Microcomputer Interface Timing
Single-Chip SDSL/HDSL Transceiver
5.6 Microcomputer Interface Timing
Tables 5-13 and 5-14 list microcomputer interface (MCI) timing requirements
and switching characteristics, respectively. Figures 5-6 through 5-9 illustrate MCI
write and read timing. Figure 5-10 illustrates internal write timing.
Table 5-13. Microcomputer Interface Timing Requirements
Symbol
Parameter
Minimum
Maximum
Units
34
35
ALE pulse-width high
30
10
—
—
ns
ns
Address setup prior to ALE falling edge(1)
Address hold after ALE low(1)
36
37
5
—
—
—
ns
ns
ns
ALE low prior to Write Strobe falling edge(2)
20
20
38a
Read Strobe falling edge after ALE falling edge – muxed mode
(3)
(MUXED = 1)
38b
Read Strobe falling edge after ALE falling edge – non-muxed mode
1
—
ns
(3)
(MUXED = 0)
Write Strobe pulse-width low(2,4)
39
40
41
42
T
÷ 32 + 25
—
—
—
—
ns
ns
ns
ns
QCLK
Read Strobe pulse-width low(3,4)
T
÷ 32 + 25
QCLK
Data In setup prior to Write Strobe rising edge(2)
30
5
Data In hold after Write Strobe high(2)
R/W setup prior to Read/Write Strobe falling edge
R/W hold after Read/Write Strobe high
ALE falling edge after Write Strobe high
ALE falling edge after Read Strobe high
RST pulse-width low
43
44
10
10
20
20
50
0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
45
46
47
48
Write Strobe rising edge after READY low
NOTE(S):
(1) Address is defined as AD[7:0] when MUXED = 1, and ADDR[7:0] when MUXED = 0.
(2) In Intel mode, Write Strobe is defined as WR and CS asserted. In Motorola mode, it is defined as DS and CS asserted when R/W
is low.
(3) In Intel mode, Read Strobe is defined as RD and CS asserted. In Motorola mode, it is defined as DS and CS asserted when R/W
is high.
(4) The timing listed is for the synchronous mode of the MCI, which is power-on default. It can also be set to asynchronous mode
by setting bit 0 of the miscellaneous/test register (address 0x0F) to a 1. In this case, the minimum timing changes to 40 ns for
symbol 39, and 50 ns for symbols 40 and 50. Synchronous mode is preferred because it reduces switching noise. To switch to
asynchronous mode, the Write Strobe pulse-width (symbol 39) should meet the synchronous mode timing requirements for a
symbol rate of 640 kbps (74 nx), which is the power-on default.
N8973DSD
Conexant
Preliminary Information
5-11
5.0 Electrical and Mechanical Specifications
5.6 Microcomputer Interface Timing
RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-14. Microcomputer Interface Switching Characteristics
Symbol
Parameter
Minimum
Maximum
Units
Data out enable (Low Z) after Read Strobe falling edge(1)
Data out valid after Read Strobe low(1, 7)
49
50
51
52
53
54
55
56
57
58
2
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
T
÷ 32 + 25
QCLK
Data out hold after Read Strobe rising edge(1)
Data out disable (High Z) after Read Strobe high(1)
IRQ hold after Write Strobe rising edge(2,3)
IRQ delay after Write Strobe high(2,3)
—
—
5
25
—
—
—
—
—
0
T
÷ 32 + 20
÷ 32
QCLK
Internal register delay after Write Strobe high(3,4)
Internal RAM delay after Write Strobe high(3,5)
Access data register delay after Write Strobe high(3,6)
T
QCLK
2 × T
QCLK
2 × T
QCLK
(3)
T
÷ 32
QCLK
READY low after Write Strobe low
(3)
59
60
61
0
0
50
÷ 32
ns
ns
ns
ns
READY rising edge after Write Strobe high
(1)
T
QCLK
READY low after Read Strobe low
(1)
0
50
10
READY rising edge after Read Strobe high
62
Data out valid after READY low
—
NOTE(S):
(1) Read Strobe is defined as RD and CS asserted in Intel mode, and DS and CS asserted when R/W is high in Motorola mode.
(2) When writing an interrupt mask or status register.
(3) Write Strobe is defined as WR and CS asserted in Intel mode, and DS and CS asserted when R/W is low in Motorola mode.
(4) Writes to internal registers are synchronized to an internal 64-times symbol-rate clock. Data is available for reading after the
specified time. This parameter may extend the overall read access time from internal register locations under high bus
speed/low symbol rate conditions.
(5) When performing an indirect write to RAM-based locations using a write select register [odd addresses: 0x71–0x7B] and the
Access Data Register. Subsequent writes to any read/write select register or the Access Data Register, as initiated by a Write
Strobe falling edge, is prohibited for the specified time. This parameter will extend the overall write access time to RAM-based
locations under normal bus speed/symbol rate conditions.
(6) When performing an indirect read from RAM-based locations using a read select register [even addresses: 0x70–0x7A] and the
Access Data Register. Subsequent writes to any read/write select register, as initiated by a Write Strobe falling-edge, is
prohibited for the specified time. Data is available for reading from the Access Data Register after the specified time. This
parameter will extend the overall read access time from RAM-based locations under normal bus speed/symbol rate conditions.
Direct writes to the Access Data Register are as specified for internal registers.
(7) The timing listed is for the synchronous mode of the MCI, which is power-on default. It can also be set to asynchronous mode
by setting bit 0 of the reserved9 register (address 0x0F) to a 1. In this case, the minimum timing changes to 40 ns for symbol
39, and 50 ns for symbols 40 and 50. Synchronous mode is preferred because it reduces switching noise. To switch to
asynchronous mode, the Write Strobe pulse-width (symbol 39) should meet the synchronous mode timing requirements for a
symbol rate of 640 kbps (74 nx), which is the power-on default.
5-12
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.6 Microcomputer Interface Timing
Single-Chip SDSL/HDSL Transceiver
Figure 5-6. MCI Write Timing, Intel Mode (MOTEL = 0)
AD[7:0]
Address
35
Data (Input)
41
or
ADDR[7:0]
42
36
Write
Strobe
37
39
45
34
48
ALE
59
58
READY
N8973DSD
Conexant
Preliminary Information
5-13
5.0 Electrical and Mechanical Specifications
5.6 Microcomputer Interface Timing
RS8973
Single-Chip SDSL/HDSL Transceiver
Figure 5-7. MCI Write Timing, Motorola Mode (MOTEL = 1)
AD[7:0]
or
Address
35
Data (Input)
41
ADDR[7:0]
42
36
Write
Strobe
37
39
48
R/W
43
44
45
34
58
ALE
59
READY
Figure 5-8. MCI Read Timing, Intel Mode (MOTEL = 0)
AD[7:0]
Address
35
Data (Output)
or
ADDR[7:0]
51
36
49
52
38
50
Read
Strobe
62
40
46
34
ALE
60
61
READY
5-14
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.6 Microcomputer Interface Timing
Single-Chip SDSL/HDSL Transceiver
Figure 5-9. MCI Read Timing, Motorola Mode (MOTEL = 1)
AD[7:0]
Address
35
Data (Output)
or
ADDR[7:0]
49
51
36
52
50
38
Read
Strobe
62
40
43
44
R/W
46
34
ALE
61
60
READY
N8973DSD
Conexant
Preliminary Information
5-15
5.0 Electrical and Mechanical Specifications
5.6 Microcomputer Interface Timing
RS8973
Single-Chip SDSL/HDSL Transceiver
Figure 5-10. Internal Write Timing
Write
Strobe
54
53
IRQ
55
Internal
Register
56
57
Internal
RAM
Access
Data
Register
5-16
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.7 Test and Diagnostic Interface Timing
Single-Chip SDSL/HDSL Transceiver
5.7 Test and Diagnostic Interface Timing
Tables 5-15 and 5-16 list test and diagnostic interface timing requirements and
switching characteristics. Figures 5-11 and 5-12 illustrate JTAG interface and
SMON timing, respectively.
Table 5-15. Test and Diagnostic Interface Timing Requirements
Symbol
Parameter
Minimum
Maximum Units
63
64
TCK pulse-width high
TCK pulse-width low
80
80
20
20
—
—
—
—
ns
ns
ns
ns
TMS, TDI setup prior to TCK rising edge(1)
TMS, TDI hold after TCK high(1)
65
66
NOTE(S):
(1) Also applies to functional inputs for SAMPLE/PRELOAD and EXTEST instructions.
N8973DSD
Conexant
Preliminary Information
5-17
5.0 Electrical and Mechanical Specifications
5.7 Test and Diagnostic Interface Timing
RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-16. Test and Diagnostic Interface Switching Characteristics
Symbol
Parameter
Minimum
Maximum Units
TDO hold after TCK falling edge(1)
TDO delay after TCK low(1)
67
68
0
—
2
—
50
—
25
—
50
ns
ns
ns
ns
ns
ns
TDO enable (Low Z) after TCK falling edge(1)
TDO disable (High Z) after TCK low(1)
SMON hold after HCLK rising edge(2)
SMON delay after HCLK high(2)
69
70
—
0
71
72
—
NOTE(S):
(1) Also applies to functional outputs for the EXTEST instruction.
(2) HCLK must be programmed to operate at 16 times the symbol rate (16 × F
).
QCLK
Figure 5-11. JTAG Interface Timing
TDO
69
67
70
63
68
TCK
64
65
66
TDI
TMS
Figure 5-12. SMON Timing
HCLK
72
71
SMON
5-18
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.8 Analog Specifications
Single-Chip SDSL/HDSL Transceiver
5.8 Analog Specifications
Tables 5-17 and 5-18 list transmitter and receiver analog requirements and
specifications. Figure 5-13 and Table 5-19 show the transmit pulse template for
two- and three-pair systems. Figure 5-14 and Table 5-20 show the transmit pulse
template for one-pair systems. Figures 5-15 through 5-17 illustrate the upper
bound of the average PSD of 392, 584, and 1160 kbaud systems, respectively.
Table 5-17. Receiver Requirements and Specifications
Parameter
Unit
s
Comments
Min
Typ
Max
Input signals
Input voltage range
RXP, RXN, RXBP, and RXBN
With respect to VAA/2
@ Data Rate = 2320 kbps
@ Data Rate = 144 kbps
VCOMI
—
–2.25
—
—
—
—
+2.25
—
—
V
Input resistance
10
kΩ
kΩ
V
Input resistance
—
35
—
Common mode voltage
—
VAA × 0.4
—
—
VGA
Six gains from 0 dB to +15 dB
—
—
—
—
dB
—
Gain step
ADC
2.55
—
3.0
3.42
—
—
—
Differential voltage range
(full scale input, FS)(1)
(V – V )—(V
– V
)
5.4
6.0
6.6
V
P
RXP
RXN
RXBP
RXBN
Timing recovery PLL pull-in range (digital)
PLL settling time
—
±64
—
—
10
—
—
ppm
ms
—
NOTE(S):
(1) Corresponds to the voltages that produce a full scale reading from the ADC when the VGA gain equals O dB. The input
voltage range is reduced proportionally as VGA gain is increased.
Table 5-18. Transmitter Analog Requirements and Specifications (1 of 2)
Parameter
Transmit symbol rate (f
Pulse template(1, 2, 3)
Comments
QCLK frequency (data rate/2)
See Figure 5-13 and Figure 5-14,
Min
72
Typ
—
Max
1160
—
Units
)
kHz
—
qclk
—
—
R = 135 Ω
L
N8973DSD
Conexant
Preliminary Information
5-19
5.0 Electrical and Mechanical Specifications
5.8 Analog Specifications
RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-18. Transmitter Analog Requirements and Specifications (2 of 2)
Parameter
Comments
Min
Typ
Max
Units
Power spectral density(1, 2, 3,4)
See Figures 5-15, 5-16 and 5-17,
—
—
—
—
R = 135 Ω
L
Average power(1, 2, 3,4)
DC to 2 x F
setting
, R = 135 Ω, calibrated gain
13.4
—
14
dBm
QCLK
L
Gain adjustment step
Common-mode voltage
Output impedance(1)
NOTE(S):
Controlled by Transmit Gain Register [0x29]
—
—
—
0.20
VAA/2
—
—
—
2
dB
V
VCOMO
DC to 1 MHz
Ω
(1) Guaranteed by design and characterization.
(2) See Figure 5-18 of Section 5.9, Test Conditions, for the test circuit.
(3) Measured after the transmitter is calibrated by writing the value in the Transmitter Calibration Register [tx_calibrate; 0x28] to
the Transmitter Gain Register [tx_gain; 0x29].
(4) Measured with a pseudo-random code sequence of pulses.
Figure 5-13. Transmit Pulse Template for Two- and Three-Pair Systems; Normalized Pulse Mask
(Source ETSI TS 101 135 Formerly ETR 152)
– 0,4T 0,4T
B = 1,07
C = 1,00
D = 0,93
T = 2,55 µs at 784 kbps
T = 1,71 µs at 1168 kbps
– 1,2T
1,25T
E = 0,03
A = 0,01
F = – 0,01
A = 0,01
F = – 0,01
H = – 0,05
0
T
G = – 0,16
– 0,6T 0,5T
14T
50T
5-20
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.8 Analog Specifications
Single-Chip SDSL/HDSL Transceiver
Table 5-19. Transmit Pulse Template for Two- and Three-Pair Systems (Source ETSI TS 101 135 Formerly ETR 152)
Quaternary Symbols
Normalized Level
+ 3
+ 1
– 1
– 3
A
B
C
D
E
0.01
1.07
0.0264
2.8248
2.6400
2.4552
0.0792
–0.0264
–0.4224
–0.1320
0.0088
0.9416
0.8800
0.8184
0.0264
–0.0088
–0.1408
–0.0440
–0.0088
–0.9416
–0.8800
–0.8184
–0.0264
0.0088
–0.0264
–2.8248
–2.6400
–2.4552
–0.0792
0.0264
1.00
0.93
0.03
F
–0.01
–0.16
–0.05
G
H
0.1408
0.4224
0.0440
0.1320
N8973DSD
Conexant
Preliminary Information
5-21
5.0 Electrical and Mechanical Specifications
5.8 Analog Specifications
RS8973
Single-Chip SDSL/HDSL Transceiver
Figure 5-14. Transmit Pulse Template for One-Pair Systems (Source ETSI TS 101 135 Formerly ETR 152)
– 0,4T 0,4T
B = 1,07
C = 1,00
D = 0,93
T = 0,862 µs at 2320 kbps
– 1,2T
1,25T
E = 0,04
A = 0,01
A = 0,01
F = – 0,01
F = – 0,01
0
T
H = – 0,05
G = – 0,20
– 0,6T 0,5T
14T
50T
Table 5-20. Transmit Pulse Template for One-Pair Systems (Source ETSI TS 101 135 Formerly ETR 152)
Quaternary Symbols
Normalized Level
+ 3
+ 1
– 1
– 3
A
B
C
D
E
0.01
1.07
0.0250 V
2.6750 V
2.500 V
0.0083 V
0.8917 V
0.8333 V
0.7750 V
0.0333 V
–0.0083 V
–0.1667 V
–0.0417 V
–0.0083 V
–0.8917 V
–0.8333 V
–0.7750 V
–0.0333 V
0.0083 V
0.1667 V
0.0417 V
–0.0250 V
–2.6750 V
–2.5000 V
–2.3250 V
–0.1000 V
0.0250 V
0.5000 V
0.1250 V
1.00
0.93
2.3250 V
0.1000 V
–0.0250 V
–0.5000 V
–0.1250 V
0.04
F
–0.01
–0.20
–0.05
G
H
5-22
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.8 Analog Specifications
Single-Chip SDSL/HDSL Transceiver
Figure 5-15. Upper Bound of the Average PSD of a 392 kbaud System (Source ETSI TS 101 135 Formerly ETR 152)
dBm/Hz
– 20
– 37 dBm/Hz
– 40
– 60
– 80
– 100
Floor at – 117 dBm/Hz
– 120
Hz
1
e3
1
e4
1
e5
1,96
e5
1
e6
1,96
e6
4
e6
Figure 5-16. Upper Bound of the Average PSD of a 584 kbaud System (Source ETSI TS 101 135 Formerly ETR 152)
dBm/Hz
– 20
– 39 dBm/Hz
– 40
– 60
– 80
– 100
Floor at – 119 dBm/Hz
– 120
Hz
1
e3
1
e4
1
e5
2,92
e5
1
e6
2,92
4
e6 e6
N8973DSD
Conexant
Preliminary Information
5-23
5.0 Electrical and Mechanical Specifications
5.9 Test Conditions
RS8973
Single-Chip SDSL/HDSL Transceiver
Figure 5-17. Upper Bound of the Average PSD of a 1160 kbaud System (Source ETSI TS 101 135 Formerly ETR 152)
dBm/Hz
– 20
– 41,5 dBm/Hz
– 40
– 60
– 80
– 100
Floor at – 121,5 dBm/Hz
– 120
– 130
Hz
1
e3
1
e4
1
e5
4,85
e5
1
e6
4,85
1
e6 e7
5.9 Test Conditions
Figure 5-18 shows the transmitter test circuit. Figures 5-19 and 5-20 show the
standard output and open-drain output loads, respectively.
Figure 5-18. Transmitter Test Circuit
RS8973
15.4 Ω
15.4 Ω
1:2
TXP (71)
TXP (74)
+
–
+
+
Line
Transformer
Line
R
L
Driver
–
–
Primary
Inductance = 2mH
5-24
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.9 Test Conditions
Single-Chip SDSL/HDSL Transceiver
Figure 5-19. Standard Output Load (Totem Pole and Three-State Outputs)
IOL
From
RS8973
1.5 V
CL
IOH
Figure 5-20. Open-Drain Output Load (IRQ)
IOD
From
RS8973
VDD2
CL
N8973DSD
Conexant
Preliminary Information
5-25
5.0 Electrical and Mechanical Specifications
5.10 Timing Measurements
RS8973
Single-Chip SDSL/HDSL Transceiver
5.10 Timing Measurements
Figure 5-21 shows the input waveforms. Figures 5-22 and 5-23 show the output
waveforms.
Figure 5-21. Input Waveforms for Timing Tests
3 V
2.0 V
0.8 V
0 V
Input
High
Input
Low
Input
Low
Input
High
Figure 5-22. Output Waveforms for Timing Tests
≈ VDD
2.4 V
0.4 V
≈ 0 V
Output
High
Output
Low
Output
Low
Output
High
5-26
Conexant
Preliminary Information
N8973DSD
RS8973
5.0 Electrical and Mechanical Specifications
5.10 Timing Measurements
Single-Chip SDSL/HDSL Transceiver
Figure 5-23. Output Waveforms for Three-state Enable and Disable Tests
VOH – 0.2 V
1.7 V
1.5 V
1.3 V
VOL + 0.2 V
Output
Output
Output
Disabled
Disabled
Enabled
N8973DSD
Conexant
Preliminary Information
5-27
5.0 Electrical and Mechanical Specifications
5.11 Mechanical Specifications
RS8973
Single-Chip SDSL/HDSL Transceiver
5.11 Mechanical Specifications
Figure 5-24. 100-Pin PQFP
TOP VIEW
BOTTOM VIEW
D
D1
b
e
E
E1
A
S
Y
M
B
O
L
ALL DIMENSIONS IN
MILLIMETERS
MIN. NOM. MAX.
A
A
----
3.04
3.40
----
0.25 0.33
2.57 2.71
1
A
2.87
2
D
D
E
E
23.20 BSC.
A2
20.00 BSC.
17.20 BSC.
14.00 BSC.
1
1
L
e
b
0.65 0.70
0.95
0.38
0.65 BSC.
----
0.22
L
A1
1.60
(.063)
REF.
5-28
Conexant
Preliminary Information
N8973DSD
A
Appendix A: Acronym List
The following list of acronyms and abbreviations does not include all signal,
register, and bit names.
A
ADC
AGC
analog-to-digital converter
automatic gain control
B
BDSL
BER
2B1Q
Boundary Scan Description Language
bit error rate
Two binary, one quaternary encoding/decoding
scheme
C
COT
CT
central office terminal
continuous time
D
DAC
DAGC
DFE
DSP
digital-to-analog converter
digital automatic gain control
decision feedback equalizer
digital signal processor
E
EC
EP
echo canceller
error predictor
ETSI
European Telecommunications Standard Institute
F
FELM
FFE
FIR
Far-end Level Meter
feed forward equalizer
finite impulse response
H
HDSL
High-bit-rate Digital Subscriber Line
I
IC
IS
integrated circuit
impulse shortening
N8973DSD
Conexant
Preliminary Information
A-1
Appendix A : Acronym List
RS8973
Single-Chip SDSL/HDSL Transceiver
J
JTAG
L
Joint Test Action Group
LEC
LMS
LSB
Linear Echo Canceller
least mean square
least significant bit
M
MCI
MSB
microcomputer interface
most significant bit
N
NEC
nonlinear echo canceller
P
PCB
PKD
PLL
PQFP
PSD
printed circuit board
Peak Detector
phase lock loop
plastic quad flat pack
power spectral density
Q
quat
quaternary
R
RT
remote terminal
S
SDSL
SLM
SMON
SNR
Symmetric Digital Subscriber Line over Single Pair
Signal Level Meter
serial monitor
signal-to-noise ratio
T
TAP
TCK
TMS
test access port
test clock
test mode select
V
VGA
variable gain amplifier
crystal oscillator
X
XO
A-2
Conexant
Preliminary Information
N8973DSD
0.0 Sales Offices
Further Information
Hong Kong
literature@conexant.com
1-800-854-8099 (North America)
33-14-906-3980 (International)
Phone: (852) 2827 0181
Fax: (852) 2827 6488
India
Web Site
Phone: (91 11) 692 4780
www.conexant.com
Fax: (91 11) 692 4712
Korea
Phone: (82 2) 565 2880
Fax: (82 2) 565 1440
World Headquarters
Conexant Systems, Inc.
4311 Jamboree Road
P. O. Box C
Phone: (82 53) 745 2880
Fax: (82 53) 745 1440
Newport Beach, CA
92658-8902
Phone: (949) 483-4600
Fax: (949) 483-6375
Europe Headquarters
Conexant Systems France
Les Taissounieres B1
1681 Route des Dolines
BP 283
U.S. Florida/South America
Phone: (727) 799-8406
Fax: (727) 799-8306
06905 Sophia Antipolis Cedex
FRANCE
Phone: (33 4) 93 00 33 35
Fax: (33 4) 93 00 33 03
U.S. Los Angeles
Phone: (805) 376-0559
Fax: (805) 376-8180
Europe Central
Phone: (49 89) 829 1320
Fax: (49 89) 834 2734
U.S. Mid-Atlantic
Phone: (215) 244-6784
Fax: (215) 244-9292
Europe Mediterranean
Phone: (39 02) 9317 9911
Fax: (39 02) 9317 9913
U.S. North Central
Phone: (630) 773-3454
Fax: (630) 773-3907
Europe North
Phone: (44 1344) 486 444
Fax: (44 1344) 486 555
U.S. Northeast
Phone: (978) 692-7660
Fax: (978) 692-8185
Europe South
Phone: (33 1) 41 44 36 50
Fax: (33 1) 41 44 36 90
U.S. Northwest/Pacific West
Phone: (408) 249-9696
Fax: (408) 249-7113
Middle East Headquarters
Conexant Systems
Commercial (Israel) Ltd.
P. O. Box 12660
U.S. South Central
Phone: (972) 733-0723
Fax: (972) 407-0639
Herzlia 46733, ISRAEL
Phone: (972 9) 952 4064
Fax: (972 9) 951 3924
U.S. Southeast
Phone: (919) 858-9110
Fax: (919) 858-8669
Japan Headquarters
Conexant Systems Japan Co., Ltd.
Shimomoto Building
1-46-3 Hatsudai,
U.S. Southwest
Phone: (949) 483-9119
Fax: (949) 483-9090
Shibuya-ku, Tokyo
151-0061 JAPAN
Phone: (81 3) 5371-1567
Fax: (81 3) 5371-1501
APAC Headquarters
Conexant Systems Singapore, Pte.
Ltd.
1 Kim Seng Promenade
Great World City
#09-01 East Tower
SINGAPORE 237994
Phone: (65) 737 7355
Fax: (65) 737 9077
Taiwan Headquarters
Conexant Systems, Taiwan Co., Ltd.
Room 2808
International Trade Building
333 Keelung Road, Section 1
Taipei 110, TAIWAN, ROC
Phone: (886 2) 2720 0282
Fax: (886 2) 2757 6760
Australia
Phone: (61 2) 9869 4088
Fax: (61 2) 9869 4077
China
Phone: (86 2) 6361 2515
Fax: (86 2) 6361 2516
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