74HC595D [TGS]
8-Bit Shift Registers with Output Latches;
| 型号： | 74HC595D |
| 厂家： | 
Tiger Electronic Co.,Ltd |
| 描述： | 8-Bit Shift Registers with Output Latches 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIGER ELECTRONIC CO.,LTD
74HC595D / 74HC595V / 74HC595P
8-Bit Shift Registers with Output Latches
General Description
The 74HC595 high speed shift register utilizes advanced silicon-gate CMOS technology. This device
possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as
the ability to drive 15 LS-TTL loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an
8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both
the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial
output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks.
If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage
register.
Features
● Low quiescent current: 80µA maximum
● Low input current: 1µA maximum
● 8-bit serial-in, parallel-out shift register with storage
● Wide operating voltage range: 2V–6V
● Cascadable
● Shift register has direct clear
● Guaranteed shift frequency: DC to 30 MHz
● Package: SOP16(74HC595D), TSSOP16(74HC595V), DIP16(74HC595P)
Connection Diagram
1
2
3
4
5
Q
16
15
14
13
12
11
VCC
B
Q
C
Q
A
SER
G
Q
D
Q
E
Q
F
RCK
SCK
SCLR
Q
G
6
7
Q
H
10
9
'
Q
H
8
GND
SOP16(74HC595D), TSSOP16(74HC595V), DIP16(74HC595P)
Rev 2.2 2013-11-21
74HC595
Pin Function
Pin
Name
QA～QH
GND，VCC
Q’H
I/O
Description
8 bit 3-STATE Output
Grond, Supply
15，1～7
O
－
O
I
8，16
9
Serial Output
10
Shift Register cleared
Shift Register clocked
Output Register clocked
Output state control
Data input
SCLR
11
SCK
I
12
RCK
I
13
I
G
14
SER
I
Truth Table
RCK
X
SCK
Description
QA to QH = 3-STATE
SCLR
G
H
L
L
X
X
X
L
X
Shift Register cleared, Q’H =0
Shift Register clocked,QN= Qn-1，Q0= SER
Contents of Shift Register transferred to output
latches
X
↑
H
↑
X
H
L
Rev 2.2 2013-11-21
2/7
74HC595
Logic Diagram
13
12
14
G
RCK
SER
15
1
D
R
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
QA
QB
QC
QD
QE
QF
QG
QH
D
R
2
D
R
3
D
R
PARALLEL
DATA OUTPUTS
4
D
R
5
D
R
6
D
R
7
9
D
R
11
10
SCK
SERIAL DAT A
OUTPUT
'
SCLR
QH
Rev 2.2 2013-11-21
3/7
74HC595
Timing Diagram
Absolute Maximum Ratings
Parameter
Symbol
Scope
Unit
Supply Voltage
VCC
-0.5～7.0
V
DC Input Voltage
DC Output Voltage
VIN
VOUT
IOUT
ICC
-1.5～VCC +1.5
-0.5～VCC +0.5
±35
V
V
DC Output Current
mA
mA
mW
℃
DC VCC or GND Current
Power Dissipation
±70
PD
600
Storage Temperature Range
TSTG
-65～150
Recommended Operating Conditions
Parameter
Symbol
Condition
Min
Max
Unit
Supply Voltage
VCC
2
0
6
V
V
DC Input or Output Voltage
VIN ，VOUT
VCC
1000
500
400
+85
V
CC =2.0V
Input Rise or Fall Times
tr , tf
TA
VCC =4.5V
VCC =6.0V
ns
Operating Temperature Range
-40
℃
Rev 2.2 2013-11-21
4/7
74HC595
Electrical Characteristics
DC Characteristics
TA=25 to
TA=-55 to
TA=25℃
85℃
125℃
Symbol Parameter
Condition
VCC
Unit
V
typ
Guaranteed Limits
2V
4.5V
6V
1.5
1.5
1.5
Minimum High
VIH
Level
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
Input Voltage
2V
Maximum Low
Level Input
Voltage
VIL
4.5V
6V
V
2V
2.0
4.5
6
Minimum High
Level
VIN = VIH or VIL
4.5V
6V
V
V
︱IOUT ︱≤20μA
Output Voltage
VIN = VIH or VIL
︱IOUT ︱≤4.0mA
︱IOUT ︱≤5.2mA
VIN = VIH or VIL
︱IOUT ︱≤6.0mA
︱IOUT ︱≤7.8mA
4.5V
6V
4.2
5.2
3.98
5.48
3.84
5.34
3.7
5.2
VOH
QH
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
QA to QH
V
2V
4.5V
6V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Maximum
LOW Level
VIN = VIH or VIL
V
︱IOUT ︱≤20μA
Output Voltage
VIN = VIH or VIL
︱IOUT ︱≤4.0mA
︱IOUT ︱≤5.2mA
VIN = VIH or VIL
4.5V
6V
0.2
0.2
0.2
0.2
0.26
0.26
0.26
0.26
0.33
0.33
0.33
0.33
0.4
0.4
0.4
0.4
VOL
QH
V
4.5V
6V
QA to QH
︱IOUT ︱≤6.0mA
︱IOUT ︱≤7.8mA
V
Maximum
Input
IIN
IOZ
ICC
VIN = VCC or GND
6V
6V
6V
±0.1
±0.5
8.0
±1.0
±5.0
80
±1.0
±10
160
μA
Current
Maximum
3-STATE
Output
VOUT = VCC or GND
μA
μA
G = VIH
Leakage
Maximum
Quiescent
Supply Current
VIN = VCC or GND
IOUT= 0μA
Rev 2.2 2013-11-21
5/7
74HC595
AC Characteristics (VCC =5V，TA =25℃，tr=tf =6ns)
Guaranteed
Limit
Symbol
Parameter
Condition
Typ
50
Unit
MHz
ns
Maximum Operating Frequency of
SCK
fMAX
30
20
30
28
25
20
20
40
0
Maximum Propagation Delay, SCK
to QH’
tPHL tPLH
CL =45pF
CL =45pF
12
Maximum Propagation Delay, RCK
to QA thru QH
tPHL tPLH
18
ns
Maximum Output Enable Time from
G to QA thru QH
RL=1kΩ
CL =45pF
RL=1kΩ
CL =5pF
tPZH tPZL
17
ns
Maximum Output Disable Time
from G to QA to QH
Minimum Setup Time from SER to
SCK
tPHZ tPLZ
15
ns
tS
tS
ns
Minimum Setup Time from SCLR
to SCK
ns
Minimum Setup Time from SCK to
RCK
tS
ns
Minimum Hold Time from SER to
SCK
tH
tW
ns
Minimum Pulse Width of SCK or
RCK
16
ns
AC Characteristics (VCC =2.0～6.0V，CL =50pF，tr=tf =6ns)
TA=25℃
TA=25 to 85℃
TA=-55 to 125℃
Symb
Parameter
Condition
VCC
Unit
ol
Typ
10
45
50
58
83
14
17
10
14
70
105
21
28
18
Guaranteed Limit
2V
4.5V
6V
6
4.8
24
4.0
20
Maximum
Operating
Frequency
fMAX
CL =50pF
30
MHz
35
28
24
2V
210
294
42
265
367
53
315
441
63
CL =50pF
ns
ns
ns
ns
CL =150pF
2V
Maximum
Propagation
Delay from
SCK to QH
4.5V
4.5V
6V
tPHL
tPLH
CL =50pF
CL =150pF
58
74
88
36
45
54
CL =50pF
CL =150pF
6V
50
63
76
2V
175
245
35
220
306
44
265
368
53
CL =50pF
Maximum
Propagation
Delay from
RCK to QA thru
QH
CL =150pF
2V
tPHL
tPLH
4.5V
4.5V
6V
CL =50pF
ns
ns
CL =150pF
49
61
74
CL =50pF
30
37
45
Rev 2.2 2013-11-21
6/7
74HC595
CL =150pF
6V
2V
26
42
53
221
44
63
261
52
ximum
Propagation
delay
175
36
4.5V
tPHL
tPLH
ns
ns
fromSCLR to
QH
6V
30
37
44
RL =1kΩ
CL =50pF
CL =150pF
CL =50pF
CL =150pF
2V
2V
75
175
245
220
306
265
368
Maximum
Output Enable
from G to QA
thru QH
100
tPZH
tPZL
4.5V
4.5V
6V
15
20
13
17
75
15
35
49
44
61
53
74
ns
ns
30
37
45
CL =50pF
CL =150pF
6V
42
53
63
Maximum
Output Disable
Time from G
to QA thru QH
Minimum Setup
Time
2V
175
35
220
44
265
53
tPHZ
tPLZ
RL =1kΩ
4.5V
ns
ns
ns
CL =50pF
6V
13
30
37
45
2V
100
20
125
25
150
30
4.5V
tS
from SER to
SCK
6V
17
21
25
Minimum
2V
50
10
63
13
75
15
Removal Time
from SCLR to
SCK
4.5V
tR
6V
9
11
13
Minimum Setup
Time
2V
100
20
125
25
150
30
4.5V
tS
tH
tW
ns
ns
ns
from SCK to
RCK
6V
17
21
26
2V
5
5
5
5
5
5
Minimum Hold
Time
4.5V
SER to SCK
6V
5
5
5
Minimum Pulse
Width
2V
30
9
80
16
100
20
120
24
4.5V
of SCK or
SCLR
6V
8
14
18
22
Maximum Input
Rise and
2V
1000
500
1000
500
1000
500
4.5V
tr tf
ns
ns
Fall Time,
Clock
6V
400
400
400
2V
25
7
60
12
75
15
90
18
tTHL
tTLH
Maximum
Output
4.5V
Rev 2.2 2013-11-21
7/7
74HC595
Rise and Fall
Time
6V
6
10
13
15
QA–QH
Maximum
Output
2V
75
15
95
19
110
22
4.5V
tTHL
tTLH
Rise & Fall
Time
ns
6V
13
16
19
QH
Power
90
Dissipation
Capacitance,
Outputs
G =VCC
CPD
pF
150
G =GND
Enabled
Maximum Input
Capacitance
Maximum
Output
CIN
5
10
20
10
20
10
20
pF
pF
COUT
15
Capacitance
Rev 2.2 2013-11-21
8/7
74HC595
Package Dimension
SOP16
0.203
10.00±0.10
2°～8°
0.406±0.1
1.27
Unit：mm
0.20±0.10
TSSOP16
4.96±0.10
1.20MAX
0.20
～
0.28
0.65
0°～8°
Unit：mm
0.05～0.15
0.10
DIP16
7.62
2.54
3.80±0.20
3.30±0.30
0.254
8.40～9.20
0.46±0.10
19.10±0.20
1.52
Unit：mm
Rev 2.2 2013-11-21
9/7
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