2N7001TQDCKRQ1 [TI]
汽车类 1 位双电源缓冲电压信号转换器 | DCK | 5 | -40 to 125;
| 型号： | 2N7001TQDCKRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 1 位双电源缓冲电压信号转换器 | DCK | 5 | -40 to 125 光电二极管 接口集成电路 转换器 |
| 文件： | 总22页 (文件大小：1627K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2N7001T-Q1
ZHCSKU1A –FEBRUARY 2020 –REVISED JULY 2020
2N7001T-Q1 Single-bit 双电源缓冲电压信号转换器
1 特性
3 说明
• 在1.65V 至3.6 V 范围内进行上行和下行电平转换
• 符合AEC-Q100 汽车标准
• 工作温度等级1：–40°C 至+125°C
• 最大静态电流(ICCA + ICCB) 14µA（最高125°C）
• 在整个电源范围内支持高达100Mbps 的速率
• VCC 隔离特性
2N7001T-Q1 器件符合 AEC-Q100 标准，是一款采用
两个独立可配置电源轨的 single-bit 缓冲电压信号转换
器，可对单向信号进行升压/降压转换。该器件通过
1.65V 至 3.60V 的 VCCA 和 VCCB 电源供电。VCCA
定
义了A 输入端的输入阈值电压。VCCB 定义了B 输出端
的输出驱动电压。
– 如果任何一个VCC 输入低于100mV，则输出处
于高阻态
• Ioff 支持局部断电模式运行
• 闩锁性能超过100mA，符合JESD 78 II 类规范
• ESD 保护性能超过JEDEC JS-001 规范要求
该器件完全符合使用 Ioff 电流的部分断电应用的规范要
求。当器件断电时，Ioff 保护电路可确保不从输入、输
出或偏置到特定电压的组合I/O 获取多余电流，也不向
其提供多余电流。
VCC 隔离功能确保当 VCCA 或 VCCB 低于 100mV 时，
输出端口(B) 进入高阻态。
– 2000V 人体放电模型
– 1000V 充电器件模型
器件信息(1)
2 应用
封装尺寸（标称值）
器件型号
封装
• MCU/FPGA/处理器GPIO 转换
• 通信模块至处理器转换
• 推挽式I/O 缓冲
2N7001TDCKRQ1
SC70 (5)
2.00mm × 1.25mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VCCA
VCCB
DCK Package
2N7001T-Q1
VCCA
B
VCCB
GND
5
1
2
A
B
ESD
ESD
A
3
4
方框图和引脚配置
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCES906
2N7001T-Q1
ZHCSKU1A –FEBRUARY 2020 –REVISED JULY 2020
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Table of Contents
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Applications.................................................. 12
10 Power Supply Recommendations..............................14
11 Layout...........................................................................14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Documentation Support.......................................... 15
12.2 Receiving Notification of Documentation Updates..15
12.3 Support Resources................................................. 15
12.4 Trademarks.............................................................15
12.5 Electrostatic Discharge Caution..............................15
12.6 Glossary..................................................................15
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................6
6.7 Operating Characteritics: TA = 25°C...........................6
6.8 Typical Characteristics................................................8
7 Parameter Measurement Information............................9
7.1 Load Circuit and Voltage Waveforms..........................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
Information.................................................................... 15
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (February 2020) to Revision A (July 2020)
Page
• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Pin Configuration and Functions
VCCA
B
VCCB
GND
5
4
1
2
A
3
图5-1. DCK Package 5-Pin SC70 Top View
Pin Functions
PIN
TYPE
DESCRIPTION
Data Output. This pin is referenced to VCCB
NAME
B
DCK
1
2
3
4
5
O
.
VCCB
GND
A
Output Supply voltage. 1.65V ≤VCCB ≤3.6 V.
—
Ground
—
I
Data Input. This pin is referenced to VCCA
.
VCCA
Input Supply voltage. 1.65V ≤VCCA ≤3.6 V.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCCA
4.2
4.2
Supply voltage
VCCB
V
VI
Input voltage(2)
4.2
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2) (3)
4.2
V
VCCB + 0.2
–50
–50
50
V
Input clamp current
VI < 0
mA
mA
mA
mA
°C
°C
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous output current through VCCA, VCCB, or GND
Junction temperature
–50
–100
–40
ICC
TJ
100
150
Tstg
Storage temperature
150
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.2V maximum if the output current ratings are observed.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.65
MAX
3.6
UNIT
V
VCCA
VCCB
Supply voltage
Supply voltage
1.65
3.6
V
VCCA = 1.65 V - 1.95V
VCCA = 2.30 V - 2.70V
VCCA = 3.00 V - 3.60V
VCCA = 1.65 V - 1.95V
VCCA = 2.30 V - 2.70V
VCCA = 3.00 V - 3.60V
VCCA x 0.65
1.6
VIH
High-level input voltage
Low-level input voltage
2.0
VCCA x 0.35
0.7
VIL
0.8
VI
Input voltage
0
0
0
3.6
V
V
Active State
Tri-State
VCCB
3.6
VO
Output voltage
Input transition rise and fall rate
Operating free-air temperature
100
ns/V
°C
Δt/Δv
TA
125
–40
6.4 Thermal Information
2N7001T-Q1
THERMAL METRIC(1)
DCK (SC70)
5 PINS
253.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
162.6
140.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
69.8
ΨJT
139.7
ΨJB
RθJC(bot)
NA
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
MIN
VCCB-0.1
1.2
TYP
MAX UNIT
IOH = -100 µA
1.65 V - 3.6 V 1.65 V - 3.6 V
High Level
Output
Voltage
IOH = -8 mA
1.65 V
2.30 V
3.00 V
1.65 V
2.30 V
3.00 V
VOH
VI = VIH
V
IOH = -9 mA
IOH = -12 mA
IOL = 100 µA
IOL = 8 mA
1.75
2.3
1.65 V - 3.6 V 1.65 V - 3.6 V
0.1
Low Level
Output
Voltage
1.65 V
2.30 V
3.00 V
0 V
1.65 V
2.30 V
3.00 V
0 V - 3.6 V
0 V
0.45
V
0.55
VOL
VI = VIL
IOL = 9 mA
IOL = 12 mA
0.7
VI or VO = 0 V - 3.6 V
VI or VO = 0 V - 3.6 V
8
–8
–8
Partial power
down current
Ioff
µA
8
0 V - 3.6 V
1.65 V - 3.6 V 1.65 V - 3.6 V
8
VCCA Supply
Current
ICCA
VI = VCCA or GND; Io = 0 mA
0 V
3.60 V
0 V
µA
–8
3.60 V
8
1.65 V - 3.6 V 1.65 V - 3.6 V
8
VCCB Supply
Current
0 V
3.60 V
0 V
8
ICCB
VI = VCCA or GND; Io = 0 mA
VI = VCCA or GND; Io = 0 mA
µA
µA
3.60 V
–8
Combined
Supply
Current
ICCA
ICCB
+
1.65 V - 3.6 V 1.65 V - 3.6 V
14
Input
Capacitance
VI = 1.65V DC + 1 MHz, -16
dBm sine wave
CI
3.30V
0V
0V
2
4
pF
pF
Output
Capacitance
VO = 1.65V DC + 1 MHz, -16
dBm sine wave
CO
3.30V
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCCA
VCCB
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
20
17
14
18
15
12
16
13
10
UNIT
ns
1.65 V - 1.95 V
2.30 V - 2.70 V
3.00 V - 3.60 V
1.65 V - 1.95 V
2.30 V - 2.70 V
3.00 V - 3.60 V
1.65 V - 1.95 V
2.30 V - 2.70 V
3.00 V - 3.60 V
1.65 V - 1.95 V
2.30 V - 2.70 V
3.00 V - 3.60 V
ns
ns
ns
tpd
Propagation delay
ns
ns
ns
ns
ns
6.7 Operating Characteritics: TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
IO = 0 mA,
CL = 0 pF,
f = 1 MHz
tr = tf = 1 ns
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
Power Dissipation
Capacitance - Port A
1.3
1.8
CpdA
pF
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PARAMETER
TEST CONDITIONS
VCCA = VCCB = 1.8 V
MIN
TYP
12
MAX
UNIT
IO = 0 mA,
CL = 0 pF,
f = 1 MHz
tr = tf = 1 ns
Power Dissipation
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
15
CpdB
pF
Capacitance - Port B
18
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6.8 Typical Characteristics
Output High Voltage (VOH) vs. Output High Current (IOH
)
Output Low Voltage (VOL) vs. Output Low Current (IOL)
V
VCCA = VCCB = 1.8 V, TA = 25èC
CCA = VCCB = 1.8V, TA = 25èC
1.85
1.8
0.4
0.35
0.3
1.75
1.7
0.25
0.2
1.65
1.6
0.15
0.1
1.55
1.5
0.05
0
1.45
-8
-7
-6
-5
Output High Current (IOH) [mA]
-4
-3
-2
-1
0
0
0
0
1
2
3
Output Low Current (IOL) [mA]
4
5
6
7
8
VOH1
VOL1
图6-1. VOH vs IOH, 1.8 V
图6-2. VOL vs IOL, 1.8 V
Output High Voltage (VOH) vs. Output High Current (IOH
CCA = VCCB = 2.5V, TA = 25èC
)
Output Low Voltage (VOL) vs. Output Low Current (IOL)
VCCA = VCCB = 2.5V, TA = 25èC
V
2.55
2.5
0.4
0.35
0.3
2.45
2.4
0.25
0.2
2.35
2.3
0.15
0.1
2.25
2.2
0.05
0
2.15
-9
-8
-7
-6
-5
-4
-3
Output High Current (IOH) [mA]
-2
-1
0
1
2
3
4
5
6
Output Low Current (IOL) [mA]
7
8
9
VOH2
VOL2
图6-3. VOH vs IOH, 2.5 V
图6-4. VOL vs IOL, 2.5 V
Output High Voltage (VOH) vs. Output High Current (IOH
VCCA = VCCB = 3.3V, TA = 25èC
)
Output Low Voltage (VOL) vs. Output Low Current (IOL)
VCCA = VCCB = 3.3V, TA = 25èC
3.35
3.3
0.5
0.45
0.4
3.25
3.2
0.35
0.3
3.15
3.1
0.25
0.2
3.05
3
0.15
0.1
2.95
2.9
0.05
0
2.85
-12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1
Output High Current (IOH) [mA]
0
1
2
3 7
Output Low Current (IOL) [mA]
4
5
6
8
9
10 11 12
VOH3
VOL3
图6-5. VOH vs IOH, 3.3 V
图6-6. VOL vs IOL, 3.3 V
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f = 1 MHz
• ZO = 50 Ω
• dv/dt ≤1 ns/V
Measurement Point
Output Pin
Under Test
(1)
CL
RL
A. CL includes probe and jig capacitance.
图7-1. Load Circuit
表7-1. Load Circuit Conditions
Parameter
VCC
RL
CL
tpd
Propagation (delay) time
15 pF
1.65 V –3.6 V
2 kΩ
VCCA
VCCA / 2
VCCA / 2
Input A
0 V
VOH
tpd
tpd
(2)
Output B
VCCB / 2
VCCB / 2
(2)
VOL
A. VCCI is the supply pin associated with the input port.
B. VOH and VOL are typical output voltage levels that occur with specified RL and CL.
图7-2. Propagation Delay
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8 Detailed Description
8.1 Overview
The 2N7001T-Q1 is an automotive AEC-Q100 qualified single-bit dual-supply buffered voltage signal converter
that can be used to up or down-translate a single unidirectional signal. The device is operational with both VCCA
and VCCB supplies down to 1.65 V and up to 3.60 V. VCCA defines the input threshold voltage on the A input
while VCCB defines the output voltage on the B output.
8.2 Functional Block Diagram
1.8 V
3.3 V
2N7001T-Q1
VCCA
VCCB
System
Controller
A
PROC
ERR
B
PROC
ERR
Processor
ESD
ESD
GND
8.3 Feature Description
8.3.1 Up-Translation or Down-Translation from 1.65 V to 3.60 V
The VCCA and VCCB pins can both be supplied by a voltage range from 1.65 V to 3.6 V. This voltage range
makes the device suitable for translating between any of the voltage nodes (1.8 V, 2.5 V, and 3.3 V).
8.3.2 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to over-
current. The electrical and thermal limits defined the in the Absolute Maximum Raings must be followed at all
times.
8.3.3 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance shown in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, shown in the Absolute Maximum Ratings, and the maximum input leakage current, shown in the
Electrical Characteristics, using Ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in the Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
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8.3.4 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as shown in 图8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input negative-voltage and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
图8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.5 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input pin or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.6 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the input supply voltage (VCCA), as long as they remain below
the maximum input voltage value specified in the Recommended Operating Conditions.
8.4 Device Functional Modes
表8-1 lists the functional modes of the 2N7001T-Q1 device.
表8-1. Function Table
INPUT
OUTPUT
L (Referenced to VCCA
)
L (Referenced to VCCB)
H (Referenced to VCCA
)
H (Referenced to VCCB)
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9 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The 2N7001T-Q1 device can be used in level-translation applications for interfacing between devices or systems
that are operating at different interface voltages.
9.2 Typical Applications
9.2.1 Processor Error Up Translation
图9-1 shows an example of the 2N7001T-Q1 being used in a unidirectional logic level-shifting application.
1.8 V
3.3 V
2N7001T-Q1
VCCA
VCCB
System
Controller
A
PROC
ERR
B
PROC
ERR
Processor
ESD
ESD
GND
图9-1. Processor Error Up Translation Application
9.2.1.1 Design Requirements
For this design example, use the parameters shown in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETER
Input voltage supply
Output voltage supply
EXAMPLE VALUE
1.8 V
3.3 V
9.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– The supply voltage of the upstream device (device that is driving input pin A) will determine the
appropriate input voltage range. For a valid logic-high, the value must exceed the high-level input voltage
(VIH) of the input port. For a valid logic low the value must be less than the low-level input voltage (VIL) of
the input port.
• Output voltage range
– The supply voltage of the downstream device (device that output pin B is driving) will determine the
appropriate output voltage range.
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9.2.1.3 Application Curve
A Data Input = 1.8V
B Data Output = 3.3V
图9-2. Up Translation (1.8 V to 3.3 V) at 1 MHz
9.2.2 Discrete FET Translation Replacement
The 2N7001T-Q1 device is an excellent option for replacing discrete translators, as shown in 图9-3, and has the
following benefits regarding discrete translation implementations:
• A single device vs a four component solution
• Minimized implementation size
• Lower power consumption
• VCC isolation feature
• Higher data rates
• Integrated ESD protection
• Improved glitch performance
Discrete Translator: Four Component,
Push-Pull Translation w/o ESD Protection
2N7001T: Single Small Footprint Device,
Low Power Translation with ESD Protection
0603
Res.
SOT23
FET
DCK Package
VCCA
1
2
3
5
B
VCCB
GND
4
A
SOT23
FET
SOT23
FET
Solution Size: 4.2mm2
Solution Size: ~ 60mm2
图9-3. Discrete Translation vs. 2N7001T-Q1 Solution
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: 2N7001T-Q1
2N7001T-Q1
ZHCSKU1A –FEBRUARY 2020 –REVISED JULY 2020
www.ti.com.cn
10 Power Supply Recommendations
The 2N7001T-Q1 device uses two separate configurable power-supply rails, VCCA and VCCB. The VCCA and
VCCB power-supply rails accept any supply voltage that range from 1.65 V to 3.6 V. The A input and B output are
referenced to VCCA and VCCB respectively allowing up or down translation among the 1.8-V, 2.5-V, and 3.3-V
voltage nodes. A 0.1 µF bypass capacitor is recommended on all VCC pins.
Always apply a ground reference to the GND pin first. However, there are no additional requirement for power
supply sequencing.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:
• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF
capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF
capacitors in parallel as bypass capacitors.
• Use short trace lengths to avoid excessive loading.
11.2 Layout Example
Legend
Via to VCCA
Via to VCCB
A
B
G
Via to GND
Copper Traces
2N7001TDCKRQ1
A
A
Applications MCU
Wake Input
1
2
3
5
4
VCCA
0402
0.1µF
B
B
G
VCCB
0402
0.1µF
V2X Processor
Enable Flag
G
GND
A
G
图11-1. DCK Package Example Layout
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: 2N7001T-Q1
2N7001T-Q1
ZHCSKU1A –FEBRUARY 2020 –REVISED JULY 2020
www.ti.com.cn
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Common Risks with FET Translation and Advantages of 2N7001T application report
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
• Texas Instruments, Designing and Manufacturing with TI's X2SON Packages application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: 2N7001T-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
2N7001TQDCKRQ1
ACTIVE
SC70
DCK
5
3000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
W9
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
2N7001TQDCKRQ1
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SC70 DCK
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
2N7001TQDCKRQ1
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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