54AC11534_09 [TI]
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS;
| 型号： | 54AC11534_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS 输出元件 |
| 文件： | 总7页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
• Eight D-Type Flip-Flops in a Single Package
• 3-State Bus Driving Inverting Outputs
• Full Parallel Access for Loading
54AC11534 . . . JT PACKAGE
74AC11534 . . . DW OR NT PACKAGE
(TOP VIEW)
• Inputs Are TTL-Voltage Compatible
1Q
2Q
OC
1D
2D
3D
4D
1
24
23
22
21
20
19
18
17
16
15
14
13
2
• Flow-Through Architecture to Optimize
3Q
3
PCB Layout
4Q
4
• Center-Pin V
and GND Configurations to
Minimize High-Speed Switching Noise
CC
GND
GND
GND
GND
5Q
5
6
V
V
CC
CC
• EPIC (Enhanced-Performance Implanted
7
CMOS) 1- m Process
8
5D
• 500-mA Typical Latch-Up Immunity
at 125°C
9
6D
10
11
12
6Q
7D
• Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
7Q
8D
8Q
CLK
54AC11534 . . . FK PACKAGE
(TOP VIEW)
description
These eight flip-flops feature 3-state outputs
designed for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
4
3
2 1 28 27 26
5
25 7D
2D
1D
OC
NC
1Q
2Q
3Q
6
24
23
22
21
20
19
8D
7
CLK
NC
8Q
7Q
6Q
The eight flip-flops of the ′AC11534 are edge-
triggered, D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
complement of the logic levels at the D inputs. The
′AC11534 is functionally equivalent to the
′AC11374 except for having inverted outputs.
8
9
10
11
12 13 14 15 16 17 18
An output-control input (OC) is used to place the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
NC – No internal connection
nor drive the bus lines significantly.
The
FUNCTION TABLE
(each filp-flop)
high-impedance third state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components. The output control (OC)
does not affect the internal operation of the
flip-flops. Old data can be retained or new data
can be entered while the outputs are in the
high-impedance state.
INPUTS
OUTPUT
Q
OC
CLK
D
L
L
L
↑
↑
L
X
H
L
H
L
X
X
Q
Z
0
H
The 54AC11534 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The 74AC11534 is characterized for
operation from – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
†
logic diagram (positive logic)
logic symbol
24
24
OC
OC
EN
C1
13
13
CLK
CLK
23
22
21
20
17
16
15
14
1
2
C1
1D
1
2
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
23
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
3
C1
1D
4
22
21
20
17
16
15
14
9
10
11
12
C1
1D
3
C1
1D
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
C1
1D
9
C1
1D
10
11
12
C1
1D
C1
1D
Pin numbers shown are for the DW, JT, and NT packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
recommended operating conditions
54AC11534
MIN NOM
74AC11534
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
3
2.1
5
5.5
3
2.1
5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
High-level input voltage
V
V
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
IH
0.9
1.35
1.65
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
– 4
V
CC
– 4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
Low-level output current
mA
mA
= 4.5 V
= 5.5 V
= 3 V
– 24
–24
12
– 24
–24
12
OH
I
= 4.5 V
= 5.5 V
24
24
OL
24
24
OC
D
0
0
5
0
0
5
t/ v
Input transition rise or fall rate
Operating free-air temperature
ns/V
10
10
T
–55
125
– 40
85
°C
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54AC11534
74AC11534
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
3.85
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
3 V
I
= – 50 A
4.4
4.4
OH
5.4
5.4
I
I
= – 4 mA
2.58
3.94
4.94
2.48
3.8
OH
V
OH
V
4.5 V
5.5 V
5.5 V
5.5 V
3 V
= – 24 mA
OH
4.8
I
I
= – 50 mA
= – 75 mA
OH
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 A
4.5 V
5.5 V
3 V
OL
0.1
0.1
0.1
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.5
0.44
0.44
0.44
OL
V
OL
V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
0.5
OL
0.5
I
I
= 50 mA
= 75 mA
1.65
OL
OL
1.65
± 5
± 1
80
I
I
I
V
= V or GND
CC
± 0.5
± 0.1
8
± 10
± 1
A
A
OZ
O
V = V
or GND
or GND,
or GND
I
I
CC
CC
CC
V = V
I = 0
O
160
A
CC
I
C
C
V = V
4
pF
pF
i
I
V
= V or GND
CC
5 V
10
o
O
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
timing requirements, V
= 3.3 V ± 0.3 V (see Figure 1)
CC
T
= 25°C
54AC11534
74AC11534
A
UNIT
MIN
0
MAX
MIN
0
MAX
50
MIN
0
MAX
50
f
t
t
t
Clock frequency
50
MHz
ns
clock
Pulse duration, CLK low or CLK high
Setup time, data before CLK ↑
Hold time, data after CLK ↑
10
10
10
w
3.5
5.5
3.5
5.5
3.5
5.5
ns
su
h
ns
timing requirements, V
= 5 V ± 0.5 V (see Figure 1)
CC
T
= 25°C
54AC11534
74AC11534
A
UNIT
MIN
0
MAX
MIN
0
MAX
75
MIN
0
MAX
75
f
t
t
t
Clock frequency
75
MHz
ns
clock
Pulse duration, CLK low or CLK high
Setup time, data before CLK ↑
Hold time, data after CLK ↑
6.5
3.5
4.5
6.5
3.5
4.5
6.5
3.5
4.5
w
ns
su
h
ns
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
75
11
54AC11534
74AC11534
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
50
MAX
MIN
50
MAX
MIN
50
MAX
f
max
PLH
PHL
PZH
t
t
1.5
1.5
1.5
1.5
1.5
1.5
15.3
15.7
12.8
12.6
12.6
13
1.5
1.5
1.5
1.5
1.5
1.5
19.1
19
1.5
1.5
1.5
1.5
1.5
1.5
17.6
17.7
14.6
14.3
13.3
13.8
CLK
Q
Q
Q
11
t
9
15.8
15.6
13.8
14.2
ns
ns
OC
OC
t
9
PZL
t
10
8
PHZ
t
PLZ
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T = 25°C
A
54AC11534
74AC11534
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
75
TYP
100
7
MAX
MIN
75
MAX
MIN
75
MAX
f
max
PLH
PHL
PZH
t
t
1.5
1.5
1.5
1.5
1.5
1.5
10.3
10.7
9.2
1.5
1.5
1.5
1.5
1.5
1.5
12.7
13.2
11.2
11.3
11.9
9.6
1.5
1.5
1.5
1.5
1.5
1.5
11.7
12.1
10.4
10.4
11.6
9.2
CLK
Q
Q
Q
7
t
6
ns
ns
OC
OC
t
6
9.2
PZL
t
9
11.1
8.8
PHZ
t
6
PLZ
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
Outputs enabled
Outputs disabled
75
65
C
Power dissipation capacitance per flip-flop
C
pF
pd
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC11534, 74AC11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS037A – JULY 1987 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
/t
t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
V
CC
Timing Input
(see Note B)
50%
0 V
t
w
t
h
t
V
CC
su
V
CC
Input
50%
50%
50%
50%
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
Input
(see Note B)
50%
50%
50%
50%
0 V
0 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note C)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
0 V
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
V
OL
(see Note C)
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–6
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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