54ACT16823_06
更新时间：2024-09-18 06:50:14
品牌：TI
描述：18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
概述
数据手册54ACT16823_06 概述
18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS 18位总线接口触发器具有三态输出
54ACT16823_06 数据手册
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PDF下载54ACT16823, 74ACT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS160A – APRIL 1991 – REVISED APRIL 1996
54ACT16823 . . . WD PACKAGE
74ACT16823 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLR
1OE
1Q1
GND
1Q2
1Q3
1CLK
1CLKEN
1D1
GND
1D2
2
3
Flow-Through Architecture Optimizes PCB
Layout
4
5
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
6
1D3
CC
7
V
V
CC
CC
8
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
These 18-bit flip-flops feature 3-state outputs
designed specifically for driving highly-capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, parity bus interfacing, and
working registers.
V
V
CC
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
2D7
2D8
GND
2D9
2CLKEN
2CLK
The ’ACT16823 can be used as two 9-bit flip-flops
or one 18-bit flip-flop. With the clock-enable
(CLKEN) input low, the D-type flip-flops enter data
on the low-to-high transitions of the clock. Taking
CLKEN high disables the clock buffer, thus
latching the outputs. Taking the clear (CLR) input
low causes the Q outputs to go low independently
of the clock.
A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74ACT16823 is packaged in theTI shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16823 is characterized for operation over the full military temperature range of 55°C to 125°C. The
74ACT16823 is characterized for operation from –40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16823, 74ACT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS160A – APRIL 1991 – REVISED APRIL 1996
FUNCTION TABLE
(each 9-bit stage)
INPUTS
OUTPUT
Q
OE
L
CLR CLKEN CLK
D
X
H
L
L
H
H
H
H
X
X
L
X
↑
L
H
L
L
L
L
↑
L
L
L
X
X
X
X
X
Q
Q
0
0
L
H
X
H
Z
†
logic symbol
2
1
EN1
R2
1OE
1CLR
1CLKEN
1CLK
55
G3
56
27
28
30
29
3C4
EN5
R6
2OE
2CLR
2CLKEN
2CLK
G7
7C8
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
3
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
4D
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
1, 2
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
25
8D
5, 6
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16823, 74ACT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS160A – APRIL 1991 – REVISED APRIL 1996
logic diagram (positive logic)
2
1OE
1
1CLR
R
55
1CLKEN
CE
56
3
1CLK
C1
1D
1Q1
54
1D1
One of Nine Channels
To Eight Other Channels
27
2OE
28
2CLR
R
30
2CLKEN
CE
29
15
2CLK
C1
1D
2Q1
42
2D1
One of Nine Channels
To Eight Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16823, 74ACT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS160A – APRIL 1991 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum package power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W
Storage temperature range, T
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±450 mA
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils.
recommended operating conditions (see Note 2)
54ACT16823
MIN NOM
74ACT16823
MIN NOM
UNIT
MAX
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
24
–24
24
mA
mA
ns/V
°C
OH
OL
I
∆t/∆v
0
10
0
10
T
–55
125
–40
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16823, 74ACT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS160A – APRIL 1991 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54ACT16823
74ACT16823
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
= –50 µA
OH
5.4
5.4
5.4
V
3.94
4.94
3.8
3.8
V
OH
OL
I
I
I
= –24 mA
OH
OH
OL
4.8
4.8
†
= –75 mA
= 50 µA
3.85
3.85
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.44
0.44
1.65
±1
0.44
0.44
1.65
±1
V
I
I
= 24 mA
OL
†
= 75 mA
OL
I
I
I
V = V
or GND
±0.1
±0.5
8
µA
µA
µA
I
I
CC
V
= V
or GND
±5
±5
OZ
CC
O
CC
V = V
or GND,
I
O
= 0
80
80
I
CC
One input at 3.4 V,
Other inputs at V
‡
5.5 V
0.9
1
1
mA
∆I
CC
or GND
CC
or GND
C
C
V = V
5 V
5 V
3
pF
pF
i
I
CC
= V or GND
CC
V
12
o
O
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
timing requirements over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
= 25°C
54ACT16823
74ACT16823
A
UNIT
MHz
ns
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
90
90
90
clock
CLR low
3.3
5.5
0.5
7
3.3
5.5
0.5
7
3.3
5.5
0.5
7
w
CLK high or low
CLR inactive
Data
t
Setup time before CLK↑
Hold time after CLK↑
ns
ns
su
h
CLKEN low
Data
3.5
0.5
2.5
3.5
0.5
2.5
3.5
0.5
2.5
t
CLKEN high or low
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16823, 74ACT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS160A – APRIL 1991 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T = 25°C
A
54ACT16823
74ACT16823
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
90
TYP
MAX
MIN
90
MAX
MIN
90
MAX
f
t
t
t
t
t
t
t
max
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
4.2
4.8
3.4
2.4
3.3
5.5
4.6
7.5
8.3
7.3
5.9
7.1
7.6
6.7
10.6
11.5
11.2
9.5
4.2
4.8
3.4
2.4
3.3
5.5
4.6
12.1
12.9
12.5
10.7
12.8
10.3
9.4
4.2
4.8
3.4
2.4
3.3
5.5
4.6
12.1
12.9
12.5
10.7
12.8
10.3
9.4
CLK
CLR
OE
Q
Q
Q
ns
ns
11.3
9.7
Q
ns
OE
8.8
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
42
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per flip-flop
C
pF
pd
24
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16823, 74ACT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS160A – APRIL 1991 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
h
t
3 V
su
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
0 V
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
74ACT16823DL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DL
56
56
56
56
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74ACT16823DLG4
74ACT16823DLR
74ACT16823DLRG4
SSOP
SSOP
SSOP
DL
DL
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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www.ti.com/military
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microcontroller.ti.com
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54ACT16823_06 相关器件
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| 54ACT16823_08 | TI | 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS | 获取价格 |
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| 54ACT16824WD | ETC | Logic IC | 获取价格 |
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| 54ACT16825 | TI | 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS | 获取价格 |
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| 54ACT16825DW | TI | 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS | 获取价格 |
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| 54ACT16825_07 | TI | 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS | 获取价格 |
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| 54ACT16825_08 | TI | 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS | 获取价格 |
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| 54ACT16827 | TI | 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS | 获取价格 |
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| 54ACT16827WD | TI | 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS | 获取价格 |
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| 54ACT16827_08 | TI | 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS | 获取价格 |
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