54ACTQ533DM [TI]
ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20;
| 型号： | 54ACTQ533DM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20 驱动 CD 输出元件 |
| 文件： | 总8页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54ACTQ533
Quiet Series Octal Transparent Latch with TRI-STATE®
Outputs
General Description
Features
n ICC and IOZ reduced by 50%
The ACTQ533 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The flip-flops ap-
pear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing re-
quirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus out-
put is in the high impedance state.
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch up immunity
n Eight latches in a single package
n TRI-STATE outputs drive bus lines or buffer memory
address registers
The ACTQ533 utilizes NSC Quiet Series technology to guar-
antee quiet output switching and improve dynamic threshold
n Outputs source/sink 24 mA
n Inverted version of the ACTQ373
n 4 kV minimum ESD immunity
™
™
performance. FACT Quiet Series features GTO output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Logic Symbols
IEEE/IEC
DS100241-1
DS100241-2
Pin
Description
Names
D0–D7
LE
Data Inputs
Latch Enable Input
OE
Output Enable Input
O0–O7
TRI-STATE Latch
Outputs
™
GTO is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
™
FACT Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100241
www.national.com
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100241-4
DS100241-3
Functional Description
Truth Table
The ACTQ533 contains eight D-type latches with TRI-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the stan-
dard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Inputs
Outputs
LE
X
OE
H
L
Dn
On
Z
X
L
H
H
L
H
L
H
X
L
L
O0
=
=
=
=
H
L
Z
X
O
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
=
Previous O before HIGH to Low transition of Latch Enable
0
0
Logic Diagram
DS100241-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
DC Latchup Source
or Sink Current
Junction Temperature (TJ)
CDIP
±
300 mA
175˚C
Supply Voltage (VCC
)
−0.5V to +7.0V
Recommended Operating
Conditions
DC Input Diode Current (IIK
)
=
VI −0.5V
−20 mA
+20 mA
=
VI VCC + 0.5V
Supply Voltage (VCC
)
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
’ACTQ
4.5V to 5.5V
0V to VCC
0V to VCC
DC Output Diode Current (IOK
)
Input Voltage (VI)
=
VO −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
=
VO VCC + 0.5V
Operating Temperature (TA)
54ACTQ
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
Minimum Input Edge Rate ∆V/∆t
±
±
or Sink Current (IO
)
50 mA
’ACTQ Devices
DC VCC or Ground Current
per Output Pin (ICC or IGND
VIN from 0.8V to 2.0V
@
VCC 4.5V, 5.5V
125 mV/ns
)
50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
Storage Temperature (TSTG
)
−65˚C to +150˚C
Note 2: All commercial packaging is not recommended for applications re-
quiring greater than 2000 temperature cycles from −40˚C to +125˚C.
DC Characteristics for ’ACTQ Family Devices
54ACTQ
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to
+125˚C
Guaranteed
Limits
2.0
=
VIH
VIL
Minimum High Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
V
V
V
VOUT 0.1V
2.0
or VCC − 0.1V
=
Maximum Low Level
Input Voltage
0.8
VOUT 0.1V
0.8
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
4.4
IOUT −50 µA
5.4
(Note 3)
=
VIN VIL or VIH
=
IOH −24 mA
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 3)
=
VIN VIL or VIH
=
IOL 24 mA
4.5
5.5
5.5
0.50
0.50
V
=
IOL 24 mA
=
±
IIN
Maximum Input Leakage
Current
1.0
µA
µA
VI VCC, GND
=
±
IOZ
Maximum TRI-STATE
Leakage Current
Maximum
5.5
5.5
5.0
VI VIL, VIH
=
VO VCC, GND
=
VI VCC − 2.1V
ICCT
1.6
mA
I
CC/Input
3
www.national.com
DC Characteristics for ’ACTQ Family Devices (Continued)
54ACTQ
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to
+125˚C
Guaranteed
Limits
50
=
VOLD 1.65V Max
IOLD
IOHD
Minimum Dynamic
5.5
5.5
mA
mA
=
VOHD 3.85V Min
Output Current
(Note 4)
−50
=
ICC
Maximum Quiescent
Supply Current
5.5
5.0
5.0
80.0
1.7
µA
V
VIN VCC
or GND (Note 5)
(Notes 6, 7)
VOLP
Quiet Output
Maximum Dynamic VOL
Quiet Output
VOLV
−1.2
V
(Notes 6, 7)
Minimum Dynamic VOL
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACTQ 25˚C is identical to 74ACQ 25˚C.
Note 5:
I
CC
Note 6: Plastic DIP package.
@
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output GND.
AC Electrical Characteristics
54ACTQ
=
VCC
TA −55˚C
Fig.
No.
Symbol
Parameter
(V)
to +125˚C
Units
=
CL 50 pF
(Note 8)
Min
Max
t
PHL, tPLH
Propagation Delay
Dn to On
5.0
5.0
1.5
1.5
9.0
ns
ns
tPHL, tPLH
Propagation Delay
LE to On
10.5
tPZL, tPZH
PHZ, tPLZ
Output Enable Time
Output Disable Time
5.0
5.0
1.5
1.5
10.5
10.5
ns
ns
t
±
Note 8: Voltage Range 5.0 is 5.0V 0.5V.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
) or LOW to HIGH (t ). Parameter guaranteed by design.
OSHL OSLH
AC Operating Requirements
54ACTQ
=
VCC
TA −55˚C
Fig.
No.
Symbol
Parameter
(V)
to +125˚C
Units
=
(Note 10)
CL 50 pF
Guaranteed
Minimum
3.0
tS
Setup Time, HIGH or LOW
Dn to LE
5.0
5.0
5.0
ns
ns
ns
tH
Hold Time, HIGH or LOW
Dn to LE
1.5
5.0
tW
LE Pulse Width, HIGH
±
Note 10: Voltage Range 5.0 is 5.0V 0.5V.
www.national.com
4
Capacitance
Symbol
Parameter
Typ
4.5
40
Units
pF
Conditions
=
VCC OPEN
CIN
Input Capacitance
Power Dissipation
Capacitance
=
VCC 5.0V
CPD
pF
5
www.national.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明