54F374DC [TI]
F/FAST SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20;
| 型号： | 54F374DC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | F/FAST SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 驱动 CD 输出元件 |
| 文件： | 总11页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1995
54F/74F374
Octal D-Type Flip-Flop with TRI-STATE Outputs
É
General Description
Features
Y
Edge-triggered D-type inputs
The ’F374 is a high-speed, low-power octal D-type flip-flop
featuring separate D-type inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications. A buff-
ered Clock (CP) and Output Enable (OE) are common to all
flip-flops.
Y
Buffered positive edge-triggered clock
Y
TRI-STATE outputs for bus-oriented applications
Guaranteed 4000V minimum ESD protection
Y
Package
Commercial
74F374PC
Military
Package Description
Number
N20A
20-Lead (0.300 Wide) Molded Dual-In-Line
×
54F374DM (QB)
J20A
20-Lead Ceramic Dual-In-Line
74F374SC (Note 1)
74F374SJ (Note 1)
74F374MSA (Note 1)
M20B
M20D
MSA20
W20A
E20A
20-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
20-Lead Molded Shrink Small Outline, EIAJ Type II
20-Lead Cerpack
54F374FM (QB)
54F374LM (QB)
20-Lead Ceramic Leadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
×
SCX, SJX, and MSAX.
Logic Symbols
Connection Diagrams
Pin Assignment for DIP,
SOIC, SSOP and Flatpak
Pin Assignment
for LCC
TL/F/9524–1
IEEE/IEC
TL/F/9524–3
TL/F/9524–2
TL/F/9524–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9524
RRD-B30M75/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin
Description
U.L.
Input I /I
IH IL
Output I /I
Names
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
D –D
0
Data Inputs
1.0/1.0
1.0/1.0
7
CP
OE
Clock Pulse Input (Active Rising Edge)
TRI-STATE Output Enable Input (Active LOW)
b
1.0/1.0
20 mA/ 0.6 mA
b
O –O TRI-STATE Outputs
0 7
150/40 (33.3)
3 mA/24 mA (20 mA)
Functional Description
Truth Table
Inputs
The ’F374 consists of eight edge-triggered flip-flops with in-
dividual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH Clock (CP) transition. With
the Output Enable (OE) LOW, the contents of the eight flip-
flops are available at the outputs. When the OE is HIGH, the
outputs go to the high impedance state. Operation of the
OE input does not affected the state of the flip-flops.
Internal
Output
Register
D
n
CP
OE
O
n
H
L
L
X
L
L
H
L
H
L
L
X
H
X
Z
e
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
Z
High Impedance
e
L
LOW-to-HIGH Clock Transition
Logic Diagram
TL/F/9524–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
b
b
a
65 C to 150 C
Storage Temperature
§
§
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
a
55 C to 125 C
Ambient Temperature under Bias
§
§
§
§
§
§
b
b
a
55 C to 175 C
Junction Temperature under Bias
Plastic
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
a
§
b
a
30 mA to 5.0 mA
Supply Voltage
Military
Commercial
a
a
a
4.5V to 5.5V
e
in HIGH State (with V
CC
Standard Output
0V)
a
4.5V to 5.5V
b
0.5V to 5.5V
0.5V to V
CC
b
a
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
DC Electrical Characteristics
54F/74F
Symbol
Parameter
Units
V
CC
Conditions
Min
Typ
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
e b
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.5
2.4
2.5
2.4
2.7
2.7
I
I
I
I
I
I
1 mA
3 mA
1 mA
3 mA
1 mA
3 mA
CC
CC
CC
CC
OH
OH
OH
OH
OH
OH
54F 10% V
74F 10% V
74F 10% V
V
74F 5% V
74F 5% V
CC
CC
e
e
V
Output LOW
Voltage
54F 10% V
74F 10% V
0.5
I
I
20 mA
24 mA
OL
CC
OL
OL
V
Min
Max
Max
Max
0.0
0.5
CC
e
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
V
V
V
2.7V
IH
IN
mA
mA
mA
V
e
Input HIGH Current
Breakdown Test
54F
74F
100
7.0
7.0V
BVI
IN
e
V
CC
Output HIGH
54F
74F
250
50
CEX
OUT
Leakage Current
e
All Other Pins Grounded
V
ID
Input Leakage
Test
I
1.9 mA
ID
74F
74F
4.75
e
IOD
I
Output Leakage
Circuit Current
V
150 mV
OD
3.75
mA
0.0
All Other Pins Grounded
b
e
0.5V
I
I
I
I
I
I
Input LOW Current
0.6
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
0.0V
Max
V
V
V
V
V
V
IL
IN
e
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
50
2.7V
0.5V
0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
b
e
e
e
50
b
b
60
150
500
86
5.25V
ZZ
e
Power Supply Current
55
HIGH Z
CCZ
O
3
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
50 pF
T
, V
CC
e
Mil
T
, V
A CC
Com
A
e a
Symbol
Parameter
V
Units
CC
e
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
f
Maximum Clock Frequency
Propagation Delay
100
140
60
70
MHz
ns
max
t
t
4.0
4.0
6.5
6.5
8.5
8.5
4.0
4.0
10.5
11.0
4.0
4.0
10.0
10.0
PLH
CP to O
PHL
n
t
t
Output Enable Time
Output Disable Time
2.0
2.0
9.0
5.8
11.5
7.5
2.0
2.0
14.0
10.0
2.0
2.0
12.5
8.5
PZH
PZL
ns
t
t
2.0
1.5
5.3
4.3
7.0
5.5
2.0
1.5
8.0
7.5
2.0
1.5
8.0
6.5
PHZ
PLZ
AC Operating Requirements
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
, V
A CC
Com
Max
Units
A
e a
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
2.0
2.0
2.5
2.0
2.0
2.0
t (L)
s
D to CP
n
ns
ns
t (H)
h
Hold Time, HIGH or LOW
D to CP
n
2.0
2.0
2.0
2.5
2.0
2.0
t (L)
h
t
t
(H)
(L)
CP Pulse Width
HIGH or LOW
7.0
6.0
7.0
6.0
7.0
6.0
w
w
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 374
S
C
X
Temperature Range Family
e
e
54F Military
Special Variations
e
74F Commercial
QB
Military grade device with
environmental and burn-in
processing
Device Type
e
X
Devices shipped in 13 reel
×
Package Code
Temperature Range
e
e
e
e
e
e
e
e
P
D
F
L
S
Plastic DIP
Ceramic DIP
Flatpak
Leadless Chip Carrier (LCC)
Small Outline SOIC JEDEC
Small Outline SOIC EIAJ
Shrink Small Outline (EIAJ SSOP)
a
C
Commercial (0 C to 70 C)
§
§
e
b a
Military ( 55 C to 125 C)
M
§
§
NOTE:
Not required for MSA package code
SJ
MSA
4
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
5
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M20B
20-Lead (0.300 Wide) Molded Small Outline Package, EIAJ (SJ)
×
NS Package Number M20D
6
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Shrink Small Outline Package, EIAJ, Type II (MSA)
×
NS Package Number MSA20
20-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N20A
7
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Products > Military/Aerospace > Logic > FAST > 54F374
Product Folder
54F374
Octal D Flip-Flop with Clock Enable
Contents
l
l
l
l
General Description
Features
Datasheet
Package Availability, Models, Samples
& Pricing
General Description
The 'F374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs
for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock
(CP) and Output Enable (OE#) are common to all flip-flops.
Features
l
l
l
l
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
TRI-STATE outputs for bus-oriented applications
Guaranteed 4000V minimum ESD protection
Datasheet
Size
(in
Kbytes)
Title
Date
Receive via
Email
View
Online
Download
54F374 Octal D-Type Flip-Flop with
TRI-STATE(RM) Outputs
175
Kbytes
9-Dec- View
97 Online
Receive via
Email
Download
54F374 Mil-Aero Datasheet MN54F374-
X
View
Online
Receive via
Email
23 Kbytes
Download
Please use Adobe Acrobat to view PDF file(s).
If you have trouble printing, see Printing Problems.
Package Availability, Models, Samples & Pricing
Budgetary
Pricing
Samples
Package
Models
Std
Pack
Size
&
Part Number
Status
Electronic
Orders
#
$US
each
Type
SPICE IBIS
Quantity
pins
tube
$3.4000 of
50
.
Full
production
Order Parts
54F374LMQB
LCC 20
N/A N/A
50+
tube
$3.4000 of
20
Full
production
54F374DM
Cerdip 20
Cerdip 20
Cerpack 20
Cerdip 20
N/A N/A
N/A N/A
N/A N/A
N/A N/A
.
50+
50+
50+
tube
$1.7000 of
20
.
Full
production
Order Parts
54F374DMQB
54F374FMQB
54F374DC
tube
$2.8000 of
19
.
Full
production
Order Parts
tube
of
N/A
Full
production
.
.
.
.
tube
$4.5000 of
50
Full
production
JM38510/34105B2 LCC 20
JM38510/34105BR Cerdip 20
JM38510/34105BS Cerpack 20
N/A N/A
N/A N/A
N/A N/A
50+
50+
50+
tube
$1.9000 of
20
Full
production
tube
$4.5000 of
19
Full
production
tube
of
N/A
JD54F374SRA
54F374 MW8
Cerdip 20 Preliminary N/A N/A
Full
.
.
wafer
N/A N/A
N/A
production
[Information as of 28-Jul-2000]
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