5962-01-420-4926 [TI]
IC,TIMER,QFP,60PIN,PLASTIC;
| 型号： | 5962-01-420-4926 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,TIMER,QFP,60PIN,PLASTIC |
| 文件： | 总18页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
FS PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
•
PAL-Timing Operation
Solid-State Reliability
Color and Monochrome Operation
Five Selectable-Antiblooming Modes
Variable-Integration-Time Option
Surface-Mount Package
60 59 58 57 56 55 54 53 52 51 50 4948 47 46
1
2
3
4
5
6
7
8
45
BCP1
BCP2
CP1
V
V
X2
CC
CC1
44
43
42
41
40
39
38
Clamp-Pulse Select Option
Horizontal and Vertical Resets for External
Synchronization
CP2
X1
GND
CSYNC
CBLK
BF
V
PI
CC
description
VD
ABIN
GT
PS
NC
S3
S2
S1
T
9
37
36
35
34
33
32
31
SCBLK
IDP
HGATE
TESTA
FI
The SN28837 is a monolithic integrated circuit
10
11
12
13
14
15
designed to supply timing signals for the Texas
Instruments (TI ) 8-mm-diagonal TC276 (PAL
color) and TC277 (PAL monochrome) CCD image
sensors. The SN28837 supplies both CCD-drive
signals and PAL-television synchronization
signals at standard video rates. It requires a
single 5-V supply voltage and a 13.37-MHz
crystal-oscillatorinput. The SN28837 provides the
user with several options including multiple
antiblooming modes, variable-integration time,
external synchronization, clamp-pulse selection,
and delayed horizontal transfer.
SFI
NC
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC – No internal connection
The SN28837 is designed to drive the CCD image sensor through intermediary level-shifting devices such as
the TI TMS3473B parallel driver and the SN28846 serial driver. It also supplies sample-and-hold signals for the
TI TL1593 3-channel sample-and-hold circuit and multiplex signals for the TI TL1051 video preprocessor. In
color applications, the SN28837 interfaces with the SN28838 color-subcarrier generator to generate the PAL
color subcarrier.
The SN28837 is supplied in a 60-pin plastic flat package and is characterized for operation from –20°C to 45°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method3015;however, precautionsshouldbetakentoavoidapplicationofanyvoltagehigherthanmaximum-ratedvoltagestothese
high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in
conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either V
Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices and Assemblies available from Texas Instruments.
or ground.
CC
TI is a trademark of Texas Instruments Incorporated.
Copyright 1991, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
functional block diagram
42
X1
13 MHz
47
50
Oscillator
CLK13M
CLK
43
X2
1
2
3
4
5
6
BCP1
BCP2
CP1
3.3 MHz
Divide
by 4
CP2
CSYNC
CBLK
BF
7
8
48
9
10
12
16
17
28
20
11
12
14
Horizontal
Counter
59
VD
HCR
LSW
SCBLK
IDP
Decoder
Vertical
Counter
TESTA
TESTB
TESTC
VD2
VGATE
HGATE
FI
58
VCR
SFI
49
37
39
36
31
PD
GT
PI
PS
T
Clock
Generator
26
GPS
GP
VDS
SB
27
18
29
Antiblooming
Generator
38
ABIN
21
ABS0
22
ABS1
23
ABS2
32
33
34
51
53
56
57
S1
S2
S3
Serial
Generator
SH1
19
GT3/SH2
GT1/SH3
GT2
E/L
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
Terminal Functions
TERMINAL
NAME
ABIN
I/O
DESCRIPTION
NO.
38
O
Antiblooming in
The levels on these three terminals determine which of the five antiblooming modes is selected:
Mode
ABS2
NC
NC
NC
H
ABS1
ABS0
L
L
H
H
H
Operation
No ABG pulses
2-MHz burst of ABG pulses
1-MHz burst of ABG pulses
1-MHz continuous ABG pulses
2-MHz continuous ABG pulses
ABS0
ABS1
ABS2
21
22
23
I
I
I
0
1
2
3
4
L
H
L
H
H
L
Mode 1 is used for normal operation.
Optical black clamp
BCP1
BCP2
BF
1
2
O
O
O
O
O
O
O
O
O
Optical black clamp
7
Burst flag
CBLK
CLK
6
Composite blank
50
47
3
3.34-MHz clock (factory-test point)
CLK13M
CP1
13-MHz clock (connect to SN28838 color-subcarrier generator for color operation)
Clamp 1 (signal processing)
Clamp 2 (signal processing)
Composite sync
CP2
4
CSYNC
5
Delay select for S1, S2, S3. When E/L is high, the three serial-transfer pulses occur early relative to the
sample-and-holdpulses SH1, SH2, and SH3. When E/L is low, the three serial-transfer pulses occur late
relative to the sample-and-hold pulses.
E/L
19
I
FI
13
41, 60
27
O
Field index
GND
GP
Ground
I
I
Exposure control: GP gates the PS and PI outputs (see the description of GPS)
When GPS is high, the timer operates in the normal-integration-time mode (t = 20 ms) and VD is
int
connected internally to GP. To operate the imager in the variable-integration-time mode, GPS must be
heldlow and a user-defined logic circuit must be inserted between VD and GP to vary the integration time
(see Figure 1).
GPS
26
GT
37
56
57
53
O
O
O
O
TMS3473B parallel-driver MIDSEL input switch
GT1/SH3 is a logic signal for both Y gate 1 of the TL1051 video preprocessor and sample-and-hold
channel 3 of the TL1593 3-channel sample-and-hold circuit.
GT1/SH3
GT2
Y gate 2 for the TL1051 video preprocessor
GT3/SH2 is a logic signal for both Y gate 3 of the TL1051 video preprocessor and sample-and-hold
channel 2 of the TL1593 3-channel sample-and-hold circuit.
GT3/SH2
HCR
HGATE
HIGH
IDP
59
11
25
10
48
I
Horizontal-counter reset
O
I
Decoded H count signal. HGATE is a test point and is not used in normal operation.
Not used (tie high)
O
O
ID pulse (for SECAM operation)
LSW
Line switch (connect to SN28838 for color operation)
15, 30,
35, 46,
NC
No connect
52, 54, 55
PD
PI
49
39
36
O
O
O
Power down. A low-logic level on PD causes the device to enter a low power-consumption mode.
Parallel-image-area gate clock
PS
Parallel-storage-area gate clock
Standby-mode select. When SB is high, normal operation is selected; when SB is low, the power-down
mode is selected.
SB
29
9
I
SCBLK
O
Subcarrier blank (for SECAM applications)
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
SFI
14
O
O
O
O
O
O
O
O
O
Second field index
SH1
S1
51
Sample and hold 1
Serial clock 1
32
S2
33
Serial clock 2
S3
34
Serial clock 3
T
31
Transfer-gate clock
Test A (factory-test point)
Test B (factory-test point)
Test C (factory-test point)
DC power
TESTA
TESTB
TESTC
12
16
17
V
CC
24, 40, 45
VCC1
VCR
VD
44
58
8
Oscillator power
I
Vertical-counter reset
Vertical drive
O
Vertical-dumpspeed. When VDS is high, the vertical-dump frequency is 3.3 MHz; when VDS is low, the
vertical-dump frequency is 2 MHz.
VDS
18
I
VD2
VGATE
X1
28
20
42
43
O
O
Real-display-area signal. VD2 is a test point and is not used in normal operation.
Decoded V count signal. VGATE is a test point and is not used in normal operation.
Crystal oscillator (see Figure 2)
X2
t
int
GP
1
2
3
Flush Pulses
Transfer Pulse
Figure 1. GP Flush and Transfer Pulses
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
variable-integration-time mode
In addition to the normal TV mode of operation, the SN28837 timing generator offers an optional
variable-integration mode for use with the TC276 and TC277 CCD area-array image sensors. The
variable-integration mode is selected by applying a low-logic level to GPS. This low-logic level disables the
vertical-drive (VD) signal from controlling, internal to the timer, the image-area and storage-area parallel transfer
signal (GP).
Prior to the start of a new integration period, the charge that has accumulated in the image area must be
transferred out. To flush this previous signal or dark-current charge from the image area, GP is pulsed low two
times. Each low pulse generates 302 pulses image-area and storage-area gate and transfer signals that shift
the unwanted charge into the clearing drain. This clearing function should be performed during the high time
of the VD signal (see Figure 3 through Figure 13).
The new integration period continues as long as GP remains high. GPS must be held at a low-logic level to
prevent VD from controlling GP internally. The integration ceases and the readout occurs when VD and GP are
pulsed low simultaneously; this is accomplished by taking GPS to a high-logic level. The readout timing is
dependent on the vertical-drive pulse; this means that the total-integration time is a multiple of 1/50 of a second
plus the time interval between the last GP low pulse and the next VD low pulse. The image readout occurs within
the normal 1/50-second readout interval. If the integration time is less than 1/50 of a second, normal output
operation occurs; if the integration time is greater than 1/50 of a second, a frame buffer may be required to
capture the image.
Integration times greater than 1/50 of a second result in image degradation at temperatures greater than 25°C
due to dark-current generation. The degradation is seen as a decrease in dynamic range (contrast) and an
increase in noise. It is recommended that the image sensor be cooled for long-exposure operation. The
dark-current generation is reduced by a factor of two for each 7°C temperature decrease. The sensor operates
at–30°C. CoolingcanbeaccomplishedbyusingathermoelectricorPeltiercoolerattachedtothe imagesensor.
Condensation on the header must be prevented by isolating the cooled sensor from moist air. Vacuum isolation
is preferred; however, the continual flushing of dry nitrogen across the header can also prevent condensation.
SN28837
X1
X2
43
42
C1 ≈ 40 pF
C2 ≈ 40 pF
NOTE: The SN28837 is designed for use with a
crystal oscillator. The X1 and X2
terminals should not connect directly to
external driver outputs.
Figure 2. Connection of an External Crystal Oscillator to the SN28837
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
+ 0.3 V
I
DD
DD
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
O
Continuous total power dissipation at (or below) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mW
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 45°C
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
STG
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN
NOM
MAX
UNIT
V
Supply voltage, V
4.5
5
5.5
DD
High-level input voltage, V
V
DD
x 0.7
V
IH
Low-level input voltage, V
Operating frequency
Power-up time
0.8
V
IL
13.375
300
MHz
µs
Operating free-air temperature, T
–20
45
°C
A
electrical characteristics over recommended operating ranges of supply voltage and free-air
‡
temperature (unless otherwise noted)
PARAMETER
GT3/SH2 and GT1/SH3
All other outputs
TEST CONDITIONS
MIN
3.5
TYP
MAX
UNIT
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
I
I
I
I
= –4 mA
= –2 mA
= 4 mA
DD
DD
DD
DD
OH
OH
OL
OL
V
V
V
OH
3.5
GT3/SH2 and GT1/SH3
All other outputs
0.5
0.5
1
V
OL
§
= 2 mA
I
I
I
I
= 5 V
= 0
µA
µA
IH
IH
IL
–30 –200 –500
IL
Average supply current
Standby supply current
10
1
30
mA
mA
DD(AV)
DD(S)
‡
§
The HCR, SB, and VCR inputs are Schmitt-trigger inputs with 0.1-V to 1-V hysteresis.
All inputs except X1 have pullup-current sources.
switching characteristics over recommended operating free-air temperature range, V
= 5 V
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
4.458333
75
MAX
UNIT
MHz
ns
f
t
Frequency
S1, S2, S3, SH1, GT2, GT1/SH3, GT3/SH2
S1, S2, S3, SH1, GT2, GT1/SH3, GT3/SH2
GT1/SH3 and GT3/SH2
All other outputs
clock
C
C
= 50 pF
= 50 pF
L
L
Pulse duration
w
10
t
Rise time
Fall time
ns
ns
r
f
50
GT1/SH3 and GT3/SH2
All other outputs
10
t
50
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
1st Field
2H
4th Field
1254
1875
1878
1238
1246
EQ
1262
1270
EQ
1278
1286
1294
1302
13101862
1870
1886
1894
1902
1910
1918
1926
Vertical
Scale
1255 12601265
1875 1880 1885 1890
CSYNC
EQ
EQ
VS
1925
VS
1250
1300
1875
CBLK
BF
1248
1268
1872
1892
1250
1875
1890
1265
VD
LSW
1250
1268
1286
1286
1300
1875
1875
1892
1892
1910
1910
1925
SCBLK
1268
IDP
F1
1250
SF1
CP1
1248
1256
1874
1875
1890
1300
1925
1924
1250
CP2
1248
1298
1872
BCP1
1248
1276
1872
1900
BCP2
12431245
13121314
1314
1870
1937
VD2
1939
1867
1242
VGATE
Always Continuous
HGATE
PI
GT
PS, T
ABIN
1248
1298
1872
1924
S1,S2,S3
1250
1276
1874
1900
SH1,GT3/SH2,
GT1/SH3
GT2
NOTES: A. GPS is low and VD is fed back to GP.
B. When GPS is high, VGATE is always low.
C. 1 field = 312 1/2 horizontal lines = 625 vertical counts. 1 frame = 625 horizontal lines = 1250 vertical counts. Period of each count
of vertical counter = 32 µs.
Figure 3. Vertical Timing (First and Fourth Fields)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
3rd Field
2H
2nd Field
625
12 16 20 24 28 32 36 40 44 48 52 56 60 612 616620624 628 632 636 640 644 648 652 656 660 664 668 672 676
2492
2488
2496 0
EQ
4
8
Vertical
Scale
CSYNC
EQ
EQ
EQ
50
675
VS
VS
625
0
CBLK
BF
2496
16
15
620
640
625
0
VD
LSW
0
675
642
660
660
50
625
625
18
18
36
36
SCBLK
642
IDP
FI
0
15
SFI
2498
16
624
640
676
CP1
0
50
48
625
675
CP2
2498
2498
622
622
674
BCP1
26
650
BCP2
VD2
2493
2492
2495
62 64
64
618 620
687 689
689
617
VGATE
Always Continuous
HGATE
PI
GT
2498
48
622
674
PS,T
AB IN
S1,S2,S3
0
0
26
26
624
650
650
SH1, GT1/SH3,
GT3/SH2
624
GT2
NOTES: A. GPS is low and VD is fed back to GP.
B. When GPS is high, VGATE is always low.
C. 1 field = 312 1/2 horizontal lines = 625 vertical counts. 1 frame = 625 horizontal lines = 1250 vertical counts. Period of each count
of vertical counter = 32 µs.
Figure 4. Vertical Timing (Second and Third Fields)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
(214)
192 196 200 204 208 2120
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 96 100 104 108 112 116 120 124
Horizontal
†
Scale
Continuous
CLK
5
21
HSYNC
5
5
13
11
2
120
EQ
VS
CSYNC
11
2
203
96
0
40
CBLK
BF
23.5
31
5
5
LSW
0
0
24
SCBLK
48
IDP
5
21
CP1
0
38
CP2
30
34
BCP1
BCP2
30
34
5
112
HGATE
PS
24
28
0
4
4
8
12 16 20
T
8
12 16 20 24
S1,S2,S3
See Note A
SH1,GT3/SH2,
GT1/SH3
GT2
†
For the horizontal scale (T1 clock), one interval = 299 ns ≥ 4 master-clock periods.
NOTES: A. AlthoughS1, S2, and S3 appear to be coincident, S1 leads S2 by t5 ns, and S2 leads S3 by 75 ns between 4 and 24 on the horizontal
scale.
B. 1 TV line = 64 µs = 214 horizontal clocks
Figure 5. Horizontal Timing
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
T1 = 299 ns
30
28
29
31
32
33
34
35
36
37
38
39
40
Horizontal
Scale
CBLK
4.458333-MHz Pulse
S1
S2
S3
SH1
GT3/SH2
GT1/SH3
GT2
CCD Output
CH1
CH2
CH3
DA
1
DA
2
DA
3
DA
4
DA
5
DA
6
DA
7
DU
1
DU
2
DU
3
DU
4
(2)A
A
A
A
1
2
3
4
0(1)
(1):Not For Use, (2):Half-Dark, DA:Dark, DU:Dummy, A:Active
S/H Output
CH1
CH2
CH3
DA
1
DA
2
DA
3
DA
4
DA
5
DA
6
DA
7
DU
1
DU
2
DU
3
DU
4
A
1
A
A
3
A
2
4
SW-Y Output
Dark
Dummy
Active
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 1
2
3
4
5
6
7
8
9
10 11 12 1
2 3 4 5 6 7 8 9 10
BCP1
BCP2
CP2
NOTE A: This chart shows early mode only. Late mode is shown in Figure 7.
Figure 6. S, SH, GT Timing (Start of H)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
30
29
T1 = 299 ns
T1
S1
S2
S3
±5 ns
±5 ns
Early
±5 ns
37.4 ± 10 ns
S1
S2
±5 ns
±5 ns
Late
±5 ns
S3
±10 ns(S1/SH1)
±5 ns
SH1
±5 ns
GT3/SH2
±5 ns
±5 ns
GT1/SH3
GT2
±5 ns
NOTE A: S1, S2, S3, SH1, GT3/SH2, GT1/SH3, GT2 are:
Cycle time = 224.3 ns
Pulse width = 74.8 ns
Duty cycle = 1/3
Figure 7. S, SH, GT Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
T1 = 299 ns
212 213
(214)
0
211
T1
CBLK
S1
S2
S3
SH1
GT3/SH2
GT1/SH3
GT2
CCD Output
DA 1
DA 1
A
232
CH1
CH2
CH3
233
All Outputs Are Held
Until Next Pulse
S/H Output
DA 1
DA 1
CH1
CH2
CH3
A
232
233
All Outputs Are Held
Until Next Pulse
SW-Y Output
ACTIVE
NOTE A: This chart shows early mode only. Late mode is shown in Figure 7.
Figure 8. S, SH, GT Timing (End of H)
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
H Timing
2T1
T1 = 299 ns
208
206
210 212
0
2
4
6
8
10 12 14 16
18 20 22 24 26 28 30
32 34 36 38 40 42 44
H Counter(T1)
CBLK
BCP1
BCP1
Mode 1
2-MHz Burst
Mode 2
1-MHz Burst
ABIN
Mode 3
Mode 4
1 MHz (0.9554 MHz)
2 MHz (1.9107 MHz)
Always Free Running
V Timing
VD
INTGO
ABCLR
(mode 1, mode 2)
ABIN
(mode 1, mode 2)
ANTIBLOOMING MODE SELECTION
MODE
ABS0
ABS1
ABS2
ABIN OUTPUT
No ABG
0
1
2
3
4
X
X
X
1
0
1
0
1
1
0
0
1
1
1
2 MHz burst
1 MHz burst
1 MHz const
2 MHz const
0
X = Don’t care
NOTES: A. For mode 1 and mode 4, duty cycle is 4/7 high and 3/7 low.
B. Only the timing from odd field to even field is shown. The timing from even field to odd field is the same as that for odd field to even
field minus the H-to-V timing.
C. GPS is always high.
Figure 9. ABIN Timing
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
Powerup Operation
Power
Refresh Pulse
(see Note B)
SB (see Note A)
VD (see Note C)
PI
1026 Pulses
290 Pulses
PS,T
S1,S2,S3
GT
ABIN
Refresh Pulses
(see Note B)
See Note D
Normal Operation
SB
VD (see Note A)
PI
1026 Pulses
290 Pulses
290 Pulses
PS,T
S1,S2,S3
GT
ABIN
PD
NOTES: A. A capacitor is connected to SB (between SB and GND).
B. Refresh pulses (1026 pulses) of PI, PS and T are generated even if VD is not fed back to GP.
C. VD is always fed back to GP and GPS is low.
D. PI, PS, S1, S2, S3, ABIN, and GT go low when SB is low.
Figure 10. Operation Chart of SB
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
VD
GP
290 Pulses
(see Note A)
302 Pulses
(see Note B)
PI
PS,T
GT
ABIN
BCP1, BCP2
Clear
Operation
Operation
Mode
Normal Operation
NOTES: A. When VD is low and GP goes low, 290 pulses are generated for PI, PS, and T after VD goes high.
B. When VD is high, GP goes low and 302 pulses are generated for PI, PS and T.
C. GPS is at a steady-state low level.
Figure 11. Normal Timing and Variable Integration
T1 = 299 ns
n+1
n
n+2
n+3
n+4
m
m+1
m+2 m+3
6
7
8
9
H Counter
CLK
HCR
(see Note A)
Reset Window
m
m+1
m+2 m+3
6
7
8
9
H Counter(T1)
CBLK
HCR
(see Note B)
NOTES: A. The H counter is preset to the value 6 when HCR changes from low to high.
B. Output signals are changed one T1 clock after the change of the counter through the output latches.
Figure 12. Operation of HCR
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
1H = 64 µs
n+3 n+4
n+1
n
n+2
m
m+1
m+2 m+3
16
17
18
19
V Counter
(see Note A)
CLK
VCR
Reset Window
16 17
m
m+1
m+2 m+3
18
19
V Counter
(see Note A)
CLK
VCR
NOTE A: The V counter is preset to the value 16 when VCR changes from low to high.
Figure 13. Operation of VCR
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN28837
1/2-INCH PAL TIMER
SOCS031B – JULY 1991
MECHANICAL DATA
This plastic package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound withstands soldering temperatures with no deformation, and circuit
performance characteristics remain stable when operated in high-humidity conditions. The package is intended for
surface mounting, and leads are spaced on 1,0-mm centers with a 0,8-mm foot length. Leads require no additional
cleaning or processing when used in soldered assembly.
FS060
Designation per JEDEC Std 30:
PQFP-G44
18,2 (0.717)
17,4 (0.685)
14,2 (0.559)
13,8 (0.543)
15
1
Index Corner
Chamfer
16
60
(44 pin used for illustration to save space)
0,20 (0.008)
46
30
2,1 (0.083)
0,10 (0.004)
1,9 (0.075)
0° – 12°
31
45
0,65 (0.026)
0,45 (0.018)
0,95 (0.037)
0,65 (0.026)
1,4 (0.055)
0,8 (0.031)
0,10 (0.004) MIN
Seating Plane
15,0 (0.591) NOM
Detail A
See Detail A
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
7/94
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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