概述
规格参数
数据手册
替代型号5962-8952601LA 概述
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS 同步8位加/减计数器 逻辑芯片 计数器
5962-8952601LA 规格参数
| 生命周期： | Active | 零件包装代码： | DIP |
| 包装说明： | DIP, DIP24,.3 | 针数： | 24 |
| Reach Compliance Code： | not_compliant | HTS代码： | 8542.39.00.01 |
| Factory Lead Time： | 1 week | 风险等级： | 5.29 |
| 其他特性： | RCO OUTPUT; COUNT ENABLE INPUTS | 计数方向： | BIDIRECTIONAL |
| 系列： | AS | JESD-30 代码： | R-GDIP-T24 |
| 长度： | 32 mm | 负载电容（CL）： | 50 pF |
| 负载/预设输入： | YES | 逻辑集成电路类型： | BINARY COUNTER |
| 最大频率@ Nom-Sup： | 40000000 Hz | 最大I（ol）： | 0.02 A |
| 工作模式： | SYNCHRONOUS | 位数： | 8 |
| 功能数量： | 1 | 端子数量： | 24 |
| 最高工作温度： | 125 °C | 最低工作温度： | -55 °C |
| 封装主体材料： | CERAMIC, GLASS-SEALED | 封装代码： | DIP |
| 封装等效代码： | DIP24,.3 | 封装形状： | RECTANGULAR |
| 封装形式： | IN-LINE | 包装方法： | TUBE |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 5 V |
| 最大电源电流（ICC）： | 195 mA | Prop。Delay @ Nom-Sup： | 35 ns |
| 传播延迟（tpd）： | 16 ns | 认证状态： | Not Qualified |
| 筛选级别： | MIL-STD-883 | 座面最大高度： | 5.08 mm |
| 子类别： | Counters | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | NO | 技术： | TTL |
| 温度等级： | MILITARY | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 触发器类型： | POSITIVE EDGE |
| 宽度： | 6.92 mm | 最小 fmax： | 40 MHz |
| Base Number Matches： | 1 |
5962-8952601LA 数据手册
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PDF下载SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
SN54AS867, SN54AS869 . . . JT PACKAGE
• Fully Programmable With Synchronous
SN74ALS867A, SN74ALS869, SN74AS867,
SN74AS869 . . . DW OR NT PACKAGE
(TOP VIEW)
Counting and Loading
• SN74ALS867A and ′AS867 Have
Asynchronous Clear; SN74ALS869 and
′AS869 Have Synchronous Clear
S0
S1
A
B
C
D
E
F
G
V
CC
ENP
1
24
23
22
21
20
19
18
17
16
15
14
13
2
• Fully Independent Clock Circuit
Q
3
Simplifies Use
A
Q
B
4
• Ripple-Carry Output for n-Bit Cascading
Q
5
C
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
Q
D
6
Q
7
E
Q
F
8
Q
9
G
H
ENT
GND
Q
H
CLK
10
11
12
description
RCO
These synchronous, presettable, 8-bit up/down
counters feature internal-carry look-ahead
circuitry for cascading in high-speed counting
applications. Synchronous operation is provided
by having all flip-flops clocked simultaneously so
that the outputs change coincidentally with each
other when so instructed by the count-enable
(ENP, ENT) inputs and internal gating. This mode
of operation eliminates the output counting spikes
normally associated with asynchronous (ripple-
clock) counters. A buffered clock (CLK) input
triggers the eight flip-flops on the rising (positive-
going) edge of the clock waveform.
SN54AS867, SN54AS869 . . . FK PACKAGE
(TOP VIEW)
4
3
2
1 28 27 26
25
B
C
Q
Q
Q
5
B
C
D
24
23
22
21
20
19
6
D
7
NC
E
NC
8
Q
9
E
F
10
11
Q
Q
F
These counters are fully programmable; they may
be preset to any number between 0 and 255. The
load-input circuitry allows parallel loading of the
cascaded counters. Because loading is
synchronous, selecting the load mode disables
the counter and causes the outputs to agree with
the data inputs after the next clock pulse.
G
G
12 13 14 15 16 17 18
NC – No internal connection
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output are instrumental
in accomplishing this function. Both ENP and ENT must be low to count. The direction of the count is determined
by the levels of the select (S0, S1) inputs as shown in the function table. ENT is fed forward to enable RCO. RCO
thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting
up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages.
Transitions at ENP and ENT are allowed regardless of the level of CLK. All inputs are diode clamped to minimize
transmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the
SN74ALS867A and ′AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q
outputs until clocking occurs. For the ′AS867 and ′AS869, any time ENP and/or ENT is taken high, RCO either
goes or remains high. For the SN74ALS867A and SN74ALS869, any time ENT is taken high, RCO either goes
or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely
by the conditions meeting the stable setup and hold times.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
description (continued)
The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of
–55°C to 125°C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
S1
L
S0
L
FUNCTION
Clear
L
H
L
Count down
Load
H
H
H
Count up
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
†
logic symbols
SN74ALS867A
CTRDIV 256
1
S0
S1
0
0
3
2
M
1
13
11
RCO
1,4CT=0
ENT
G4
23
14
3,4CT=255
ENP
CLK
G5
C6/1,4,5–/3,4,5+
0R
3
22
21
20
19
18
17
16
15
Q
A
A
B
C
D
E
F
2,6D
4
Q
B
5
Q
C
6
Q
D
7
Q
E
8
Q
F
9
Q
G
G
H
10
Q
H
SN74ALS869
CTRDIV 256
0
3
1
S0
S1
0
2
M
1
13
11
RCO
ENT
1,4CT=0
G4
23
14
3,4CT=255
ENP
CLK
G5
C6/1,4,5–/3,4,5+
0,6R
3
22
21
20
19
18
17
16
15
Q
A
A
B
C
D
E
F
2,6D
4
Q
B
5
Q
C
6
Q
D
7
Q
E
8
Q
F
9
Q
G
G
H
10
Q
H
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
†
logic symbols (continued)
′AS867
CTRDIV 256
0
3
1
S0
S1
0
2
M
1
13
11
RCO
1,4,5CT=0
3,4,5CT=255
ENT
G4
23
14
ENP
CLK
G5
C6/1,4,5–/3,4,5+
0R
3
22
21
20
19
18
17
16
15
Q
A
A
B
C
D
E
F
2,6D
4
Q
B
5
Q
C
6
Q
D
7
Q
E
8
Q
F
9
Q
G
G
H
10
Q
H
′AS869
CTRDIV 256
0
3
1
S0
S1
0
2
M
1
13
11
RCO
1,4,5CT=0
3,4,5CT=255
ENT
G4
23
14
ENP
CLK
G5
C6/1,4,5–/3,4,5+
0,6R
3
22
21
20
19
18
17
16
15
Q
A
A
B
C
D
E
F
2,6D
4
Q
B
5
Q
C
6
Q
D
7
Q
E
8
Q
F
9
Q
G
G
H
10
Q
H
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
logic diagram (positive logic)
SN74ALS867A, SN74ALS869
14
CLK
1
SN74ALS867A Only
(asynchronous clear)
S0
2
S1
23
ENP
1D
C1
22
R
3
A
Q
Q
Q
Q
A
B
C
D
1D
C1
4
21
20
19
R
B
1D
C1
R
5
C
1D
C1
R
6
D
1D
C1
7
18
17
R
E
Q
Q
E
F
1D
C1
R
8
F
1D
C1
9
16
15
R
G
Q
Q
G
H
1D
C1
10
H
R
13
RCO
11
ENT
Pin numbers shown are for the DW, JT, and NT packages.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
logic diagram (positive logic)
′AS867, ′AS869
1
S0
2
′AS867 Only
(asynchronous clear)
S1
11
ENT
13
22
RCO
23
14
ENP
CLK
Q
Q
Q
Q
A
B
C
D
3
4
5
6
1D
C1
R
A
B
C
D
21
20
19
1D
C1
R
1D
C1
R
1D
C1
R
18
17
16
15
Q
Q
Q
Q
E
F
7
1D
C1
R
E
F
8
1D
C1
R
G
H
9
1D
C1
R
G
H
10
1D
C1
R
Pin numbers shown are for the DW, JT, and NT packages.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
typical clear, preset, count, and inhibit sequences
The following sequence is illustrated below:
1. Clear outputs to zero (SN74ALS867A and ′AS867 are asynchronous;
SN74ALS869 and ′AS869 are synchronous.)
2. Preset to binary 252
3. Count up to 253, 254, 255, 0, 1, and 2
4. Count down to 1, 0, 255, 254, 253, and 252
5. Inhibit
S0
S1
A
B
C
D
Data
Inputs
E
F
G
H
CLK
ENP
ENT
Q
A
Q
B
Q
C
Q
D
Outputs
Q
E
Q
F
Q
G
Q
H
RCO
Sync
Clear
252 253 254 255
0
1
2
1
0
255 254 253 252
Count Down
†
Count Up
Inhibit
Async
Preset
Clear
†
ENT and ENP both must be low for counting to occur.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN74ALS867A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74ALS867A
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
IH
0.8
–0.4
8
V
IL
I
I
f
t
t
High-level output current
Low-level output current
Clock frequency
mA
mA
MHz
ns
OH
OL
0
14
10
10
15
12
12
12
3
35
clock
w(clock)
w(clear)
Pulse duration, CLK high or low
Pulse duration of clear pulse, S0 and S1 low
ns
Data inputs A–H
ENP or ENT
t
su
S0 low and S1 high (load)
S0 high and S1 low (count down)
S0 and S1 high (count up)
S0 high after S1↑ or S1 high after S0↑
Data inputs A–H
ns
Setup time before CLK↑
t
h
ns
Hold time after CLK↑
0
T
A
Operating free-air temperature
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS867A
PARAMETER
TEST CONDITIONS
UNIT
‡
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
V
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
CC
–2
OH
CC
OH
OL
OL
0.25
0.35
0.4
0.5
V
OL
V
CC
= 4.5 V
V
= 8 mA
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V
V = 7 V
0.1
mA
µA
I
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.2
–112
45
mA
mA
mA
§
V
O
= 2.25 V
–30
O
28
CC
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
†
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN74ALS867A
MIN
35
4
MAX
f
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PLH
PHL
PLH
14
14
16
16
14
9
CLK
CLK
RCO
4
3
Any Q
ns
3
3
ns
ns
ns
ns
ENT
RCO
2
S0 or S1 (clear mode)
Any Q
8
26
16
16
16
4
S0 or S1
(count up/down)
RCO
RCO
4
S0 or S1 (clear mode)
4
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN74ALS869 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74ALS869
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.8
–0.4
8
V
IL
I
I
f
t
mA
mA
MHz
ns
OH
OL
0
14
10
15
13
13
13
13
3
35
clock
w(clock)
Pulse duration, CLK high or low
Data inputs A–H
ENP or ENT
S0 and S1 low (clear)
t
su
ns
Setup time before CLK↑
S0 low and S1 high (load)
S0 high and S1 low (count down)
S0 and S1 high (count up)
S0 high after S1↑ or S1 high after S0↑
Data inputs A–H
t
h
ns
Hold time after CLK↑
0
T
A
Operating free-air temperature
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS869
PARAMETER
TEST CONDITIONS
UNIT
‡
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
V
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
CC
–2
OH
CC
OH
OL
OL
0.25
0.35
0.4
0.5
V
OL
V
CC
= 4.5 V
V
= 8 mA
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V
V = 7 V
0.1
mA
µA
I
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.2
–112
45
mA
mA
mA
§
V
O
= 2.25 V
–30
O
28
CC
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
†
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN74ALS869
MIN MAX
35
f
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
4
4
3
3
3
2
4
4
4
4
14
14
16
16
14
9
CLK
CLK
ENT
RCO
Any Q
ns
ns
ns
ns
RCO
RCO
RCO
15
15
16
12
S1
(count up/down)
S0
(clear/load)
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54AS867 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74AS867 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS867
MIN NOM
SN74AS867
MIN NOM
UNIT
MAX
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
IH
0.8
–2
20
40
0.8
–2
20
50
V
IL
I
I
f
t
t
High-level output current
Low-level output current
Clock frequency
mA
mA
MHz
ns
OH
OL
clock
*
0
12.5
12.5
5
0
10
10
4
*
Pulse duration, CLK high or low
Pulse duration of clear pulse, S0 and S1 low
w(clock)
*
ns
w(clear)
Data inputs A–H
ENP or ENT
9
8
S0 low and S1 high (load)
S0 and S1 low (clear)
S0 high and S1 low (count down)
S0 and S1 high (count up)
Data inputs A–H
11
10
10
40
40
0
t
*
ns
Setup time before CLK↑
su
11
42
42
0
t *
h
Hold time after CLK↑
ns
ns
°C
Skew time between S0 and S1
t
*
8
7
skew
(maximum to avoid inadvertent clear)
T
Operating free-air temperature
–55
125
0
70
A
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS867
SN74AS867
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
V
IK
CC
I
= 4.5 V to 5.5 V,
I
= –2 mA
V
CC
–2
V
CC
–2
OH
CC
OH
OL
I
V
= 20 mA,
on ENT = 0.7 V
0.34
0.5
RCO
IL
V
OL
V
CC
= 4.5 V
V
Other outputs
I
= 20 mA
0.34
0.5
0.1
OL
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 7 V
0.1
40
mA
I
CC
I
ENT
40
V = 2.7 V
µA
IH
IL
CC
I
Other inputs
ENT
20
20
–4
–4
I
V
CC
= 5.5 V,
V = 0.4 V
mA
I
Other inputs
–2
–2
‡
I
I
V
V
= 5.5 V,
= 5.5 V
V = 2.25 V
O
–30
–112
195
–30
–112
195
mA
mA
O
CC
134
134
CC
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
§
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54AS867
SN74AS867
MIN
40
5
MAX
MIN
50
5
MAX
f
t
t
t
t
t
t
t
t
t
*
MHz
ns
max
31
19
12
16
19
21
16
21
23
22
16
11
15
10
17
14
17
21
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
CLK
CLK
RCO
6
6
3
3
Any Q
ns
ns
4
4
3
3
ENT
RCO
5
5
5
5
ns
ns
ENP
RCO
5
5
Clear (S0 or S1 low)
Any Q
7
7
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54AS869 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74AS869 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS869
MIN NOM
SN74AS869
MIN NOM
UNIT
MAX
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.7
–2
20
40
0.8
–2
20
45
V
IL
I
I
f
t
mA
mA
MHz
ns
OH
OL
clock
*
*
Pulse duration, CLK high or low
12.5
6
11
5
w(clock)
Data inputs A–H
ENP or ENT
10
13
13
52
52
0
9
S0 low and S1 high (load)
S0 and S1 low (clear)
S0 high and S1 low (count down)
S0 and S1 high (count up)
Data inputs A–H
11
11
50
50
0
t *
su
ns
Setup time before CLK↑
t *
h
Hold time after CLK↑
ns
T
A
Operating free-air temperature
–55
125
0
70
°C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS869
SN74AS869
PARAMETER
TEST CONDITIONS
UNIT
V
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 4.5 V,
I = –18 mA
I
–1.2
–1.2
IK
CC
CC
CC
= 4.5 V to 5.5 V,
= 4.5 V,
I
I
I
= –2 mA
= –2 mA
V
CC
–2
OH
OH
OL
V
OH
V
CC
–2*
= 20 mA,
on ENT = 0.7 V
0.34
0.5
RCO
V
IL
V
OL
V
CC
= 4.5 V
V
Other outputs
I
= 20 mA
0.34
0.5
0.1
OL
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 7 V
0.1
40
mA
I
CC
I
ENT
40
V = 2.7 V
µA
IH
IL
CC
I
Other inputs
ENT
20
20
–4
–4
I
V
CC
= 5.5 V,
V = 0.4 V
mA
I
Other inputs
–2
–2
‡
I
I
V
V
= 5.5 V,
= 5.5 V
V = 2.25 V
O
–30
–112
195
–30
–112
195
mA
mA
O
CC
134
134
CC
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
§
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54AS869
SN74AS869
MIN
40
6
MAX
MIN
45
6
MAX
f
t
t
t
t
t
t
t
t
*
MHz
ns
max
35
20
12
16
25
21
27
21
35
18
11
15
15
17
19
18
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
CLK
CLK
RCO
6
6
3
3
Any Q
ns
ns
ns
4
4
3
3
ENT
ENP
RCO
RCO
6
6
5
5
6
6
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
5962-89526013A
5962-8952601KA
5962-8952601LA
5962-89668013A
5962-8966801KA
5962-8966801LA
SN54AS867JT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
28
24
24
28
24
24
24
24
24
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
W
A42
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CFP
JT
A42 SNPB
FK
POST-PLATE N / A for Pkg Type
W
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
CDIP
CDIP
CDIP
SOIC
JT
A42 SNPB
A42 SNPB
A42 SNPB
JT
SN54AS869JT
JT
SN74ALS867ADW
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS867ADWE4
SN74ALS867ADWR
SN74ALS867ADWRE4
SN74ALS867ANT
SN74ALS867ANTE4
SN74ALS869DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
DW
DW
DW
NT
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NT
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
DW
DW
DW
DW
NT
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS869DWE4
SN74ALS869DWR
SN74ALS869DWRE4
SN74ALS869NT
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ALS869NTE4
SN74AS867DW
NT
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
DW
DW
DW
DW
NT
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AS867DWE4
SN74AS867DWR
SN74AS867DWRE4
SN74AS867NT
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AS867NT3
SN74AS867NTE4
OBSOLETE
ACTIVE
PDIP
PDIP
NT
NT
24
24
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AS869DW
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AS869DWE4
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
SN74AS869DWR
SN74AS869DWRE4
SN74AS869NT
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
DW
DW
NT
24
24
24
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AS869NT3
SN74AS869NTE4
OBSOLETE
ACTIVE
PDIP
PDIP
NT
NT
24
24
TBD
Call TI Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
SNJ54AS867FK
SNJ54AS867JT
SNJ54AS867W
SNJ54AS869FK
SNJ54AS869JT
SNJ54AS869W
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
JT
W
28
24
24
28
24
24
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
LCCC
CDIP
CFP
FK
JT
W
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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5962-8952601LA CAD模型
引脚图
封装焊盘图
5962-8952601LA 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| SN54AS867JT | TI | SYNCHRONOUS 8-BIT UP/DOWN COUNTERS | 完全替代 |
|
| SN54AS869JT | TI | SYNCHRONOUS 8-BIT UP/DOWN COUNTERS | 完全替代 |
|
| 5962-8966801LA | TI | SYNCHRONOUS 8-BIT UP/DOWN COUNTERS | 完全替代 |
|
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