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5962-8974601CA [TI]

High Speed CMOS Logic 8-Input NAND Gate; 高速CMOS逻辑8输入与非门
5962-8974601CA
型号： 5962-8974601CA
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High Speed CMOS Logic 8-Input NAND Gate
高速CMOS逻辑8输入与非门

栅极 逻辑集成电路
文件： 总13页 (文件大小：348K)
中文：  中文翻译
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CD54/74HC30,  
CD54/74HCT30  
Data sheet acquired from Harris Semiconductor  
SCHS121D  
High Speed CMOS Logic  
8-Input NAND Gate  
August 1997 - Revised September 2003  
Features  
Description  
• Buffered Inputs  
The ’HC30 and ’HCT30 each contain an 8-input NAND gate  
in one package. They provide the system designer with the  
direct implementation of the positive logic 8-input NAND  
function. Logic gates utilize silicon gate CMOS technology to  
achieve operating speeds similar to LSTTL gates with the  
low power consumption of standard CMOS integrated cir-  
cuits. All devices have the ability to drive 10 LSTTL loads.  
The HCT logic family is functionally pin compatible with the  
• Typical Propagation Delay: 10ns at V  
o
= 5V,  
[ /Title  
(CD54H  
C30,  
CD74H  
C30,  
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C standard LS logic family.  
CD74H  
CT30)  
/Subject  
(High  
Speed  
CMOS  
Logic 8-  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
PART NUMBER  
CD54HC30F3A  
CD54HCT30F3A  
CD74HC30E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
• HC Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
CD74HC30M  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOP  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
CD74HC30MT  
CD74HC30M96  
CD74HC30NSR  
CD74HC30PW  
CD74HC30PWR  
CD74HC30PWT  
CD74HCT30E  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld PDIP  
Pinout  
CD54HC30, CD54HCT30 (CERDIP)  
CD74HC30 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT30 (PDIP, SOIC)  
TOP VIEW  
A
B
1
2
3
4
5
6
7
14  
V
CD74HCT30M  
CD74HCT30MT  
CD74HCT30M96  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
CC  
13 NC  
C
12  
11  
H
G
D
E
10 NC  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
F
9
8
NC  
Y
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated.  
1
CD54/74HC30, CD54/74HCT30  
Functional Diagram  
1
A
2
B
3
C
4
8
D
Y
5
6
E
F
11  
12  
Y = ABCDEFGH  
G
H
TRUTH TABLE  
INPUTS  
A
L
B
X
L
C
X
X
L
D
E
X
X
X
X
L
F
X
X
X
X
X
L
G
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
L
OUTPUT  
X
X
X
L
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
H
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
H
X
X
X
H
X
X
H
X
H
H
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant  
Logic Symbol  
1
A
2
B
3
C
4
D
8
Y
5
E
6
F
11  
G
12  
H
2
CD54/74HC30, CD54/74HCT30  
Absolute Maximum Ratings  
Thermal Information  
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Package Thermal Impedance, θ (see Note 1)  
JA  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
o
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 C/W  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 C/W  
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 C/W  
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . .113 C/W  
IK  
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
o
DC Output Diode Current, I  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
O
o
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
o
o
DC V  
or Ground Current, I  
I
. . . . . . . . . . . . . . . . . .±50mA  
CC  
CC or GND  
o
(SOIC - Lead Tips Only)  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO +85 C -55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
High Level Input  
Voltage  
V
-
-
-
2
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
4.5  
3.15  
-
-
3.15  
-
-
3.15  
6
2
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
-0.02  
2
1.9  
1.9  
1.9  
OH  
IH  
V
IL  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
IH  
V
IL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
3
CD54/74HC30, CD54/74HCT30  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO +85 C -55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
2
-
20  
-
40  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
IH  
-0.02  
4.5  
4.5  
4.5  
4.5  
5.5  
5.5  
4.4  
4.4  
4.4  
OH  
V
IL  
High Level Output  
Voltage  
TTL Loads  
-4  
3.98  
-
-
-
-
3.84  
-
3.7  
-
V
V
Low Level Output  
Voltage  
CMOS Loads  
V
V
or  
IH  
-0.02  
-
-
-
0.1  
-
-
-
0.1  
0.33  
±1  
-
-
-
0.1  
0.4  
±1  
OL  
V
IL  
Low Level Output  
Voltage  
TTL Loads  
4
-
0.26  
±0.1  
V
Input Leakage  
Current  
I
V
µA  
I
CC  
and  
GND  
Quiescent Device  
Current  
I
V
or  
0
-
-
-
-
2
-
-
20  
-
-
40  
µA  
µA  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
(Note 2)  
∆I  
CC  
V
4.5 to  
5.5  
100  
360  
450  
490  
CC  
-2.1  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
All  
UNIT LOADS  
0.6  
NOTE: Unit Load is ∆I  
Specifications table, e.g. 360µA max at 25 C.  
limit specified in DC Electrical  
o
CC  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Propagation Delay, Input to  
Output (Figure 1)  
t
, t  
PLH PHL  
C = 50pF  
2
4.5  
6
-
-
-
-
-
-
130  
26  
22  
-
-
-
-
-
165  
33  
28  
-
-
-
-
-
195  
39  
33  
-
ns  
ns  
ns  
ns  
L
-
Propagation Delay, Data Input to  
Output Y  
t , t  
PLH PHL  
C = 15pF  
5
10  
L
4
CD54/74HC30, CD54/74HCT30  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
95  
19  
16  
10  
-
MIN  
MAX  
110  
22  
UNITS  
ns  
Transition Times (Figure 1)  
t
, t  
TLH THL  
C = 50pF  
L
2
4.5  
6
-
-
-
-
-
-
-
75  
15  
13  
10  
-
-
-
-
-
-
-
-
-
-
-
ns  
-
19  
ns  
Input Capacitance  
C
-
-
-
-
10  
pF  
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
5
25  
-
pF  
PD  
HCT TYPES  
Propagation Delay, Input to  
Output (Figure 2)  
t
, t  
C = 50pF  
4.5  
5
-
-
-
28  
-
-
-
35  
-
-
-
42  
-
ns  
ns  
RHL PHL  
L
Propagation Delay, Data Input to  
Output Y  
t
, t  
C = 15pF  
11  
PLH PHL  
L
Transition Times (Figure 2)  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
L
4.5  
-
-
-
-
-
-
15  
10  
-
-
-
-
19  
10  
-
-
-
-
22  
10  
-
ns  
pF  
pF  
C
-
-
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
5
26  
PD  
NOTES:  
3. C  
is used to determine the dynamic power consumption, per gate.  
2
PD  
4. P = V  
f (C  
PD  
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.  
CC  
D
CC  
i
L
i
L
Test Circuits and Waveforms  
t = 6ns  
t = 6ns  
f
t = 6ns  
f
t = 6ns  
r
r
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
TLH  
t
t
THL  
THL  
TLH  
90%  
50%  
10%  
90%  
1.3V  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
t
t
PHL  
PLH  
PHL  
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
5
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Feb-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
CDIP  
CDIP  
PDIP  
Drawing  
5962-8974601CA  
8404001CA  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
14  
14  
14  
14  
14  
14  
1
1
None  
None  
None  
None  
None  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
CD54HC30F  
J
1
CD54HC30F3A  
CD54HCT30F3A  
CD74HC30E  
J
1
J
1
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HC30M  
CD74HC30M96  
CD74HC30MT  
CD74HC30NSR  
CD74HC30PW  
CD74HC30PWR  
CD74HC30PWT  
CD74HCT30E  
CD74HCT30M  
CD74HCT30M96  
CD74HCT30MT  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SO  
D
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
50  
2500  
250  
2000  
90  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
D
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
NS  
PW  
PW  
PW  
N
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
TSSOP  
TSSOP  
TSSOP  
PDIP  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
2000  
250  
25  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
SOIC  
SOIC  
SOIC  
D
50  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
D
2500  
250  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
D
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional  
product content details.  
None: Not yet available Lead (Pb-Free).  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,  
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Feb-2005  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
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Addendum-Page 2  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°–8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
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