5962-89757013A [TI]
8 位幅度比较器 | FK | 28 | -55 to 125;
| 型号： | 5962-89757013A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 位幅度比较器 | FK | 28 | -55 to 125 运算电路 比较器 |
| 文件： | 总18页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
SN54AS885 . . . JT PACKAGE
SN74AS885 . . . DW OR NT PACKAGE
(TOP VIEW)
• Latchable P-Input Ports With Power-Up
Clear
• Choice of Logical or Arithmetic
(Two’s Complement) Comparison
L/A
P < QIN
P > QIN
Q7
V
CC
23 PLE
1
2
3
4
5
6
7
8
9
24
• Data and PLE Inputs Utilize pnp Input
Transistors to Reduce dc Loading Effects
22 P7
21 P6
• Approximately 35% Improvement in
ac Performance Over Schottky TTL While
Performing More Functions
Q6
Q5
Q4
Q3
20 P5
19 P4
18 P3
• Cascadable to n Bits While Maintaining
17 P2
High Performance
Q2
16 P1
• 10% Less Power Than STTL for an 8-Bit
Q1 10
Q0 11
15 P0
Comparison
14 P < QOUT
13 P > QOUT
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
GND 12
SN54AS885 . . . FK PACKAGE
(TOP VIEW)
description
These advanced Schottky devices are capable of
performing high-speed arithmetic or logic
comparisons on two 8-bit binary or two’s
complement words. Two fully decoded decisions
about words P and Q are externally available at
two outputs. These devices are fully expandable
to any number of bits without external gates. To
compare words of longer lengths, the P > QOUT
and P < QOUT outputs of a stage handling less
significant bits can be connected to the P > QIN
and P < QIN inputs of the next stage handling
more significant bits. The cascading paths are
implemented with only a two-gate-level delay to
reduce overall comparison times for long words.
Two alternative methods of cascading are shown
in application information.
4
3
2
1
28 27 26
25
Q7
Q6
Q5
NC
Q4
Q3
Q2
P6
P5
P4
NC
P3
P2
P1
5
24
23
22
21
20
19
6
7
8
9
10
11
12 13 14 15 16 17 18
NC – No internal connection
The latch is transparent when P latch-enable
(PLE) input is high; the P-input port is latched
when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry
is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE,
P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically
–0.25 mA, which minimizes dc loading effects.
The SN54AS885 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AS885 is characterized for operation from 0°C to 70°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
FUNCTION TABLE
INPUTS
OUTPUTS
DATA
COMPARISON
L/A
P0–P7, P > QIN P < QIN P > QOUT P < QOUT
Q0–Q7
Logical
Logical
H
H
H
L
P > Q
P < Q
X
X
X
X
H
L
L
H
†
Logical
P = Q
H or L
X
H or L
X
H or L
H
H or L
L
Arithmetic
Arithmetic
P AG Q
Q AG P
P = Q
L
X
X
L
H
†
Arithmetic
L
H or L
H or L
H or L
H or L
†
In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.
AG = arithmetically greater than
‡
logic symbol
1
COMP
L/A
M [LOGIC]
M [ARITH, 2s COMP]
C1
23
15
16
17
18
19
20
21
22
3
PLE
P0
1D
1=0
0
P1
P2
P3
P
P4
P5
13
14
P6
P > Q
P < Q
P > QOUT
P < QOUT
P7
7
P > QIN
P < QIN
Q0
>
<
0
2
11
10
9
Q1
Q2
8
Q3
7
Q
Q4
6
Q5
5
Q6
4
Q7
7
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
logic diagram (positive logic)
23
P7 = Q7
P6 = Q6
PLE
P7
C1
1D
P7
22
21
20
19
P7
P6
P6
P6
P5
P5 = Q5
P5
P4
P3
P2
P1
P5
P4
P3 = Q3
P4
P3
18
17
P2 = Q2
P1 = Q1
P3
P2
14
P2
P1
P < QOUT
16
15
P0 = Q0
P1
P0
P0
P0
Q7
4
5
Q7
Q6
Q7
Q6
Q6
Q5
6
7
Q5
Q4
13
Q5
Q4
P > QOUT
Q4
Q3
8
9
Q3
Q2
Q3
Q2
4MSB =
Q2
Q1
10
11
Q1
Q0
Q1
Q0
Q0
3
2
P > QIN
P < QIN
1
ARITH
LOGIC
L/A
Pin numbers shown are for the DW, JT, and NT packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54AS885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74AS885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS885
MIN NOM
SN74AS885
MIN NOM
UNIT
MAX
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Setup time, data before PLE↓
Hold time, data after PLE↓
Operating free-air temperature
IH
0.8
–2
20
0.8
–2
20
V
IL
I
I
t
mA
mA
ns
ns
°C
OH
OL
*
2
4.5
2
4
0
su
t *
h
T
A
–55
125
70
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS885
SN74AS885
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
V
IK
CC
CC
CC
CC
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
I
= –2 mA
= 20 mA
V
CC
–2
V
CC
–2
OH
OL
OH
OL
0.35
0.5
0.1
40
0.35
0.5
0.1
40
V
I
I
= 5.5 V,
V = 7 V
I
mA
L/A
I
IH
V
CC
= 5.5 V,
V = 2.7 V
I
µA
Others
20
20
L/A
–4
–4
I
IL
P > QIN, P < QIN
P, Q, PLE
V
CC
= 5.5 V,
V = 0.4 V
I
–2
–2
mA
–1
–1
§
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 2.25 V
O
–20
–112
210
–20
–112
210
mA
mA
O
CC
See Note 1
130
130
CC
CC
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
NOTE 1:
I
is measured with all inputs high except L/A, which is low.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
switching characteristics (see Figure 3)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
= 500 Ω,
CC
L
L
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54AS885
SN74AS885
†
†
MIN TYP
MAX
14
MIN TYP
MAX
13
t
t
t
t
t
t
2
2
2
2
2
2
8.5
7.5
5
1
1
1
1
1
1
8.5
7.5
5
PLH
PHL
PLH
PHL
PLH
PHL
P < QOUT,
P > QOUT
ns
ns
ns
L/A
14
13
10
8
P < QIN,
P > QIN
P < QOUT,
P > QOUT
5.5
13.5
10
10
5.5
13.5
10
8
21
17.5
15
Any P or Q
data input
P < QOUT,
P > QOUT
17
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
APPLICATION INFORMATION
The ′AS885 can be cascaded to compare words longer than eight bits. Figure 1 shows the comparison of two 32-bit
words; however, the design is expandable to n bits. Figure 1 shows the optimum cascading arrangement for
comparing words of 32 bits or greater. Typical delay times shown are at V
= 5 V, T = 25°C and use the standard
CC
A
advanced Schottky load of R = 500 Ω, C = 50 pF.
L
L
Figure 2 shows the fastest cascading arrangement for comparing 16-bit or 24-bit words. Typical delay times shown
are at V = 5 V, T = 25°C and use the standard advanced Schottky load of R = 500 Ω, C = 50 pF.
CC
A
L
L
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
APPLICATION INFORMATION
PLE
1
′AS885
L/A
PLE 23
15
P0
16
P1
17
P2
18
P3
19
P4
20
P5
21
P6
13
14
P > QOUT
P < QOUT
22
P7
P > QIN
3
2
P < QIN
1
′AS885
H or L
L/A
11
10
9
Q0
PLE 23
Q1
Q2
Q3
15
P0
8
16
P1
7
17
Q4
Q5
Q6
Q7
P2
6
18
P3
5
19
P4
4
20
P5
PLE
21
P6
22
13
14
P7
P > QIN
P > QOUT
P < QOUT
1
′AS885
L/A
3
2
P < QIN
H or L
PLE 23
11
10
9
Q0
15
16
17
18
19
20
21
22
3
P0
P1
P2
1
′AS885
Q1
Q2
Q3
L/A
8
PLE 23
P3
P4
P5
7
15
P0
Q4
Q5
Q6
Q7
6
16
P1
5
17
P2
P6
P7
4
18
P3
13
14
P > QOUT
P < QOUT
P > QOUT
P < QOUT
19
P4
P > QIN
P < QIN
Q0
20
2
P5
H or L
21
P6
13
14
11
10
9
P > QOUT
P < QOUT
22
P7
P > QIN
Q1
Q2
3
2
P < QIN
1
′AS885
8
H or L
L/A
Q3
Q4
Q5
11
10
9
7
Q0
PLE 23
6
Q1
Q2
Q3
15
P0
5
Q6
Q7
8
16
4
P1
7
17
Q4
Q5
Q6
Q7
P2
6
18
P3
5
19
P4
4
20
P5
21
P6
22
13
14
P7
P > QIN
P > QOUT
P < QOUT
3
2
P < QIN
H or L
11
10
9
Q0
Q1
Q2
Q3
8
7
Q4
Q5
Q6
Q7
6
5
4
13.5 ns
Typical
13.5 ns
Typical
Figure 1. 32-Bit to 72 (n)-Bit Magnitude Comparator
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
APPLICATION INFORMATION
Latch
Enable
1
1
1
′AS885
′AS885
′AS885
L/A
L/A
L/A
PLE 23
PLE 23
PLE 23
15
16
17
15
16
17
15
16
17
P0
P1
P2
P0
P1
P2
P0
P1
P2
18
18
18
P3
P3
P3
19
P4
19
P4
19
P4
20
P5
20
P5
20
P5
21
P6
21
P6
21
P6
22
22
22
P7
P > QIN
P < QIN
P7
P > QIN
P < QIN
P7
P > QIN
P < QIN
3
2
11
10
9
3
2
11
10
9
3
2
11
10
9
13
14
13 MSB
14
13
14
P > QOUT
P < QOUT
P > QOUT
P < QOUT
P > QOUT
P < QOUT
H or L
LSB
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
8
7
8
7
8
7
Q3
Q4
Q5
Q6
6
5
4
6
5
4
6
5
4
MSB Q7
LSP
MSP
16 Bit
19 ns
Typical
24 Bit
24.4 ns
Typical
Figure 2. Fastest Cascading Arrangement for Comparing 16-Bit or 24-Bit Words
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 3. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
5962-89757013A
5962-8975701KA
5962-8975701LA
SN54AS885JT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
28
24
24
24
24
1
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
W
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
CDIP
CDIP
SOIC
JT
A42 SNPB
A42 SNPB
JT
SN74AS885DW
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AS885DWE4
SN74AS885DWG4
SN74AS885DWR
SN74AS885DWRE4
SN74AS885DWRG4
SN74AS885NT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
DW
DW
DW
DW
DW
NT
24
24
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AS885NT3
SN74AS885NTE4
OBSOLETE
ACTIVE
PDIP
PDIP
NT
NT
24
24
TBD
Call TI Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
SNJ54AS885FK
SNJ54AS885JT
SNJ54AS885W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
JT
W
28
24
24
1
1
1
TBD
TBD
TBD
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2007
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
SN74AS885DWR
DW
24
SITE 60
330
24
10.75
15.7
2.7
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74AS885DWR
DW
24
SITE 60
346.0
346.0
0.0
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明