5962-9050101VEA [TI]
并联负载 8 位移位寄存器 | J | 16 | -55 to 125;
| 型号： | 5962-9050101VEA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 并联负载 8 位移位寄存器 | J | 16 | -55 to 125 移位寄存器 |
| 文件： | 总33页 (文件大小：2180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
SNx4HC166 8 位并行负载移位寄存器
1 特性
2 说明
• 2V 至6V 的宽工作电压范围
• 输出可驱动多达10 个LSTTL 负载
• 低功耗，ICC 最大值为80μA
• tpd 典型值= 13ns
• ±4mA 输出驱动（在5V 时）
• 低输入电流，最大值1µA
• 同步负载
SNx4HC166 器件包含一个8 位移位寄存器，具有一路
串行输入和八路并行负载输入。
器件信息
零件编号
封装(1)
封装尺寸（标称值）
9.90mm × 3.90mm
6.20mm × 5.30mm
19.31mm × 6.35mm
6.20mm × 5.30mm
5.00mm × 4.40mm
24.38mm × 6.92mm
8.89mm × 8.45mm
10.16mm × 6.73mm
SN74HC166D
SN74HC166DB
SN74HC166N
SN74HC166NS
SN74HC166PW
SN54HC166J
SNJ54HC166FK
SNJ54HC166J
SOIC (16)
SSOP (16)
PDIP (16)
SO (16)
• 直接覆盖清零
• 并行转串行转换
TSSOP (16)
CDIP (16)
LCCC (20)
CFP (16)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
功能框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS117
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
Table of Contents
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Device Functional Modes............................................9
8 Power Supply Recommendations................................10
9 Layout.............................................................................10
9.1 Layout Guidelines..................................................... 10
10 Device and Documentation Support..........................11
10.1 接收文档更新通知................................................... 11
10.2 支持资源..................................................................11
10.3 Trademarks............................................................. 11
10.4 Electrostatic Discharge Caution..............................11
10.5 术语表..................................................................... 11
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 说明................................................................................... 1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(1) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements .................................................6
5.6 Switching Characteristics ...........................................7
5.7 Operating Characteristics........................................... 7
6 Parameter Measurement Information............................8
7 Detailed Description........................................................9
Information.................................................................... 11
3 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (December 1982) to Revision E (February 2022)
Page
• 更新了整个文档中的编号、格式、表格、图和交叉参考，以反映现代数据表标准..............................................1
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: SN54HC166 SN74HC166
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
4 Pin Configuration and Functions
J, D, DB, N, NS, or PW Package
16-Pin CDIP, SOIC, SSOP, PDIP, SO, TSSOP
Top View
FK Package
20-Pin LCCC
Top View
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: SN54HC166 SN74HC166
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7
UNIT
V
VCC
IIK
Supply voltage range
Input clamp current(2)
Output clamp current(2)
Continuous output current
–0.5
VI < 0 or VI > VCC
VO < 0 or VO > VCC
VO = 0 to VCC
±20
±20
±25
±50
150
150
mA
mA
mA
mA
°C
IOK
IO
Continuous current through VCC or GND
Junction temperature
TJ
Tstg
Storage temperature
°C
–65
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under 节5.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(1)
SN54HC166
SN74HC166
UNIT
MIN
2
NOM
MAX
MIN
2
NOM
MAX
VCC
Supply voltage
5
6
5
6
V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
1.5
3.15
4.2
1.5
3.15
4.2
VIH
High-level input voltage
V
V
0.5
1.35
1.8
0.5
1.35
1.8
VIL
Low-level input voltage
VI
Input voltage
0
0
VCC
VCC
1000
500
400
125
0
0
VCC
VCC
1000
500
400
85
V
V
VO
Output voltage
VCC = 2 V
Δt/Δv(2)
Input transition rise/fall time VCC = 4.5 V
VCC = 6 V
ns
°C
TA
Operating free-air temperature
−55
−40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from
induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
5.3 Thermal Information
D (SOIC)
16 PINS
DB (SSOP)
16 PINS
N (PDIP)
16 PINS
NS (SO)
16 PINS
PW (TSSOP)
16 PINS
THERMAL METRIC
RθJA Junction-to-ambient thermal
resistance(1)
UNIT
73
82
67
64
108
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: SN54HC166 SN74HC166
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
SN54HC166
SN74HC166
TEST
PARAMETER
VCC (V)
UNIT
CONDITIONS(1)
MIN
1.9
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2
4.5
6
1.998
4.499
5.999
4.3
4.4
4.4
IOH = −20 μA
5.9
5.9
VOH
V
4.5
6
3.98
5.48
3.84
5.34
IOH = −4 mA
5.8
IOH = −5.2 mA
2
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6
IOL = 20 μA
VOL
0.1
0.1
0.1
V
IOL = 4 mA
4.5
6
0.26
0.26
±100
0.4
0.33
0.33
±1000
IOL = 5.2 mA
VI = VCC or 0
0.15
0.4
II
6
±0.1
±1000
nA
μA
pF
VI = VCC or 0, IO
= 0
ICC
Ci
6
8
160
10
80
10
2 to 6
3
10
(1) VI = VIH or VIL, unless otherwise noted.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: SN54HC166 SN74HC166
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
5.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
VCC(V)
SN54HC166
SN74HC166
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
5
2
4.5
6
6
4.2
21
25
fclock
Clock frequency
31
25
MHz
36
29
2
100
20
17
80
16
14
145
29
25
80
16
14
100
20
17
80
16
14
40
8
150
30
26
120
24
20
220
44
38
120
24
20
150
30
26
120
24
20
60
12
10
0
125
25
21
100
20
17
180
36
31
100
20
17
125
25
21
100
20
17
50
10
9
CLR low
4.5
6
tw
Pulse duration
ns
2
CLK high or low
4.5
6
2
4.5
6
SH/LD high before CLK↑
SER before CLK↑
2
4.5
6
2
CLK INH low before CLK-
↑
tsu
Setup time
4.5
6
ns
2
4.5
6
Data before CLK↑
2
4.5
6
CLR inactive before CLK↑
SH/LD high after CLK↑
SER after CLK↑
7
2
0
0
4.5
6
0
0
0
0
0
0
2
5
5
5
4.5
6
5
5
5
5
5
5
th
Hold time
ns
2
0
0
0
4.5
6
0
0
0
CLK INH high after CLK↑
Data after CLK↑
0
0
0
2
5
5
5
4.5
6
5
5
5
5
5
5
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: SN54HC166 SN74HC166
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
图5-1. Typical Clear, Shift, Load, Inhibit, and Shift Sequence
5.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 6)
TA = 25°C
SN54HC166
SN74HC166
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC (V)
UNIT
MIN
6
TYP
11
36
45
62
18
13
75
15
13
38
8
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2
4.5
6
fmax
31
36
25
29
MHz
25
2
120
24
180
36
150
30
tPHL
tpd
tt
CLR
CLK
QH
QH
4.5
6
ns
ns
ns
20
31
26
2
150
30
225
45
190
38
4.5
6
26
38
32
2
75
110
22
95
Any
4.5
6
15
19
6
13
19
16
5.7 Operating Characteristics
TA = 25℃
PARAMETER
TEST CONDITIONS
TYP
50
UNIT
Cpd
Power dissipation capacitance
No load
pF
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: SN54HC166 SN74HC166
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
6 Parameter Measurement Information
tpd is the maximum between tPLH and tPHL
图6-1. Load Circuit
图6-2. Voltage Waveforms
Pulse Durations
图6-3. Voltage Waveforms
Setup and Hold and Input Rise and Fall Times
图6-4. Voltage Waveforms
Propagation Delay and Output Transition Times
A. CL includes probe and jig capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following charactersitics: PRR ≤1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%
D. The outputs are measured one at a time with one input transition per measurement.
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: SN54HC166 SN74HC166
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
7 Detailed Description
7.1 Overview
These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding
clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high,
SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock
(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the
next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-
high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable
or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the
other clock input. This allows the system clock to be free running, and the register can be stopped on command
with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides
all other inputs, including CLK, and resets all flip-flops to zero.
7.2 Functional Block Diagram
7.3 Device Functional Modes
表7-1. Function Table
OUTPUTS
INPUTS
INTERNAL
QH
PARALLEL
A...H
CLR
SH/LD
CLK INH
CLK
SER
QA
QB
L
X
X
L
X
L
L
L
L
H
X
L
X
X
X
H
L
X
X
L
QA0
a
L
L
H
H
H
H
H
QB0
b
QH0
h
a...h
X
↑
↑
↑
↑
H
H
X
H
QAn
QAn
QB0
QGn
QGn
QH0
X
L
X
X
QA0
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: SN54HC166 SN74HC166
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: SN54HC166 SN74HC166
SN54HC166, SN74HC166
ZHCSQ31E –DECEMBER 1982 –REVISED FEBRUARY 2022
www.ti.com.cn
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: SN54HC166 SN74HC166
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962-9050101Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-
Samples
9050101Q2A
SNJ54HC
166FK
5962-9050101QEA
5962-9050101VEA
SN54HC166J
ACTIVE
ACTIVE
ACTIVE
CDIP
CDIP
CDIP
J
J
J
16
16
16
1
1
1
Non-RoHS
& Green
SNPB
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
5962-9050101QE
A
SNJ54HC166J
Samples
Samples
Samples
Non-RoHS
& Green
5962-9050101VE
A
SNV54HC166J
Non-RoHS
& Green
SN54HC166J
SN74HC166DBR
SN74HC166DR
SN74HC166DRE4
SN74HC166DRG4
SN74HC166N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
SOIC
PDIP
SO
DB
D
16
16
16
16
16
16
16
20
2000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU | SN
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
HC166
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
HC166
D
HC166
D
NIPDAU
HC166
N
25
RoHS & Green
NIPDAU
SN74HC166N
HC166
SN74HC166NSR
SN74HC166PWR
SNJ54HC166FK
NS
PW
FK
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TSSOP
LCCC
NIPDAU | SN
SNPB
HC166
1
Non-RoHS
& Green
5962-
9050101Q2A
SNJ54HC
166FK
SNJ54HC166J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9050101QE
A
Samples
SNJ54HC166J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC166, SN54HC166-SP, SN74HC166 :
Catalog : SN74HC166, SN54HC166
•
Military : SN54HC166
•
Space : SN54HC166-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
Military - QML certified for Military and Defense Applications
•
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC166DBR
SN74HC166DR
SN74HC166DR
SN74HC166DRG4
SN74HC166NSR
SN74HC166NSR
SN74HC166PWR
SN74HC166PWR
SN74HC166PWR
SSOP
SOIC
SOIC
SOIC
SO
DB
D
16
16
16
16
16
16
16
16
16
2000
2500
2500
2500
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
12.4
12.4
12.4
8.35
6.5
6.6
6.5
8.2
6.6
10.3
9.3
2.4
2.1
2.1
2.1
2.5
2.5
1.6
1.6
1.6
12.0
8.0
16.0
16.0
16.0
16.0
16.0
16.2
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
8.0
D
10.3
10.5
8.0
NS
NS
PW
PW
PW
12.0
12.0
8.0
SO
8.45 10.55
TSSOP
TSSOP
TSSOP
6.9
6.9
5.6
5.6
8.0
6.85
5.45
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC166DBR
SN74HC166DR
SN74HC166DR
SN74HC166DRG4
SN74HC166NSR
SN74HC166NSR
SN74HC166PWR
SN74HC166PWR
SN74HC166PWR
SSOP
SOIC
SOIC
SOIC
SO
DB
D
16
16
16
16
16
16
16
16
16
2000
2500
2500
2500
2000
2000
2000
2000
2000
356.0
356.0
366.0
340.5
367.0
356.0
356.0
356.0
366.0
356.0
356.0
364.0
336.1
367.0
356.0
356.0
356.0
364.0
35.0
35.0
50.0
32.0
38.0
35.0
35.0
35.0
50.0
D
D
NS
NS
PW
PW
PW
SO
TSSOP
TSSOP
TSSOP
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962-9050101Q2A
SN74HC166N
FK
N
LCCC
PDIP
PDIP
LCCC
20
16
16
20
1
25
25
1
506.98
506
12.06
13.97
13.97
12.06
2030
11230
11230
2030
NA
4.32
4.32
NA
SN74HC166N
N
506
SNJ54HC166FK
FK
506.98
Pack Materials-Page 3
PACKAGE OUTLINE
NS0016A
SOP - 2.00 mm max height
S
C
A
L
E
1
.
5
0
0
SOP
C
SEATING PLANE
8.2
7.4
TYP
0.1 C
A
PIN 1 ID
AREA
14X 1.27
16
1
2X
10.4
10.0
NOTE 3
8.89
8
9
0.51
0.35
16X
5.4
5.2
B
2.00 MAX
0.25
C A B
NOTE 4
0.15 TYP
SEE DETAIL A
0.25
0.3
0.1
GAGE PLANE
0 - 10
1.05
0.55
DETAIL A
TYPICAL
(1.25)
4220735/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
NS0016A
SOP - 2.00 mm max height
SOP
16X (1.85)
16X (0.6)
SEE
DETAILS
SYMM
1
16
SYMM
14X (1.27)
9
8
(R0.05) TYP
(7)
LAND PATTERN EXAMPLE
SCALE:7X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220735/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
NS0016A
SOP - 2.00 mm max height
SOP
16X (1.85)
16X (0.6)
SYMM
1
16
SYMM
14X (1.27)
8
9
(R0.05) TYP
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220735/A 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DB0016A
SSOP - 2 mm max height
S
C
A
L
E
1
.
5
0
0
SMALL OUTLINE PACKAGE
C
8.2
7.4
TYP
A
0.1 C
SEATING
PIN 1 INDEX AREA
PLANE
14X 0.65
16
1
2X
6.5
5.9
4.55
NOTE 3
8
9
0.38
16X
0.22
5.6
5.0
B
0.1
C A B
NOTE 4
0.25
0.09
SEE DETAIL A
2 MAX
0.25
GAGE PLANE
0.95
0.55
0.05 MIN
0 -8
A
15
DETAIL A
TYPICAL
4220763/A 05/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0016A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.85)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220763/A 05/2022
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0016A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
16X (1.85)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220763/A 05/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
FK 20
8.89 x 8.89, 1.27 mm pitch
LCCC - 2.03 mm max height
LEADLESS CERAMIC CHIP CARRIER
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229370\/A\
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
5962-9050401MXX
IC 32-BIT, DSP-DIGITAL FILTER, PGA155, 1.680 X 1.680 INCH, 0.345 INCH HEIGHT, PGA-155, DSP Peripheral
WEDC
5962-9050401MYX
Digital Filter, 32-Bit, CMOS, CQFP132, 0.960 X 0.960 INCH, 0.140 INCH HEIGHT, CERAMIC, LCC-132
WEDC
©2020 ICPDF网 联系我们和版权申明