5962-9086303MXA [TI]
Wide-Band Analog Interface Circuit;
| 型号： | 5962-9086303MXA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Wide-Band Analog Interface Circuit |
| 文件： | 总56页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC32046C, TLC32046I, TLC32046M
Data Manual
Wide-Band Analog Interface Circuit
SLAS028
May 1995
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TIwarrantsperformanceofitssemiconductorproductsandrelatedsoftwaretothespecifications
applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright 1995, Texas Instruments Incorporated
Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
1.2 Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
2
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.1 Internal Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2.2 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.3 A/D Band-Pass Filter, Clocking, and Conversion Timing . . . . . . . . . . . . . . . . . . . . 2–4
2.4 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.5 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.6 D/A Low-Pass Filter, Clocking, and Conversion Timing . . . . . . . . . . . . . . . . . . . . . 2–4
2.7 D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.8 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2.9 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2.9.1 One 16-Bit Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2.9.2 Two 8-Bit Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2.9.3 Synchronous Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2.10 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2.10.1 One 16-Bit Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2.10.2 Two 8-Bit Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2.10.3 Asynchronous Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2.11 Operation of TLC32046C and TLC32046I With Internal Voltage Reference . . . 2–7
2.12 Operation of TLC32046C AND TLC32046I With External Voltage Reference . 2–7
2.13 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
2.14 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
2.15 Communications Word Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
2.15.1 Primary DR Word Bit Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
2.15.2 Primary DX Word Bit Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2.15.3 Secondary DX Word Bit Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
2.16 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
2.17 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2.18 AIC Register Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2.19 AIC Responses to Improper Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2.20 Operation With Conversion Times Too Close Together . . . . . . . . . . . . . . . . . . . . . 2–12
2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs – Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2.22 More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs – Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
iii
Section
Title
Page
2.23 More than One Set of Primary and Secondary DX Serial Communications
Occurring Between Two Receive Frame Syncs – Asynchronous Operation . . . 2–13
2.24 System Frequency Response Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2.25 (Sin x)/x Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2.26 (Sin x)/x Roll-Off for a Zero-Order Hold Function . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2.27 Correction Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2.28 Correction Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2.29 TMS320 Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . 3–1
3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3.3 Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, V
= 5 V, V
= –5 V, V
= 5 V . . . . . . . . . . . . . . . . . 3–2
CC+
CC–
DD
3.3.1 Total Device, MSTR CLK Frequency = 5.184 MHz . . . . . . . . . . . . . . . . . 3–2
3.3.2 Power Supply Rejection and Crosstalk Attenuation . . . . . . . . . . . . . . . . . 3–2
3.3.3 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3.3.4 Receive Amplifier Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3.3.5 Transmit Filter Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3.3.6 Receive and Transmit Channel System Distortion, SCF Clock
Frequency = 288kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3.3.7 Receive Channel Signal-to-Distortion Ratio . . . . . . . . . . . . . . . . . . . . . . . 3–4
3.3.8 Transmit Channel Signal-to-Distortion Ratio . . . . . . . . . . . . . . . . . . . . . . . 3–4
3.3.9 Receive and Transmit Gain and Dynamic Range . . . . . . . . . . . . . . . . . . . 3–4
3.3.10 Receive Channel Band-Pass Filter Transfer Function,
SCF f
= 288 kHz, Input (IN+ – IN–) Is A +3-V Sine Wave . . . . . . . 3–5
clock
3.3.11 Receive and Transmit Channel Low-Pass Filter Transfer Function,
SCF f = 288 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
clock
3.4 Operating Characteristics Over Recommended Operating Free-Air
Temperature Range, V = 5 V, V = –5 V, V = 5 V . . . . . . . . . . . . . . . . . 3–6
CC+
CC–
DD
3.4.1 Receive and Transmit Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3.5 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3.5.1 Serial Port Recommended Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3.5.2 Serial Port – AIC Output Signals, C = 30 pF for SHIFT CLK Output,
L
C = 15 pF For All Other Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
L
4
5
6
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
iv
List of Illustrations
Figure
Title
Page
1–1 Dual-Word (Telephone Interface) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
1–2 Word Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
1–3 Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
2–1 Asynchronous Internal Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
2–2 Primary and Secondary Communications Word Sequence . . . . . . . . . . . . . . . . . . . 2–8
2–3 DR Word Bit Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
2–4 Primary DX Word BIt Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2–5 Secondary DX Word BIt Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
2–6 Reset on Power-Up Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2–7 Conversion Times Too Close Together . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2–8 More Than One Receive Frame Sync Between Two Transmit Frame Syncs . . . 2–13
2–9 More Than One Transmit Frame Sync Between Two Receive Frame Syncs . . . 2–13
2–10 More Than One Set of Primary and Secondary DX Serial Communications
Between Two Receive Frame Syncs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2–11 First-Order Correction Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
4–1 IN+ and IN – Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4–2 Dual-Word (Telephone Interface) Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–3 Word Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–4 Byte Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4–5 Shift-Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
4–6 TMS32010/TMS320C15–TLC32046 Interface Timing . . . . . . . . . . . . . . . . . . . . . . 4–4
4–7 TMS32010/TMS320C15–TLC32046 Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . 4–5
v
List of Tables
Table
Title
Page
2–1 Mode-Selection Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2–2 Primary DX Serial Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2–3 Secondary DX Serial Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2–4 AIC Responses to Improper Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2–5 (sin x)/x Roll-Off Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2–6 (sin x)/x Correction Table for f = 8000 Hz and f = 9600 Hz . . . . . . . . . . . . . . . . . 2–1
s
s
4–1 Gain Control Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
vi
1 Introduction
The TLC32046C, TLC32046I, and TLC32046M wide-band analog interface circuits (AIC) are a complete
analog-to-digital and digital-to-analog interface system for advanced digital signal processors (DSPs)
similar to the TMS32020, TMS320C25, and TMS320C30. The TLC32046C and TLC32046I offer a powerful
combination of options under DSP control: three operating modes (dual-word [telephone interface], word,
and byte) combined with two word formats (8 bits and 16 bits) and synchronous or asynchronous operation.
It provides a high level of flexibility in that conversion and sampling rates, filter bandwidths, input circuitry,
receive and transmit gains, and multiplexed analog inputs are under processor control.
This AIC features a
•
•
•
•
band-pass switched-capacitor antialiasing input filter
14-bit-resolution A/D converter
14-bit-resolution D/A converter
low-pass switched-capacitor output-reconstruction filter.
The antialiasing input filter comprises eighth-order and fourth-order CC-type (Chebyshev/elliptic
transitional) low-pass and high-pass filters, respectively. The input filter is implemented in switched-
capacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing
caused by sampled data filtering. When low-pass filtering is desired, the high-pass filter can be switched
out of the signal path. A selectable auxiliary differential analog input is provided for applications where more
than one analog input is required.
The output-reconstruction filter is an eighth-order CC-type (Chebyshev/elliptic transitional low-pass filter)
followed by a second-order (sin x)/x correction filter and is implemented in switched-capacitor technology.
This filter is followed by a continuous-time filter to eliminate images of the sample data signal. The on-board
(sin x)/x correction filter can be switched out of the signal path using digital signal processor control.
The A/D and D/A architectures ensure no missing codes and monotonic operation. An internal voltage
reference is provided to ease the design task and to provide complete control over the performance of the
IC. The internal voltage reference is brought out to REF. Separate analog and digital voltage supplies and
ground are provided to minimize noise and ensure a wide dynamic range. The analog circuit path contains
only differential circuitry to keep noise to a minimum. The exception is the DAC sample-and-hold, which
utilizes pseudo-differential circuitry.
The TLC32046C is characterized for operation from 0°C to 70°C, the TLC32046I is characterized for
operation from –40°C to 85°C, and the TLC32046M is characterized for operation from –55°C to 125°C.
1–1
1.1 Features
•
•
•
14-Bit Dynamic Range ADC and DAC
16-Bit Dynamic Range Input With Programmable Gain
Synchronous or Asynchronous ADC and DAC Sampling Rates Up to 25,000 Samples Per
Second
•
•
Programmable Incremental ADC and DAC Conversion Timing Adjustments
Typical Applications
– Speech Encryption for Digital Transmission
– Speech Recognition and Storage Systems
– Speech Synthesis
– Modems at 8-kHz, 9.6-kHz, and 16-kHz Sampling Rates
– Industrial Process Control
– Biomedical Instrumentation
– Acoustical Signal Processing
– Spectral Analysis
– Instrumentation Recorders
– Data Acquisition
•
•
•
•
•
Switched-Capacitor Antialiasing Input Filter and Output-Reconstruction Filter
Three Fundamental Modes of Operation: Dual-Word (Telephone Interface), Word, and Byte
600-mil Wide N Package
Digital Output in Twos Complement Format
CMOS Technology
FUNCTION TABLE
SYNCHRONOUS ASYNCHRONOUS
DATA
COMMUNICATIONS
FORMAT
DIRECT
INTERFACE
(CONTROL
REGISTER
BIT D5 = 1)
(CONTROL
REGISTER
BIT D5 = 0)
FORCING CONDITION
16-bit format
Dual-word
(telephone
interface) mode
Dual-word
Terminal 13 = 0 to 5 V
TMS32020,
TMS320C25,
TMS320C30
(telephone interface) Terminal 1 = 0 to 5 V
mode
16-bit format
Word mode
Word mode
Terminal 13 = V
CC–
(–5 V nom) TMS32020,
Terminal 1 = V + (5 V nom)
CC
TMS320C25,
TMS320C30,
indirect
interface to
TMS320C10.
(see Figure 7).
8-bit format
(2 bytes required)
Byte mode
Byte mode
Terminal 13 = V (–5 V nom) TMS320C17
CC–
Terminal 1 = V (–5 V nom)
CC–
1–2
1.2 Functional Block Diagrams
WORD OR BYTE MODE
26
IN +
25
24
M
U
X
M
U
X
Serial
Port
5
IN –
AUX IN +
Low-Pass
Filter
DR
A/D
4
3
23
FSR
AUX IN –
EODR
6
High-Pass
Filter
MSTR CLK
SHIFT CLK
Receive Section
Transmit Section
10
1
Internal
Voltage
Reference
WORD-
BYTE
13
12
14
11
CONTROL
DX
FSX
22
21
OUT +
Low-Pass
Filter
(sin x)/x
Correction
M
U
X
D/A
EODX
OUT –
17,18
20
19
9
7
8
2
V
V
ANLG
GND
DGTL
GND (DIGITAL)
V
DD
REF
RESET
CC +
CC –
DUAL-WORD (TELEPHONE INTERFACE) MODE
26
IN +
25
24
M
U
X
M
U
X
5
Serial
Port
IN –
AUX IN +
Low-Pass
Filter
DR
A/D
4
3
23
FSR
AUX IN –
D11 OUT
MSTR CLK
6
High-Pass
Filter
Receive Section
Transmit Section
10
1
SHIFT CLK
FSD
Internal
Voltage
Reference
13
12
14
11
DATA DR
DX
FSX
22
21
Low-Pass
Filter
(sin x)/x
Correction
OUT +
M
U
X
D/A
D10 OUT
OUT –
20
19
17,18
9
7
8
2
V
V
ANLG
GND
DGTL
GND (DIGITAL)
V
DD
REF
RESET
CC +
CC–
1–3
FRAME SYNCHRONIZATION FUNCTIONS
Function
Frame Sync Output
FSX low
Receiving serial data on DX from processor to internal DAC
Transmitting serial data on DR from internal ADC to processor, primary communications
FSR low
Transmitting serial data on DR from Data-DR to processor, secondary communications in
dual-word (telephone interface) mode only
FSD low
5 V
20
–5 V
19
Serial Data Out
5
V
+
V
–
CC
CC
26
25
DR
FSR
IN+
Analog In
4
3
IN–
TLC32046
D11OUT
TMS32020,
TMS320C25,
TMS320C30, or
Equivalent 16-Bit DSP
22
21
OUT+
12 Serial Data In
Analog Out
DX
FSX
OUT–
14
11
TTL or CMOS
Logic Levels
D10OUT
Secondary Communication (see Table above)
1
13
Serial Data Input
FSD
DATA-DR
16-Bit Format TTL
or CMOS Logic Levels
Figure 1–1. Dual-Word (Telephone Interface) Mode
When the DATA-DR/CONTROL input is tied to a logic signal source varying between 0 and 5 V, the
TLC32046 is in the dual-word (telephone interface) mode. This logic signal is routed to the DR line for input
to the DSP only when data frame synchronization (FSD) outputs a low level. The FSD pulse duration is 16
shift clock pulses. Also, in this mode, the control register data bits D10 and D11 appear on D10OUT and
D11OUT, respectively, as outputs.
1–4
5 V
20
–5 V
19
V
V
CC +
CC –
Serial Data Out
26
25
5
4
DR
IN+
Analog In
IN–
TLC32046
FSR
TMS32020,
TMS320C25,
3
EODR
TMS320C30,
or Equivalent
16-Bit DSP
22
21
Serial Data In
OUT+
12
14
11
Analog Out
DX
FSX
OUT–
TTL or CMOS
Logic Levels
EODX
V
V
CC+
(5 V nom)
CC–
(–5 V nom)
1
13
WORD-BYTE
CONTROL
Figure 1–2. Word Mode
5 V
20
–5 V
19
V
V
CC +
CC –
Serial Data Out
26
5
4
DR
IN+
Analog In
25
IN–
TLC32046
FSR
3
TMS320C17 or
Equivalent
EODR
22
21
8-Bit Serial Interface
(2 bytes required)
Serial Data In
OUT+
12
14
11
Analog Out
DX
OUT–
TTL or CMOS
Logic Levels
FSX
EODX
V
CC–
(–5 V nom)
V
CC–
(–5 V nom)
1
13
WORD-BYTE
CONTROL
Figure 1–3. Byte Mode
The word or byte mode is selected by first connecting the DATA-DR/CONTROL input to V
CC–.
FSD/WORD-BYTE becomes an input and can then be used to select either word or byte transmission
formats. The end-of-data transmit (EODX) and the end-of-data receive (EODR) signals respectively, are
used to signal the end of word or byte communication (see the Terminal Functions section).
1–5
1.3 Terminal Assignments
†
‡
FK OR FN PACKAGE
(TOP VIEW)
J
OR N PACKAGE
(TOP VIEW)
§
FSD/WORD-BYTE
NU
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RESET
NU
2
§
D11OUT/EODR
IN+
3
FSR
DR
IN–
4
AUX IN+
AUX IN–
OUT+
OUT–
5
MSTR CLK
6
V
7
DD
4
3 2 1
28 27 26
25
5
6
7
8
9
REF
DGTL GND
SHIFT CLK
DR
IN–
8
V
CC+
MSTR CLK
24
23
22
21
20
19
AUX IN+
AUX IN–
OUT+
9
V
CC–
V
DD
10
11
12
13
14
§
D10OUT/EODX
ANLG GND
ANLG GND
NU
REF
DGTL GND
SHIFT CLK
DX
§
OUT–
‡
DATA-DR/CONTROL
FSX
V
CC+
10
11
§
NU
D10OUT/EODX
V
CC–
12 13 14 15 16 1718
NU - Nonusable; no external connection should be made to these terminals.
†
‡
§
Refer to the mechanical data for the JT package.
600-mil wide
The portion of the terminal name to the left of the slash is used for the dual-word (telephone interface) mode.
The portion of the terminal name to the right of the slash is used for word-byte mode.
1.4 Ordering Information
AVAILABLE OPTIONS
PACKAGE
PLASTIC CHIP
CARRIER
(FN)
T
A
PLASTIC DIP
(N)
CERAMIC DIP
(J)
CHIP CARRIER
(FK)
0°C to 70°C
–40°C to 85°C
–55°C to 125°C
TLC32046CFN
TLC32046IFN
TLC32046CN
TLC32046IN
TLC32046MJ
TLC32046MFK
1–6
1.5 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
ANLG GND
17,18
Analog ground return for all internal analog circuits. Not internally connected to DGTL
GND.
AUX IN+
24
I
Noninverting auxiliary analog input stage. AUX IN+ can be switched into the band-pass
filter and ADC path via software control. If the appropriate bit in the control register is
a 1, the auxiliary inputs replace the IN+ and IN– inputs. If the bit is a 0, the IN+ and IN–
inputs are used (see the DX Serial Data Word Format).
AUX IN–
23
13
I
I
Inverting auxiliary analog input (see the above AUX IN+ description).
DATA-DR
The dual-word (telephone interface) mode, selected by applying an input logic level
between0and5VtoDATA-DR, allowsthisterminaltofunctionasadatainput. Thedata
is then framed by the FSD signal and transmitted as an output to the DR line during
secondary communication. The functions FSD, D11OUT, and D10OUT are valid with
this mode selection (see Table 2–1).
CONTROL
DR
When CONTROL is tied to V , the device is in the word or byte mode. The functions
CC–
WORD-BYTE, EODR, and EODX are valid in this mode. CONTROL is then used to
select either the word or byte mode (see Function Table).
5
O
I
DR is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This
transmission of bits from the AIC to the TMS320 serial port is synchronized with
SHIFT CLK.
DX
12
11
DX is used to receive the DAC input bits and timing and control information from the
TMS320. This serial transmission from the TMS320 serial port is synchronized with
SHIFT CLK.
D10OUT
EODX
O
In the dual-word (telephone interface) mode, bit D10 of the control register is output to
D10OUT. When the device is reset, bit D10 is initialized to 0 (see DX Serial Data Word
Format). The output update is immediate upon changing bit D10.
End-of-datatransmit. During the word-mode timing, a low-going pulse occurs on EODX
immediatelyafterthe16bitsofDACandcontrolorregisterinformationhavetransmitted
from the TMS320 serial port to the AIC.This signal can be used to interrupt a
microprocessor upon completion of serial communications. Also, this signal can be
used to strobe and enable external serial-to-parallel shift registers, latches, or external
FIFO RAM and to facilitate parallel data bus communications between the DSP and the
serial-to-parallel shift registers. During the byte-mode timing, this signal goes low after
the first byte has been transmitted from the TMS320 serial port to the AIC and is kept
lowuntilthesecondbytehasbeentransmitted. TheTMS320C17canusethislow-going
signal to differentiate first and second bytes.
D11OUT
EODR
3
O
In the dual-word (telephone interface) mode, bit D11 of the control register is output to
D11OUT. When the device is reset, bit D11 is initialized to 0 (see DX Serial Data Word
Format). The output update is immediate upon changing bit D11.
End-of-data receive. During the word-mode timing, a low-going pulse occurs on EODR
immediately after the 16 bits of A/D information have been transmitted from the AIC to
the TMS320 serial port. This signal can be used to interrupt a microprocessor upon
completionof serial communications. Also, this signal can be used to strobe and enable
external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate
parallel data bus communications between the DSP and the serial-to-parallel shift
registers. During the byte-mode timing, this signal goes low after the first byte has been
transmitted from the AIC to the TMS320 serial port and is kept low until the second byte
has been transmitted. The TMS320C17 can use this low-going signal to differentiate
between first and second bytes.
1–7
1.5 Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
DGTL
9
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
FSD
1
O
Frame sync data. The FSD output remains high during primary communication. In the
dual-word (telephone interface) mode, FSD is identical to FSX during secondary
communication.
WORD-BYTE
FSR
I
WORD-BYTE allows differentiation between the word and byte data format (see
DATA-DR/CONTROL and Table 2-1 for details).
4
O
Frame sync receive. FSR is held low during bit transmission. When FSR goes low, the
TMS320 serial port begins receiving bits from the AIC via DR of the AIC. The most
significant DR bit is present on DR before FSR goes low (see Serial Port Sections and
Internal Timing Configuration Diagrams).
FSX
14
O
Frame sync transmit. When FSX goes low, the TMS320 serial port begins transmitting
bits to the AIC via DX of the AIC. FSX is held low during bit transmission (see Serial Port
Sections and Internal Timing Configuration Diagrams).
IN+
26
25
6
I
I
I
Noninverting input to analog input amplifier stage
Inverting input to analog input amplifier stage
IN–
MSTR CLK
The master clock signal is used to derive all the key logic signals of the AIC, such as
the shift clock, the switched-capacitor filter clocks, and the A/D and D/A timing signals.
The Internal Timing Configuration diagram shows how these key signals are derived.
The frequencies of these signals are synchronous submultiples of the master clock
frequency to eliminate unwanted aliasing when the sampled analog signals are
transferred between the switched-capacitor filters and the ADC and DAC converters
(see the Internal Timing Configuration).
OUT+
OUT–
REF
22
21
8
O
O
Noninverting output of analog output power amplifier. OUT+ drives transformer hybrids
or high-impedance loads directly in a differential or a single-ended configuration.
Invertingoutputofanalogoutputpoweramplifier. OUT–isfunctionallyidenticalwithand
complementary to OUT+.
I/O The internal voltage reference is brought out on REF. An external voltage reference can
be applied to REF to override the internal voltage reference.
RESET
2
I
A reset function is provided to initialize TA, TA’, TB, RA, RA’, RB (see Figure 2-1), and
the control registers. This reset function initiates serial communications between the
AIC and DSP. The reset function initializes all AIC registers, including the control
register. After a negative-going pulse on RESET, the AIC registers are initialized to
provide a 16-kHz data conversion rate for a 10.368-MHz master clock input signal. The
conversionrateadjustregisters, TA’ and RA’, are reset to 1. The CONTROL register bits
are reset as follows (see AIC DX Data Word Format section):
D11 = 0, D10 = 0, D9 = 1, D7 = 1, D6 = 1, D5 = 1, D4 = 0, D3 = 0, D2 = 1
The shift clock (SCLK) is held high during RESET.
This initialization allows normal serial-port communication to occur between the AIC
and the DSP.
SHIFT CLK
10
O
The shift clock signal is obtained by dividing the master clock signal frequency by four.
SHIFT CLK is used to clock the serial data transfers of the AIC.
V
V
V
7
Digital supply voltage, 5 V ±5%
DD
20
19
Positive analog supply voltage, 5 V ±5%
Negative analog supply voltage, –5 V ±5%
CC+
CC–
1–8
2
Detailed Description
Table 2–1. Mode-Selection Function Table
DATA-DR/
CONTROL
(Terminal 13)
FSD/
CONTROL
OPERATING
MODE
SERIAL
CONFIGURATION
WORD-BYTE REGISTER
(Terminal 1)
DESCRIPTION
BIT (D5)
†
Terminal functions DATA-DR ,
†
FSD , D11OUT, and D10OUT
are applicable in this
Dual Word
(Telephone
Interface)
configuration. FSD is asserted
during secondary
communication, but FSR is not
asserted. However, FSD
remains high during primary
communication.
Data in
(0 V to 5 V)
FSD out
(0 V to 5 V)
Synchronous,
One 16-Bit Word
1
†
Terminal functions DATA-DR
,
†
FSD , D11OUT, and D10OUT
are applicable in this
configuration. FSD is asserted
during secondary
communication, but FSR is not
asserted. However, FSD
Dual Word
(Telephone
Interface)
Data in
(0 V to 5 V)
FSD out
(0 V to 5 V)
Synchronous,
One 16-Bit Word
0
remains high during primary
communication. If secondary
communications occur while
the A/D conversion is being
transmitted from DR, FSD
cannot go low, and data from
DATA-DR cannot go onto DR.
Terminal functions
† †
Synchronous,
CONTROL , WORD-BYTE ,
1
0
1
0
One 16-Bit Word EODR, and EODX are
applicable in this configuration.
Terminal functions
V
CC+
WORD
†
†
Asynchronous,
One 16-bit Word
CONTROL , WORD-BYTE ,
EODR, and EODX are
applicable in this configuration.
V
CC–
Terminal functions
CONTROL , WORD-BYTE ,
EODR, and EODX are
†
†
Synchronous,
Two 8-Bit Bytes
applicable in this configuration.
V
CC–
BYTE
Terminal functions
CONTROL , WORD-BYTE ,
EODR, and EODX are
†
†
Asynchronous,
Two 8-Bit Bytes
applicable in this configuration.
†
DATA-DR/CONTROL has an internal pulldown resistor to –5 V, and FSD/WORD-BYTE has an internal pullup resistor
to 5 V.
2–1
2.1 Internal Timing Configuration (see Figure 2–1)
All the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock
input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by
dividing the master clock input signal frequency by four.
The TX(A) counter and the TX(B) counter, which are driven by the master clock signal, determine the D/A
conversion timing. Similarly, the RX(A) counter and the RX(B) counter determine the A/D conversion timing.
In order for the low-pass switched-capacitor filter in the D/A path (see Functional Block Diagram) to meet
its transfer function specifications, the frequency of its clock input must be 288 kHz. If the clock frequency
is not 288 kHz, the filter transfer function frequencies are frequency-scaled by the ratios of the clock
frequency to 288 kHz:
Normalized Frequency
288
288 kHz, please call the factory.
SCF f
(kHz)
clock
Absolute Frequency (kHz)
(1)
For Low-Pass SCF f
clock
To obtain the specified filter response, the combination of master clock frequency and the TX(A) counter
and the RX(A) counter values must yield a 288-kHz switched-capacitor clock signal. This 288-kHz clock
signal can then be divided by the TX(B) counter to establish the D/A conversion timing.
The transfer function of the band-pass switched-capacitor filter in the A/D path (see Functional Block
Diagram) is a composite of its high-pass and low-pass transfer functions. When the shift-clock frequency
(SCF) is 288 kHz, the high-frequency roll-off of the low-pass section will meet the band-pass filter transfer
function specification. Otherwise, the high-frequency roll-off is frequency-scaled by the ratio of the
high-passsectionSCFclockto288kHz(seeFigure5–5). Thelow-frequencyroll-offofthehigh-passsection
meets the band-pass filter transfer function specification when the A/D conversion rate is 16 kHz. If not, the
low-frequency roll-off of the high-pass section is frequency-scaled by the ratio of the A/D conversion rate
to 16 kHz.
TheTX(A)counterandtheTX(B)counterarereloadedeachD/Aconversionperiod, whiletheRX(A)counter
and the RX(B) counter are reloaded every A/D conversion period. The TX(B) counter and the RX(B) counter
are loaded with the values in the TB and RB registers, respectively. Via software control, the TX(A) counter
canbeloadedwiththeTAregister, theTAregisterlesstheTA′ register, ortheTAregisterplustheTA′ register.
By selecting the TA register less the TA′ register option, the upcoming conversion timing occurs earlier by
an amount of time that equals TA′ times the signal period of the master clock. If the TA register plus the TA′
register option is executed, the upcoming conversion timing occurs later by an amount of time that equals
TA′ times the signal period of the master clock. Thus, the D/A conversion timing can be advanced or
retarded. An identical ability to alter the A/D conversion timing is provided. However, the RX(A) counter can
be programmed via software control with the RA register, the RA register less the RA′ register, or the RA
register plus the RA′ register.
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the A/D and D/A conversion timing and can be used to enhance signal-to-noise
performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies.
If the transmit and receive sections are configured to be synchronous, then the low-pass and band-pass
switched-capacitor filter clocks are derived from the TX(A) counter. Also, both the D/A and A/D conversion
timings are derived from the TX(A) counter and the TX(B) counter. When the transmit and receive sections
are configured to be synchronous, the RX(A) counter, RX(B) counter, RA register, RA′ register, and RB
registers are not used.
2–2
20.736 MHZ
41.472 MHZ
XTAL
OSC
TMS320 DSP
5.184 MHz
10.368 MHz
MASTER CLOCK
SHIFT CLOCK
1.296 MHz
Divide By 4
2.592 MHz
TA′ REGISTER
(6 Bits)
2s-Complement TA
TA Register
(5 Bits)
SCF CLOCK
See Table 2-3
See Table 2-3
Low-Pass Filter,
(sin x)/x Filter
Adder/Subtractor
Transmit Section
D/A Conversion
Timing
†
D1 D0 SELECT
0
0
1
1
0
1
0
1
TA
TB Register
(6 Bits)
TA + TA′
TA – TA′
TA
7.20 kHz for TB = 40
8.00 kHz for TB = 36
9.60 kHz for TB = 30
14.4 kHz for TB = 20
16.0 kHz for TB = 18
19.2 kHz for TB = 15
See Table 2-3
See Table 2-2
9
18
TX (A) Counter
(6 Bits)
Divide By 2
TX (B) Counter
D/A Conversion
Frequency
288 kHz
576 kHz
RA′ Register
(6 Bits)
2s-Complement RA
RA Register
(5 Bits)
SCF CLOCK
See Table 2-3
See Table 2-3
Low-Pass Filter
Receive Section
A/D Conversion
Timing
Adder/Subtractor
†
D1 D0 SELECT
RB Register
(6 Bits)
0
0
1
1
0
1
0
1
RA
RA + RA′
RA – RA′
RA
7.20 kHz for RB = 40
8.00 kHz for RB = 36
9.60 kHz for RB = 30
14.4 kHz for RB = 20
16.0 kHz for RB = 18
19.2 kHz for RB = 15
See Table 2-3
9
18
See Table 2-2
RX (A) Counter
(6 Bits)
RX (B) Counter
Divide By 2
576 kHz
High-Pass Filter,
A/D Conversion
Frequency
288 kHz
†
These control bits are described in the DX Serial Data Word Format section.
NOTES: A. Tables 2–2 and 2–3 are primary and secondary communication protocols, respectively.
B. In synchronous operation, RA, RA’, RB, RX(A), and RX(B) are not used. TA, TA’, TB, TX(A), and TX(B) are
used instead.
C. Itemsin italics refer only to frequencies and register contents, which are variable. A crystal oscillator driving
20.736MHz into the TMS320-series DSP provides a master clock frequency of 5.184 MHz. The TLC32046
produces a shift clock frequency of 1.296 MHz. If the TX(A) register contents equal 9, the SCF clock
frequency is 288 kHz, and the D/A conversion frequency is 288 kHz ÷ T(B).
Figure 2–1. Asynchronous Internal Timing Configuration
2–3
2.2 Analog Input
Two pairs of analog inputs are provided. Normally, the IN+ and IN– input pair is used; however, the auxiliary
input pair, AUX IN+ and AUX IN–, can be used if a second input is required. Since sufficient common-mode
range and rejection are provided, each input set can be operated in differential or single-ended modes. The
gain for the IN+, IN–, AUX IN+, and AUX IN– inputs can be programmed to 1, 2, or 4 (see Table 4–1). Either
input circuit can be selected via software control. Multiplexing is controlled with the D4 bit (enable/disable
AUX IN+ and AUX IN–) of the secondary DX word (see Table 2–3). The multiplexing requires a 2-ms wait
at SCF = 288 kHz (see Figure 5–3) for a valid output signal. A wide dynamic range is ensured by the
differential internal analog architecture and the separate analog and digital voltage supplies and grounds.
2.3 A/D Band-Pass Filter, Clocking, and Conversion Timing
The receive-channel A/D high-pass filter can be selected or bypassed via software control (see Functional
Block Diagram). The frequency response of this filter is found in the electrical characteristic section. This
response results when the switched-capacitor filter clock frequency is 288 kHz and the A/D sample rate is
16 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the
filter clock frequency is not 288 kHz, the low-pass filter transfer function is frequency-scaled by the ratio of
the actual clock frequency to 288 kHz (see Typical Characteristics section). The ripple bandwidth and 3-dB
low-frequency roll-off points of the high-pass section are 300 Hz and 200 Hz, respectively. However, the
high-pass section low-frequency roll-off is frequency-scaled by the ratio of the A/D sample rate to 16 kHz.
Figure 2–1 and the DX serial data word format sections of this data manual indicate the many options for
attaining a 288-kHz band-pass switched-capacitor filter clock. These sections indicate that the RX(A)
counter can be programmed to give a 288-kHz band-pass switched-capacitor filter clock for several master
clock input frequencies.
The A/D conversion rate is attained by frequency-dividing the band-pass switched-capacitor filter clock with
the RX(B) counter. Unwanted aliasing is prevented because the A/D conversion rate is an integer
submultiple of the band-pass switched-capacitor filter sampling rate, and the two rates are synchronously
locked.
2.4 A/D Converter
Fundamental performance specifications for the receive channel ADC circuitry are in the electrical
characteristic section of this data manual. The ADC circuitry, using switched-capacitor techniques, provides
an inherent sample-and-hold function.
2.5 Analog Output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.
2.6 D/A Low-Pass Filter, Clocking, and Conversion Timing
Thefrequencyresponseresultswhenthelow-passswitched-capacitorfilterclockfrequencyis288kHz(see
equation1). LiketheA/Dfilter, thetransferfunctionofthisfilterisfrequency-scaledwhentheclockfrequency
is not 288 kHz (see Typical Characteristics section). A continuous-time filter is provided on the output of the
low-pass filter to eliminate the periodic sample data signal information, which occurs at multiples of the
288-kHz switched-capacitor clock feedthrough.
The D/A conversion rate is attained by frequency-dividing the 288-kHz switched-capacitor filter clock with
the T(B) counter. Unwanted aliasing is prevented because the D/A conversion rate is an integer submultiple
of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.
2.7 D/A Converter
Fundamental performance specifications for the transmit channel DAC circuitry are in the electrical
characteristic section. The DAC has a sample-and-hold function that is realized with a switched-capacitor
ladder.
2–4
2.8 Serial Port
The serial port has four possible configurations summarized in the function table on page 1–2. These
configurations are briefly described below.
•
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS320C17. The communications protocol is two 8-bit bytes.
The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, and TMS320C30. The communications protocol is
one 16-bit word.
•
•
The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS320C17. The communications protocol is two 8-bit bytes.
The transmit and receive sections are operated synchronously, and the serial port interfaces
directly with the TMS32020, TMS320C25, TMS320C30, or two SN74299 serial-to-parallel shift
registers, which can interface in parallel to the TMS32010, TMS320C15, to any other digital
signal processor, or to external FIFO circuitry. The communications protocol is one 16-bit word.
2.9 Synchronous Operation
When the transmit and receive sections are operated synchronously, the low-pass filter clock drives both
low-pass and band-pass filters (see Functional Block Diagram). The A/D conversion timing is derived from
and equal to the D/A conversion timing. When data bit D5 in the control register is a logic 1, transmit and
receive sections are synchronous. The band-pass switched-capacitor filter and the A/D converter timing are
derived from the TX(A) counter, the TX(B) counter, and the TA and TA’ registers. In synchronous operation,
both the A/D and the D/A channels operate from the same frequencies. The FSX and the FSR timing is
identicalduring primary communication, but FSR is not asserted during secondary communication because
there is no new A/D conversion result.
2.9.1
One 16-Bit Word (Dual-Word [Telephone Interface] or Word Mode)
The serial port interfaces directly with the serial ports of the TMS32020, TMS320C25, and the TMS320C30,
and communicates in one 16-bit word. The operation sequence is as follows:
1. The FSX and FSR pins are brought low by the TLC32046 AIC.
2. One 16-bit word is transmitted and one 16-bit word is received.
3. FSX and FSR are brought high.
4. EODX and EODR emit low-going pulses one shift clock wide. EODX and EODR are valid in the
word or byte mode only.
If the device is in the dual-word (telephone interface) mode, FSD goes low during the secondary
communication period and enables the data word received at the DATA-DR/CONTROL input to be routed
to the DR line. The secondary communication period occurs four shift clocks after completion of primary
communications.
2.9.2
Two 8-Bit Bytes (Byte Mode)
The serial port interfaces directly with the serial port of the TMS320C17 and communicates in two 8-bit
bytes. The operation sequence is as follows:
1. FSX and FSR are brought low.
2. One 8-bit word is transmitted and one 8-bit word is received.
3. EODX and EODR are brought low.
4. FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide.
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. FSX and FSR are brought high.
7. EODX and EODR are brought high.
2–5
2.9.3
Synchronous Operating Frequencies
The synchronous operating frequencies are determined by the following equations.
Switched capacitor filter (SCF) frequencies (see Figure 2–1):
master clock frequency
Low-pass SCF clock frequency
(D A and A D channels)
T(A)
2
High-pass SCF clock frequency (A D channel)
Conversion frequency (A D and D A channels)
A D conversion frequency
low-pass SCF clock frequency
T(B)
master clock frequency
T(A)
2
T(B)
NOTE: T(A), T(B), R(A), and R(B) are the contents of the TA, TB, RA, and RB registers, respectively.
2.10 Asynchronous Operation
When the transmit and the receive sections are operated asynchronously, the low-pass and band-pass filter
clocks are independently generated from the master clock. The D/A and the A/D conversion timing is also
determined independently.
D/A timing is set by the counters and registers described in synchronous operation, but the RA and RB
registers are substituted for the TA and TB registers to determine the A/D channel sample rate and the A/D
path switched-capacitor filter frequencies. Asynchronous operation is selected by control register bit D5
being zero.
2.10.1 One 16-Bit Word (Word Mode)
The serial port interfaces directly with the serial ports of the TMS32020, TMS320C25, and TMS320C30 and
communicates with 16-bit word formats. The operation sequence is as follows:
1. FSX or FSR are brought low by the TLC32046 AIC.
2. One 16-bit word is transmitted or one 16-bit word is received.
3. FSX or FSR are brought high.
4. EODX or EODR emit low-going pulses one shift clock wide. EODX and EODR are valid in either
the word or byte mode only.
2.10.2 Two 8-Bit Bytes (Byte Mode)
The serial port interfaces directly with the serial port of the TMS320C17 and communicates in two 8-bit
bytes. The operating sequence is as follows:
1. FSX or FSR are brought low by the TLC32046 AIC.
2. One byte is transmitted or received.
3. EODX or EODR are brought low.
4. FSX or FSR are brought high for four shift clock periods and then brought low.
5. The second byte is transmitted or received.
6. FSX or FSR are brought high.
7. EODX or EODR are brought high.
2.10.3 Asynchronous Operating Frequencies
The asynchronous operating frequencies are determined by the following equations.
Switched-capacitor filter frequencies (see Figure 2–1):
master clock frequency
Low-pass D A SCF clock frequency
T(A)
2
2–6
master clock frequency
R(A)
Low-pass A D SCF clock frequency
2
High-pass SCF clock frequency (A D channel)
A D conversion frequency
(2)
Conversion frequency:
D A conversion frequency
low-pass D A SCF clock frequency
T(B)
-
low-pass A D SCF clock frequency (for low pass receive filter)
R(B)
A D conversion frequency
(3)
NOTE: T(A), T(B), R(A), and R(B) are the contents of the TA, TB, RA, and RB registers, respectively.
2.11 Operation of TLC32046 With Internal Voltage Reference
The internal reference of the TLC32046 eliminates the need for an external voltage reference and provides
overall circuit cost reduction. The internal reference eases the design task and provides complete control
of the IC performance. The internal reference is brought out to REF. To keep the amount of noise on the
reference signal to a minimum, an external capacitor can be connected between REF and ANLG GND.
2.12 Operation of TLC32046 With External Voltage Reference
REF can be driven from an external reference circuit. This external circuit must be capable of supplying
250 µA and must be protected adequately from noise and crosstalk from the analog input.
2.13 Reset
A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the
control register. After a negative-going pulse on RESET, the AIC is initialized. This initialization allows
normal serial port communications activity to occur between AIC and DSP (see AIC DX Data Word Format
section). After RESET, TA=TB=RA=RB=18 (or 12 hexadecimal), TA′=RA′=01 (hexadecimal), the A/D
high-pass filter is inserted, the loop-back function is deleted, AUX IN+ and AUX IN– are disabled, transmit
and receive sections are in synchronous operation, programmable gain is set to 1, the on-board (sin x)/x
correction filter is not selected, D10OUT is set to 0, and D11OUT is set to 0.
2.14 Loopback
This feature allows the circuit to be tested remotely. In loopback, OUT+ and OUT– are internally connected
to IN+ and IN–. The DAC bits (D15 to D2), which are transmitted to DX, can be compared with the ADC bits
(D15 to D2), received from DR. The bits on DR equal the bits on DX. However, there is some difference in
these bits due to the ADC and DAC output offsets.
The loopback feature is implemented with digital signal processor control by transmitting a logic 1 for data
bit D3 in the DX secondary communication to the control register (see Table 2–3).
2–7
2.15 Communications Word Sequence
In the dual-word (telephone interface) mode, there are two data words that are presented to the DSP or µP
from the DR terminal. The first data word is the ADC conversion result occurring during the FSR time, and
the second is the serial data applied to DATA-DR during the FSD time. FSR is not asserted during secondary
communications and FSD is not asserted during primary communications.
Primary
Communications
Secondary
Communications
4 Shift
Clocks
TLC32046
DX-14 Bits Digital 11
From DSP to DAC
DX-14 Bits Digital XX
From DSP
FSX
DX
Input for D/A
Conversion
Input for Register
Program
TLC32046
TLC32046
Dual-Word
(telephone interface)
Mode Only
2s Complement Output
From ADC to the DSP
FSR
FSD
TLC32046
Dual-Word
(telephone interface)
Mode Only
16 bits Digital From
DATA-DR to DR
2s Complement Output
From ADC to the DSP
Data From DATA-DR
to the DSP
DR
TLC32046
Dual-Word
(telephone interface)
Mode Only
16 bits
16 bits
Figure 2–2. Primary and Secondary Communications Word Sequence
2.15.1 DR Word Bit Pattern
The data word is the 14-bit conversion result of the receive channel to the processor in 2s complement
format. With 16-bit processors, the data is 16 bits long with the two LSBs at zero.
A/D MSB
1st bit sent
A/D LSB
↓
↓
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
2–8
2.15.2 Primary DX Word Bit Pattern
Using 8-bit processors, the data word is transmitted in the same order as one 16-bit word, but as two bytes
with the two LSBs of the second byte set to zero.
A/D OR D/A MSB
1st bit sent
1st bit sent of 2nd byte
A/D or D/A LSB
↓
↓
↓
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 2–2. Primary DX Serial Communication Protocol
FUNCTIONS
D1
D0
D15 (MSB)-D2 → DAC Register.
TA → TX(A), RA → RX(A) (see Figure 2–1).
TB → TX(B), RB → RX(B) (see Figure 2–1).
0
0
D15 (MSB)-D2 → DAC Register.
TA+TA′ → TX(A), RA+RA′ → RX(A) (see Figure 2–1).
TB → TX(B), RB → RX(B) (see Figure 2–1).
The next D/A and A/D conversion period is changed by the addition of TA′ and RA′ master clock cycles,
in which TA′ and RA′ can be positive, negative, or zero (refer to Table 2–4).
0
1
1
0
D15 (MSB)-D2 → DAC Register.
TA–TA′ → TX(A), RA–RA′ → RX(A) (see Figure 2–1).
TB → TX(B), RB → RX(B) (see Figure 2–1).
ThenextD/AandA/DconversionperiodischangedbythesubtractionofTA′ andRA′ masterclockcycles,
in which TA′ and RA′ can be positive, negative, or zero (refer to Table 2–4).
D15 (MSB)-D2 → DAC Register.
TA → TX(A), RA → RX(A) (see Figure 2–1).
TB → TX(B), RB → RX(B) (see Figure 2–1).
1
1
After a delay of four shift cycles, a secondary transmission follows to program the AIC to operate in the
desired configuration. In the telephone interface mode, data on DATA DR is routed to DR during
secondary transmission.
NOTE: Settingthe two least significant bits to 1inthenormaltransmissionofDACinformation(primarycommunications)
to the AIC initiates secondary communications upon completion of the primary communications. When the
primary communication is complete, FSX remains high for four SHIFT CLOCK cycles and then goes low and
initiatesthesecondarycommunication. Thetimingspecificationsfortheprimaryandsecondarycommunications
are identical. In this manner, the secondary communication, if initiated, is interleaved between successive
primary communications. This interleaving prevents the secondary communication from interfering with the
primarycommunicationsandDACtiming. ThispreventstheAICfromskippingaDACoutput. FSRisnotasserted
during secondary communications activity. However, in the dual-word (telephone interface) mode, FSD is
asserted during secondary communications but not during primary communications.
2–9
2.15.3 Secondary DX Word Bit Pattern
D/A MSB
1st bit sent
1st bit sent of 2nd byte
D/A LSB
↓
↓
↓
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 2–3. Secondary DX Serial Communication Protocol
FUNCTIONS
D1
D0
D13 (MSB)-D9 → TA , 5 bits unsigned binary (see Figure 2–1).
D6 (MSB)-D2 → RA, 5 bits unsigned binary (see Figure 2–1).
0
0
D15, D14, D8, and D7 are unassigned.
D14 (sign bit)-D9 → TA′, 6 bits 2s complement (see Figure 2–1).
D7 (sign bit)-D2 → RA′, 6 bits 2s complement (see Figure 2–1).
D15 and D8 are unassigned.
0
1
1
0
D14 (MSB)-D9 → TB, 6 bits unsigned binary (see Figure 2–1).
D7 (MSB)-D2 → RB, 6 bits unsigned binary (see Figure 2–1).
D15 and D8 are unassigned.
D2 = 0/1 deletes/inserts the A/D high-pass filter.
D3 = 0/1 deletes/inserts the loopback function.
D4 = 0/1 disables/enables AUX IN+ and AUX IN–.
D5 = 0/1 asynchronous/synchronous transmit and receive sections.
D6 = 0/1 gain control bits (see Table 4–1).
1
1
D7 = 0/1 gain control bits (see Table 4–1).
D9 = 0/1 delete/insert on-board second-order (sinx)/x correction filter
D10 = 0/1 output to D10OUT (dual-word (telephone interface) mode)
D11 = 0/1 output to D11OUT (dual-word (telephone interface) mode)
D8, D12–D15 are unassigned.
2.16 Reset Function
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function
initializes all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on RESET initializes the AIC registers to provide a 16-kHz A/D and D/A conversion
rate for a 10.368-MHz master clock input signal. Also, the pass-bands of the A/D and D/A filters are 300
Hz to 7200 Hz and 0 Hz to 7200 Hz, respectively; therefore, the filter bandwidths are half those shown in
the filter transfer function specification section. The AIC, except the CONTROL register, is initialized as
follows (see AIC DX Data Word Format section):
REGISTER
INITIALIZED VALUE (HEX) 12
TA
TA′
01
TB
12
RA
12
RA′ RB
01 12
The CONTROL register bits are reset as follows (see Table 2–3):
D11 = 0, D10 = 0, D9 = 1, D7 = 1, D6 = 1, D5 = 1, D4 = 0, D3 = 0, D2 = 1
This initialization allows normal serial port communications to occur between the AIC and the DSP. If the
transmit and receive sections are configured to operate synchronously and the user wishes to program
different conversion rates, only the TA, TA′, and TB register need to be programmed. Both transmit and
receive timing are synchronously derived from these registers (see the Terminal Functions and DX Serial
Data Word Format sections).
Figure 2–3 shows a circuit that provides a reset on power-up when power is applied in the sequence given
in the power-up sequence section. The circuit depends on the power supplies reaching their recommended
values a minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
2–10
TLC32046
V
CC
+
5 V
200 kΩ
RESET
0.5 µF
– 5 V
V
CC
–
Figure 2–3. Reset on Power-Up Circuit
2.17 Power-Up Sequence
To ensure proper operation of the AIC and as a safeguard against latch-up, it is recommended that Schottky
diodes with forward voltages less than or equal to 0.4 V be connected from V to ANLG GND and from
CC–
V
toDGTLGND.Intheabsenceofsuchdiodes,powerisappliedinthefollowingsequence: ANLGGND
CC–
and DGTL GND, V
, then V
and V . Also, no input signal is applied until after power-up.
CC–
CC+ DD
2.18 AIC Register Constraints
The following constraints are placed on the contents of the AIC registers:
1. TA register must be ≥ 4 in word mode (WORD/BYTE= high).
2. TA register must be ≥ 5 in byte mode (WORD/BYTE= low).
3. TA′ register can be either positive, negative, or zero.
4. RA register must be ≥ 4 in word mode (WORD/BYTE = high).
5. RA register must be ≥ 5 in byte mode (WORD/BYTE = low).
6. RA′ register can be either positive, negative, or zero.
7. (TA register ± TA′ register) must be > 1.
8. (RA register ± RA′ register) must be > 1.
9. TB register must be ≥ 15.
10. RB register must be ≥ 15.
2.19 AIC Responses to Improper Conditions
The AIC has provisions for responding to improper conditions. These improper conditions and the response
of the AIC to these conditions are presented in Table 2–4.
2–11
Table 2–4. AIC Responses to Improper Conditions
IMPROPER CONDITION
AIC RESPONSE
TA register + TA′ register = 0 or 1
TA register – TA′ register = 0 or 1
Reprogram TX(A) counter with TA register value
TA register + TA′ register < 0
MODULO 64 arithmetic is used to ensure that a positive value is loaded into
TX(A) counter, i.e., TA register + TA′ register + 40 HEX is loaded into TX(A)
counter.
RA register + RA′ register = 0 or 1
RA register – RA′ register = 0 or 1
Reprogram RX(A) counter with RA register value
RA register + RA′ register = 0 or 1
MODULO 64 arithmetic is used to ensure that a positive value is loaded into
RX(A) counter, i.e., RA register + RA′ register + 40 HEX is loaded into RX(A)
counter.
TA register = 0 or 1
RA register = 0 or 1
AIC is shut down. Reprogram TA or RA registers after a reset.
TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
The AIC serial port no longer operates. Reprogram TA or RA registers after
a reset.
TB register < 15
Reprogram TB register with 12 HEX
Reprogram RB register with 12 HEX
Hold last DAC output
RB register < 15
AIC and DSP cannot communicate
2.20 Operation With Conversion Times Too Close Together
If the difference between two successive D/A conversion frame syncs is less than 1/25 kHz, the AIC
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly, and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A′ register result is too small. When incrementally
adjusting the conversion period via the A + A′ register options, the designer should not violate this
requirement (see Figure2–4).
t
t
1
2
Frame Sync
(FSX or FSR)
Ongoing Conversion
t
– t ≤ 1/25 kHz
1
2
Figure 2–4. Conversion Times Too Close Together
2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs – Asynchronous Operation
When incrementally adjusting the conversion period via the A + A′ or A – A′ register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC
during an FSX frame sync. The ongoing conversion period is then adjusted; however, either receive
conversion period A or conversion period B can be adjusted. For both transmit and receive conversion
periods, the incremental conversion period adjustment is performed near the end of the conversion period.
If there is sufficient time between t and t , the receive conversion period adjustment is performed during
1
2
receive conversion period A. Otherwise, the adjustment is performed during receive conversion period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see Figure 2–5).
2–12
t
1
FSX
FSR
Transmit Conversion Period
Receive Conversion
Period A
Receive Conversion
Period B
Figure 2–5. More Than One Receive Frame Sync Between Two Transmit Frame Syncs
2.22 More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs – Asynchronous Operation
When incrementally adjusting the conversion period via the A + A′ or A – A′ register options, a specific
protocol must be followed. For both transmit and receive conversion periods, the incremental conversion
period adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during an FSX frame sync. The ongoing transmit
conversion period is then adjusted. However, three possibilities exist for the receive conversion period
adjustment as shown in Figure 2–6. When the adjustment command is issued during transmit conversion
period A, receive conversion period A is adjusted if there is sufficient time between t and t . If there is not
1
2
sufficient time between t and t , receive conversion period B is adjusted. The third option is that the receive
1
2
portion of an adjustment command can be ignored if the adjustment command is sent during a receive
conversion period, which is adjusted due to a prior adjustment command. For example, if adjustment
commands are issued during transmit conversion periods A, B, and C, the first two commands may cause
receive conversion periods A and B to be adjusted, while the third receive adjustment command is ignored.
The third adjustment command is ignored since it was issued during receive conversion period B, which
already is adjusted via the transmit conversion period B adjustment command.
t
1
FSX
Transmit
Conversion
Period A
Transmit
Conversion
Period B
Transmit
Conversion
Period C
t
2
FSR
Receive Conversion Period A
Receive Conversion Period B
Figure 2–6. More Than One Transmit Frame Sync Between Two Receive Frame Syncs
2.23 More than One Set of Primary and Secondary DX Serial Communications
Occurring Between Two Receive Frame Syncs (See DX Serial Data Word
Format section) – Asynchronous Operation
The TA, TA′, TB, and control register information that is transmitted in the secondary communication is
accepted and applied during the ongoing transmit conversion period. If there is sufficient time between t
1
and t , the TA, RA′, and RB register information, sent during transmit conversion period A, is applied to
2
receive conversion period A; otherwise, this information is applied during receive conversion period B. If RA,
RA′, and RB register information has been received and is being applied during an ongoing conversion
period, any subsequent RA, RA′, or RB information received during this receive conversion period is
disregarded (see Figure 2–7).
2–13
t
1
Primary Secondary
Transmit
Primary Secondary
Primary Secondary
FSX
FSR
Transmit
Conversion
Preload B
Transmit
Conversion
Preload C
Conversion
Preload A
t
2
Receive
Conversion
Period A
Receive
Conversion
Period B
Figure 2–7. More Than One Set of Primary and Secondary DX
Serial Communications Between Two Receive Frame Syncs
2.24 System Frequency Response Correction
The (sin x)/x correction for the DAC zero-order sample-and-hold output can be provided by an on-board
second-order (sin x)/x correction filter (see Functional Block Diagram). This (sin x)/x correction filter can be
inserted into or omitted from the signal path by digital-signal-processor control (data bit D9 in the DX
secondary communications). When inserted, the (sin x)/x correction filter precedes the switched-capacitor
low-pass filter. When the TB register (see Figure 2–1) equals 15, the correction results of Figures 5–5, 5–6,
and 5–7 can be obtained.
The (sin x)/x correction [see section (sin x)/x] can also be accomplished by disabling the on-board
second-ordercorrectionfilterandperformingthe(sinx)/xcorrectionindigitalsignalprocessorsoftware. The
system frequency response can be corrected via DSP software to ± 0.1 dB accuracy to a band edge of
3000 Hz for all sampling rates. This correction is accomplished with a first-order digital correction filter, that
requires seven TMS320 instruction cycles. With a 200-ns instruction cycle, seven instructions represent an
overhead factor of 1.1% and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (Sin x)/x
Correction Section for more details).
2.25 (Sin x)/x Correction
If the designer does not wish to use the on-board second-order (sin x)/x correction filter, correction can be
accomplished in digital signal processor (DSP) software. (Sin x)/x correction can be accomplished easily
and efficiently in digital signal processor software. Excellent correction accuracy can be achieved to a band
edge of 3000 Hz by using a first-order digital correction filter. The results shown are typical of the numerical
correction accuracy that can be achieved for sample rates of interest. The filter requires seven instruction
cycles per sample on the TMS320 DS. With a 200-ns instruction cycle, nine instructions per sample
represents an overhead factor of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively.
This correction adds a slight amount of group delay at the upper edge of the 300-Hz to 3000-Hz band.
2.26 (Sin x)/x Roll-Off for a Zero-Order Hold Function
The (sin x)/x roll-off error for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz
for the various sampling rates is shown in Table 2–5 (see Figure 5–7).
2–14
Table 2–5. (sin x)/x Roll-Off Error
sin π f/f
s
Error = 20 log
π f/f
s
f
(Hz)
s
f = 3000 Hz
(dB)
7200
8000
9600
–2.64
–2.11
–1.44
–0.63
–0.50
–0.35
–0.21
14400
16000
19200
25000
The actual AIC (sin x)/x roll-off is slightly less than the figures in Table 2–5 because the AIC has less than
100% duty cycle hold interval.
2.27 Correction Filter
To externally compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter can be implemented
as shown in Figure 2–8.
+
Σ
u
X
y
(i + 1)
(i + 1)
+
(1 – p1) p2
X
– 1
Z
p1
Figure 2–8. First-Order Correction Filter
The difference equation for this correction filter is:
= p2 (1 – p1) u + p1 y
(4)
(5)
y
(i + 1)
(i + 1)
(i)
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
2
2
(p2) V (1–p1)
1–2 V p1 V cos (2p f/f ) + (p1)
| H (f) | 2
=
2
s
2.28 Correction Results
Table 2-6 shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz
sampling rates (see Figures 5–8, 5–9, and 5–10).
2–15
Table 2–6. (Sin x)/x Correction Table for f = 8000 Hz and f = 9600 Hz
s
s
ROLL-OFF ERROR (dB)
ROLL-OFF ERROR (dB)
f
= 8000 Hz
f = 9600 Hz
p1 = –0.1307
s
s
f (Hz)
p1 = –0.14813
p2 = 0.9888
p2 = 0.9951
300
600
–0.099
–0.089
–0.054
–0.002
0.041
–0.043
–0.043
0
900
1200
1500
1800
2100
2400
2700
3000
0
0
0.079
0.043
0.043
0.043
0
0.100
0.091
–0.043
–0.102
–0.043
2.29 TMS320 Software Requirements
The digital correction filter equation can be written in state variable form as follows:
= y k1 + u
y
k2
(i+1)
(i+1)
(i)
Where
k1 = p1
k2 = (1 – p1) p2
y(i) = filter state
u(i+1) = next I/O sample
The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper
shift) yields the correct result. With the assumption that the TMS320 processor page pointer and memory
configuration are properly initialized, the equation can be executed in seven instructions or seven cycles
with the following program:
ZAC
LT K2
MPY U
LTA K1
MPY Y
APAC
SACH (dma), (shift)
2–16
3
Specifications
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)
Supply voltage range, V
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
CC+
DD
Output voltage range, V
O
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
I
Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Operating free-air temperature range: TLC32046C . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC32046I . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC32046M . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range: TLC32046C, TLC32046I . . . . . . . . . . . . . –40°C to 125°C
TLC32046M . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Case temperature for 10 seconds: FN or FK package . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds:
N or J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTE 1: Voltage values for maximum ratings are with respect to V
.
CC–
3.2 Recommended Operating Conditions
MIN NOM
MAX
5.25
UNIT
V
Supply voltage, V
Supply voltage, V
(see Note 2)
(see Note 2)
4.75
–4.75
4.75
5
–5
5
CC+
–5.25
5.25
V
CC–
Digital supply voltage, V
(see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND
V
DD
0
V
Reference input voltage, V
(see Note 2)
2
2
4
V
ref(ext)
High-level input voltage, V
V
+0.3
DD
0.8
V
IH
Low-level input voltage, V (see Note 3)
IL
–0.3
300
V
Load resistance at OUT+ and/or OUT–, R
Ω
L
Load capacitance at OUT+ and/or OUT–, C
100
pF
MHz
V
L
MSTR CLK frequency (see Note 4)
5
10.368
±1.5
25
Analog input amplifier common mode input voltage (see Note 5)
A/D or D/A conversion rate
kHz
TLC32046C
TLC32046I
TLC32046M
0
–40
–55
70
85
Operating free-air temperature range, T
°C
A
125
NOTES: 2. Voltages at analog inputs and outputs, REF, V
, and V
are with respect to ANLG GND. Voltages at
CC+
CC–
are with respect to DGTL GND.
digital inputs and outputs and V
DD
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used
in this data manual for logic voltage levels only.
4. The band-pass switched-capacitor filter (SCF) specifications apply only when the low-pass section SCF
clock is 288 kHz and the high-pass section SCF clock is 16 kHz. If the low-pass SCF clock is shifted from
288 kHz, the low-pass roll-off frequency shifts by the ratio of the low-pass SCF clock to 288 kHz. If the
high-pass SCF clock is shifted from 16 kHz, the high-pass roll-off frequency shifts by the ratio of the
high-pass SCF clock to 16 kHz. Similarly, the low-pass switched-capacitor filter (SCF) specifications apply
onlywhen the SCF clock is 288 kHz. If the SCF clock is shifted from 288 kHz, the low-pass roll-offfrequency
shifts by the ratio of the SCF clock to 288 kHz.
5. This range applies when (IN+ – IN–) or (AUX IN+ – AUX IN–) equals ± 6 V.
3–1
3.3 Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, V
Otherwise Noted)
= 5 V, V
= –5 V, V
= 5 V (Unless
CC+
CC–
DD
3.3.1
Total Device, MSTR CLK Frequency = 5.184 MHz, Outputs Not Loaded
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
V
V
= 4.75 V,
= 4.75 V,
I
I
= –300 µA
2.4
OH
DD
OH
= 2 mA
0.4
35
V
OL
DD
OL
TLC32046C
Supply current from
I
TLC32046I
TLC32046M
TLC32046C
TLC32046I
TLC32046M
40
mA
mA
CC+
V
CC+
45
–35
–40
–45
7
Supply current from
I
I
CC–
V
CC –
Supply current from V
mA
V
DD
DD
TLC32046M
Internal reference
output voltage
V
2.9
3.3
ref
Temperature coefficient of internal
reference voltage
α
250
100
ppm/°C
kΩ
Vref
r
Output resistance at REF
o
3.3.2
Power Supply Rejection and Crosstalk Attenuation
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Idle channel, supply
signal at 200 mV p-p
measured at DR
(ADC output)
f = 0 kHz to 30 kHz
f = 30 kHz to 50 kHz
30
45
V
or V
supply voltage
CC –
CC+
dB
rejection ratio, receive channel
V
or V
supply voltage
CC –
Idle channel, supply
signal at 200 mV p-p
measured at OUT+
f = 0 kHz to 30 kHz
f = 30 kHz to 50 kHz
30
45
CC+
rejection ratio, transmit channel
(single-ended)
dB
TLC32046C, I
TLC32046M
80
80
Crosstalk attenuation, transmit-
to-receive (single-ended)
dB
dB
60
70
Crosstalk attenuation, receive-
to-transmit (single-ended)
TLC32046M
80
3.3.3
Serial Port
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
Input current
I
= –300 µA
2.4
OH
OH
OL
I
= 2 mA
0.4
±10
V
OL
I
I
µA
µA
pF
pF
I
Input current, DATA-DR/CONTROL
Input capacitance
±100
I
C
C
15
15
i
Output capacitance
o
†
All typical values are at T = 25°C.
A
3–2
3.3.4
Receive Amplifier Input
PARAMETER
TEST
CONDITIONS
†
MIN TYP
MAX
UNIT
mV
A/D converter offset error (filters in)
10
55
70
Common-mode rejection ratio at IN+, IN–, or AUX
IN+, AUX IN–
CMRR
See Note 6
dB
Input resistance at IN+, IN– or
AUX IN+, AUX IN+, AUX IN–, REF
r
100
kΩ
i
NOTE 6: The test condition is a 0-dBm, 1-kHz input signal with a 16-kHz conversion rate.
3.3.5
Transmit Filter Output
TEST
CONDITIONS
†
PARAMETER
MIN TYP
MAX
UNIT
Output offset voltage at OUT+ or
OUT– (single-ended relative to
ANLG GND)
TLC32046C, I
TLC32046M
15
15
80
85
mV
mV
V
OO
Maximum peak output voltage
R ≥ 300 Ω,
L
Offset voltage
= 0
TLC32046C, I
±3
±6
V
V
swing across R at OUT+ or OUT–
L
(single-ended)
V
OM
Maximum peak output voltage
swing between OUT+ and OUT–
(differential output)
R
≥ 600 Ω
L
†
All typical values are at T = 25°C.
A
3.3.6
Receive and Transmit Channel System Distortion, SCF Clock
Frequency = 288kHz (see Note 7)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Single-ended
Differential
70
70
65
65
70
70
65
65
Attenuation of second harmonic of
A/D input signal
dB
62
57
62
57
V = –0.1 dB to –24 dB
I
Single-ended
Differential
Attenuation of third and higher
harmonics of A/D input signal
dB
dB
dB
Single-ended
Differential
Attenuation of second harmonic of
D/A input signal
V = –0 dB to –24 dB
I
Single-ended
Differential
Attenuation of third and higher
harmonics of D/A input signal
†
All typical values are at T = 25°C.
A
3–3
3.3.7
Receive Channel Signal-to-Distortion Ratio (see Note 7)
‡
‡
‡
= 4
A
= 1
A
= 2
A
v
v
v
PARAMETER
TEST CONDITIONS
V = –6 dB to –0.1 dB
UNIT
MIN
58
58
56
50
44
38
32
26
20
MAX
MIN
MAX
MIN
MAX
§
§
I
§
V = –12 dB to –6 dB
I
58
58
56
50
44
38
32
26
V = –18 dB to –12 dB
I
58
58
56
50
44
38
32
V = –24 dB to –18 dB
I
A/D channel signal-to-
V = –30 dB to –24 dB
I
dB
V = –36 dB to –30 dB
I
V = –42 dB to –36 dB
I
V = –48 dB to –42 dB
I
V = –54 dB to –48 dB
I
‡
A is the programmable gain of the input amplifier.
v
§
Measurements under these conditions are unreliable due to overrange and signal clipping.
NOTE 7: The test condition is a 1-kHz input signal with a 16-kHz conversion rate. The load impedance for the DAC is
600 Ω. Input and output voltages are referred to V
.
ref
3.3.8
Transmit Channel Signal-to-Distortion Ratio (see Note 7)
PARAMETER
TEST CONDITIONS
MIN
58
58
56
50
44
38
32
26
20
MAX
UNIT
V = –6 dB to –0.1 dB
I
V = –12 dB to –6 dB
I
V = –18 dB to –12 dB
I
V = –24 dB to –18 dB
I
D/A channel signal-to-distortion ratio
V = –30 dB to –24 dB
I
dB
V = –36 dB to –30 dB
I
V = –42 dB to –36 dB
I
V = –48 dB to –42 dB
I
V = –54 dB to –48 dB
I
NOTE 7: The test condition is a 1-kHz input signal with a 16-kHz conversion rate. The load impedance for the DAC is
600 Ω. Input and output voltages are referred to V
.
ref
3.3.9
Receive and Transmit Gain and Dynamic Range (see Note 8)
†
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
dB
TYP
Transmit gain tracking error
Receive gain tracking error
C, I
V
= –48 dB to 0 dB signal range
±0.05 ±0.15
±0.05 ±0.15
O
C, I V = –48 dB to 0 dB signal range
dB
I
V
T
A
= –48 dB to 0 dB signal range,
= 25°C
O
Transmit gain tracking error
Receive gain tracking error
M
M
±0.05 ±0.25
±0.05 ±0.25
dB
dB
V = –48 dB to 0 dB signal range,
I
A
T
= 25°C
Transmit gain tracking error
Receive gain tracking error
M
M
±0.4
±0.4
dB
dB
V
T
A
= –48 dB to 0 dB signal range,
= –55°C TO 125°C
O
NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to V ).
ref
3–4
3.3.10 Receive Channel Band-Pass Filter Transfer Function, SCF f
= 288 kHz,
clock
‡
Input (IN+ – IN–) Is A ±3-V Sine Wave (see Note 9)
TEST
CONDITION
†
TYP
PARMETER
FREQUENCY
ADJUSTMENT
MIN
MAX
UNIT
f ≤ 100 Hz
K1 × 0 dB
–33
–4
–29
–25
–1
f = 200 Hz
K1 × –0.26 dB
K1 × 0 dB
–2
0
f = 300 Hz to 6200 Hz
f = 6200 Hz to 6600 Hz
f = 6600 Hz to 7300 Hz
f = 7600 Hz
–0.25
–0.3
0.25
0.3
K1 × 0 dB
0
Input signal
reference is 0 dB
Filter gain
K1 × 0 dB
0
0.5
dB
K1 × 2.3 dB
K1 × 2.7 dB
K1 × 3.2 dB
K1 × 0 dB
–2
–16
–0.5
–14
–40
–65
f = 8000 Hz
f ≥ 8800 Hz
f ≥ 10000 Hz
3.3.11 Receive and Transmit Channel Low-Pass Filter Transfer Function,
SCF f = 288 kHz (see Note 9)
clock
TEST
CONDITION
FREQUENCY
RANGE
ADJUSTMENT
†
MIN
MAX
UNIT
TYP
‡
ADDEND
K1 × 0 dB
K1 × 0 dB
K1 × 0 dB
f = 0 Hz to 6200 Hz
f = 6200 Hz to 6600 Hz
f = 6600 Hz to 7300 Hz
f = 7600 Hz
–0.25
–0.3
–0.5
0
0
0
0.25
0.3
0.5
Input signal
reference is 0 dB
Filter gain
K1 × 2.3 dB
K1 × 2.7 dB
K1 × 3.2 dB
K1 × 0 dB
–2
–0.5
–14
–40
–65
dB
f = 8000 Hz
–16
f ≥ 8800 Hz
f ≥ 10000 Hz
†
‡
All typical values are at T = 25°C.
A
The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF
may result from inaccuracies in the MSTR CLK frequency, resulting from crystal frequency tolerances. If this frequency
error is less than 0.25%, the ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications,
where K1 = 100 • [(SCF frequency – 288 kHz)/288 kHz]. For errors greater than 0.25%, see Note 9.
NOTE 9: The filter gain outside of the pass band is measured with respect to the gain at 1 kHz (2 kHz for M version).
The filter gain within the pass band is measured with respect to the average gain within the pass band. The
pass bands are 300 Hz to 7200 Hz and 0 to 7200 Hz for the band-pass and low-pass filters, respectively. For
switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of
switched-capacitor filter clock frequency to 288 kHz.
3–5
3.4 Operating Characteristics Over Recommended Operating Free-Air
Temperature Range, V = 5 V, V = –5 V, V = 5 V
CC+
CC–
DD
3.4.1
Receive and Transmit Noise (measurement includes low-pass and band-pass
switched-capacitor filters)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
500
450
400
400
300
300
UNIT
Broadband with (sin x)/x
Broadband without (sin x)/x
0 to 30 kHz with (sin x)/x
0 to 30 kHz without (sin x)/x
0 to 3.4 kHz with (sin x)/x
0 to 3.4 kHz without (sin x)/x
250
200
200
200
180
160
Transmit
noise
DX input = 00000000000000,
Constant input code
µVrms
0 to 6.8 kHz with (sin x)/x
(wide-band operation with 7.2 kHz
roll-off)
180
160
350
350
0 to 6.8 kHz without (sin x)/x
(wide-band operation with 7.2 kHz
roll-off)
300
18
500 µVrms
Receive noise (see Note 10)
Inputs grounded,
Gain = 1
dBrnc0
†
All typical values are at T = 25°C.
A
NOTE 10: The noise is computed by statistically evaluating the digital output of the A/D converter.
3.5 Timing Requirements
3.5.1
Serial Port Recommended Input Signals, TLC32046C and TLC32046I
PARAMETER
Master clock cycle time
MIN
MAX
UNIT
ns
t
t
t
95
c(MCLK)
r(MCLK)
f(MCLK)
Master clock rise time
10
10
ns
Master clock fall time
ns
Master clock duty cycle
25%
800
20
75%
RESET pulse duration (see Note 11)
DX setup time before SCLK↓
DX hold time after SCLK↓
ns
ns
ns
t
t
su(DX)
t
h(DX)
c(SCLK)/4
NOTE 11: RESET pulse duration is the amount of time that the RESET is held below 0.8 V after the power supplies have
reached their recommended values.
3.5.2
Serial Port Recommended Input Signals, TLC32046M
PARAMETER
†
TYP
MIN
MAX
UNIT
ns
t
t
t
Master clock cycle time
95
c(MCLK)
r(MCLK)
f(MCLK)
Master clock rise time
10
10
ns
Master clock fall time
ns
Master clock duty cycle
50%
RESET pulse duration (see Note 11)
DX setup time before SCLK↓
800
28
ns
ns
ns
t
t
su(DX)
DX hold time after SCLK↓
t
c(SCLK)/4
h(DX)
NOTE 11: RESET pulse duration is the amount of time that the RESET is held below 0.8 V after the power supplies have
reached their recommended values.
3–6
3.5.3
Serial Port – AIC Output Signals, C = 30 pF for SHIFT CLK Output, C = 15 pF
For All Other Outputs, TLC32046C and TLC32046I
L
L
†
PARAMETER
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
MIN TYP
MAX
UNIT
ns
t
t
t
380
c(SCLK)
f(SCLK)
r(SCLK)
3
3
8
8
ns
Shift clock (SCLK) rise time
ns
Shift clock (SCLK) duty cycle
Delay from SCLK↑ to FSR/FSX/FSD↓
45%
55%
t
t
t
t
t
t
t
t
t
t
t
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CH-FL)
d(CH-FH)
d(CH-DR)
d(CH-EL)
d(CH-EH)
f(EODX)
Delay from SCLK↑ to FSR/FSX/FSD↑
DR valid after SCLK↑
90
90
90
90
8
Delay from SCLK↑ to EODX/EODR↓ in word mode
Delay from SCLK↑ to EODX/EODR↑ in word mode
EODX fall time
2
2
EODR fall time
8
f(EODR)
Delay from SCLK↑ to EODX/EODR↓ in byte mode
Delay from SCLK↑ to EODX/EODR↑ in byte mode
Delay from MSTR CLK↑ to SCLK↓
Delay from MSTR CLK↑ to SCLK↑
90
90
170
170
d(CH-EL)
d(CH-EH)
d(MH-SL)
d(MH-SH)
65
65
†
Typical values are at T = 25°C.
A
3.5.4
Serial Port – AIC Output Signals, C = 30 pF for SHIFT CLK Output, C = 15 pF
For All Other Outputs, TLC32046M
L
L
†
PARAMETER
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
MIN TYP
MAX
UNIT
ns
t
t
t
400
c(SCLK)
f(SCLK)
r(SCLK)
3
3
ns
Shift clock (SCLK) rise time
ns
Shift clock (SCLK) duty cycle
Delay from SCLK↑ to FSR/FSX/FSD↓
45%
55%
250
250
250
250
250
t
t
t
t
t
t
t
t
t
t
t
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CH-FL)
d(CH-FH)
d(CH-DR)
d(CH-EL)
d(CH-EH)
f(EODX)
Delay from SCLK↑ to FSR/FSX/FSD↑
DR valid after SCLK↑
Delay from SCLK↑ to EODX/EODR↓ in word mode
Delay from SCLK↑ to EODX/EODR↑ in word mode
EODX fall time
2
2
EODR fall time
f(EODR)
Delay from SCLK↑ to EODX/EODR↓ in byte mode
Delay from SCLK↑ to EODX/EODR↑ in byte mode
Delay from MSTR CLK↑ to SCLK↓
Delay from MSTR CLK↑ to SCLK↑
250
250
170
170
d(CH-EL)
d(CH-EH)
d(MH-SL)
d(MH-SH)
65
65
†
Typical values are at T = 25°C.
A
3–7
3–8
4 Parameter Measurement Information
R
fb
R
R
IN +
or
AUX IN+
–
+
To Multiplexer
IN –
or
AUX IN–
–
+
R
fb
R
= R for D6 = 1 and D7 = 1
D6 = 0 and D7 = 0
fb
R
R
= 2R for D6 = 1 and D7 = 0
= 4R for D6 = 0, and D7 = 1
fb
fb
Figure 4–1. IN+ and IN – Gain Control Circuitry
Table 4–1. Gain Control Table (Analog Input Signal Required for
†
Full-Scale Bipolar A/D Conversion Twos Complement)
CONTROL REGISTER BITS
INPUT
CONFIGURATIONS
A/D CONVERSION
RESULT
ANALOG
INPUT
‡§
D6
D7
1
0
1
0
V
= ±6 V
±full scale
ID
Differential configuration
Analog input = IN+ – IN–
= AUX IN+ – AUX IN–
1
0
0
1
V
V
= ±3 V
±full scale
±full scale
ID
= ±1.5 V
ID
1
0
1
0
V = ±3 V
±half scale
I
Single-ended configuration
Analog input = IN+ – ANLG GND
= AUX IN+ –ANLG GND
1
0
0
1
V = ±3 V
I
±full scale
±full scale
V = ±1.5 V
I
†
‡
§
V
V
= 5 V, V
= –5 V, V = 5 V
DD
CC+
ID
CC–
= Differential Input Voltage, V = Input voltage referenced to ground with IN– or AUX IN– connected to GND.
I
In this example, V is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not
exceed 0.1 dB below full scale.
ref
4–1
t
c (SCLK)
SHIFT
CLK
2 V
2 V
2 V
2 V
8 V
8 V
t
d (CH-FL)
t
d (CH-FH)
2 V
FSX, FSR, FSD
DR
8 V
t
d (CH-DR)
D15
D14
D13
D12
D11
D2
D1
D0
t
su (DX)
Don’t Care
DX
D15
D14
D13
D13
D12
D12
D11
D11
D2
D2
D1
D1
D0
D0
DATA-DR
D15
D14
Figure 4–2. Dual-Word (Telephone Interface) Mode Timing
t
c (SCLK)
2 V 2 V
SHIFT
CLK
2 V
2 V
8 V
8 V
t
t
(CH-FH)
d (CH-FL)
d
†
2 V
FSX, FSR
8 V
t
d (CH–DR)
DR
D15
D14
D13
D12
D11
D2
D1
D0
t
su (DX)
Don’t Care
DX
D15
D14
D13
D12
D11
D2
D1
D0
d (CH-EL)
8 V
t
h (DX)
t
t
d (CH-EH)
2 V
‡
EODX, EODR
Figure 4–3. Word Timing
†
‡
The time between falling edges of FSR is the A/D conversion period and the time between falling edges of FSX is the
D/A conversion period.
In the word format, EODX and EODR go low to signal the end of a 16-bit data word to the processor. The word-cycle
is 20 shift-clocks wide, giving a four-clock period setup time between data words.
4–2
t
t
c (SCLK)
t
f (SCLK)
2 V
r (SCLK)
SHIFT
CLK
2 V
d (CH-FL)
2 V
2 V
2 V
2 V
t
d (CH-FH)
t
t
t
d (CH-FH)
2 V
d (CH-FL)
FSR,
FSX
2 V
8 V
8 V
t
d (CH-DR)
D14
D14
D13
D9
D8
D7
D1
D0
DR
D15
D6
D2
t
su (DX)
D15
Don’t Care
DX
D13
t
D9
D8
D12
D11
D2
D1
D0
t
h (DX)
t
d (CH-EH)
d (CH-EL)
EODR,
EODX
2 V
8 V
Figure 4–4. Byte-Mode Timing
†
The time between falling edges of FSR is the A/D conversion period, and the time between fallling edges of FSX is the D/A conversion period.
In the byte mode, when EODX or EODR is high, the first byte is transmitted or received, and when these signals are low, the second byte is
transmitted or received. Each byte-cycle is 12 shift-clocks long, allowing for a four-shift-clock setup time between byte transmissions.
‡
MSTR CLK
SHIFT CLK
t
t
d (MH-SL)
d (MH-SH)
Figure 4–5. Shift-Clock Timing
4.1 TMS32010/TMS320C15 – TLC32046 Interface Circuit
CLK OUT
DEN
S0,G1
Valid
D0–D15
IN INSTRUCTION TIMING
CLK OUT
WE
SN74LS138 Y1
SN74LS299 CLK
D0–D15
Valid
OUT INSTRUCTION TIMING
Figure 4–6. TMS32010/TMS320C15–TLC32046 Interface Timing
4–4
SN74LS74
2D
C2
Q
FSX
DX
SN74LS299
Q
S1
G2
H
DEN
S0 CLK
G1
G1
A
D8–D15
Y1
Y0
A0/PA0
SHIFT
CLK
A–H
SR
A1/PA1
A2/PA2
B
C
SN74LS138
SN74LS299
TLC32046
Q
S1
G2
TMS32010
H
S0 CLK
G1
SN74LS74
C1
DO–D15
DO–D15
A–H
SR
Q
1D
DR
DO–D7
WE
CLK
OUT
MSTR
CLK
INT
EODX
Figure 4–7. TMS32010/TMS320C15 – TLC32046 Interface Circuit
4–5
4–6
5 Typical Characteristics
D/A AND A/D LOW-PASS FILTER
RESPONSE SIMULATION
0.4
T
= 25°C
A
Input = ± 3 V Sine Wave
0.2
0
– 0.2
– 0.4
– 0.6
0
1
2
3
4
5
6
7
8
9
10
Normalized Frequency
Figure 5–1
D/A AND A/D LOW-PASS FILTER RESPONSE
0
See Figure 2-1
for Pass Band
Detail
T = 25°C
A
– 10
Input = ± 3 V Sine Wave
– 20
– 30
– 40
– 50
– 60
– 70
– 80
– 90
0
2
4
6
8
10 12 14 16 18 20
Normalized Frequency
Figure 5–2
Normalized Frequency
288
288 kHz, please call the factory.
SCF f
(kHz)
clock
NOTE : Absolute Frequency (kHz)
For Low-Pass SCF f
clock
5–1
D/A AND A/D LOW-PASS GROUP DELAY
T
= 25°C
A
0.9
0.8
0.7
0.6
0.5
0.4
0.3
Input = ± 3 V Sine Wave
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
Normalized Frequency
Figure 5–3
A/D BAND-PASS RESPONSE
0.4
0.2
High-Pass SCF f
= 16 kHz
clock
T
A
= 25°C
Input = ±3 V Sine Wave
0
– 0.2
–0.4
– 0.6
0
1
2
3
4
5
6
7
8
9
10
Normalized Frequency
Figure 5–4
Normalized Frequency
288
288 kHz, please call the factory.
SCF f
(kHz)
clock
NOTE : Absolute Frequency (kHz)
For Low-Pass SCF f
clock
5–2
A/D BAND-PASS FILTER RESPONSE SIMULATION
0
High-Pass SCF
– 10
f
T
A
= 16 kHz
= 25°C
clock
Input = ± 3 V Sine Wave
– 20
– 30
– 40
– 50
– 60
– 70
– 80
– 100
0
2
4
6
8
10 12 14 16 18 20
Normalized Frequency
Figure 5–5
A/D BAND-PASS FILTER GROUP DELAY
2
High-Pass SCF f
= 16 kHz
clock
1.8
1.6
1.4
1.2
1.1
0.8
0.6
T
A
= 25°C
Input = ±3 V Sine WWave
0.4
0.2
0
0
0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0
Normalized Frequency
Figure 5–6
Normalized Frequency
288
288 kHz, please call the factory.
SCF f
(kHz)
clock
NOTE : Absolute Frequency (kHz)
For Low-Pass SCF f
clock
5–3
A/D CHANNEL HIGH-PASS FILTER
20
10
T
= 25°C
A
Input = ± 3 V Sine Wave
0
– 10
– 20
– 30
– 40
– 50
– 60
0
100 200 300 400 500 600 700 800 900 1000
Normalized Frequency
Figure 5–7
D/A (sin x)/x CORRECTION FILTER RESPONSE
4
2
0
– 2
T
= 25°C
– 4
– 6
A
Input = ± 3 V Sine Wave
0
2
4
6
8
10 12 14 16 18 20
Normalized Frequency
Figure 5–8
Normalized Frequency
288
288 kHz, please call the factory.
SCF f
(kHz)
clock
NOTE : Absolute Frequency (kHz)
For Low-Pass SCF f
clock
5–4
D/A (sin x)/x CORRECTION FILTER RESPONSE
500
T
A
= 25°C
Input = ± 3 V Sine Wave
400
300
200
100
0
0
2
4
6
8
10 12 14 16 18 20
Normalized Frequency
Figure 5–9
D/A (sin x)/x CORRECTION ERROR
2
1.6
T
= 25°C
A
Input = ± 3 V Sine Wave
1.2
(sin x) /x Correction
Error
0.8
0.4
0
– 0.4
– 0.8
19.2 kHz (sin x) /x
Distortion
– 1.2
– 1.6
– 2
0
1
2
3
4
5
6
7
8
9
10
Normalized Frequency
Figure 5–10
Normalized Frequency
288
288 kHz, please call the factory.
SCF f
(kHz)
clock
NOTE : Absolute Frequency (kHz)
For Low-Pass SCF f
clock
5–5
A/D BAND-PASS GROUP DELAY
760
720
680
640
600
Low-pass SCF f
= 144 kHz
= 8 kHz
clock
High-pass SCF f
clock
T
A
= 25°C
Input = ± 3 V Sine Wave
560
520
480
440
400
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
f – Frequency – Hz
Figure 5–11
D/A LOW-PASS GROUP DELAY
560
Low-pass SCF f
= 144 kHz
clock
520
480
440
400
360
T
A
= 25°C
Input = ± 3 V Sine Wave
320
280
240
200
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
f – Frequency – Hz
Figure 5–12
5–6
A/D SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
100
90
80
70
60
50
1-kHz Input Signal
16-kHz Conversion Rate
T
A
= 25°C
Gain = 1
Gain = 4
40
30
20
10
0
– 50
– 40
– 30
– 20
– 10
0
10
Input Signal Relative to V – dB
ref
Figure 5–13
A/D GAIN TRACKING
(GAIN RELATIVE TO GAIN AT 0-dB INPUT SIGNAL)
0.5
1-kHz Input Signal
16-kHz Conversion Rate
= 25°C
0.4
0.3
0.2
0.1
T
A
– 0.1
– 0.2
– 0.3
– 0.4
– 0.5
– 50
– 40
– 30
– 20
– 10
0
10
Input Signal Relative to V – dB
ref
Figure 5–14
5–7
D/A CONVERTER SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
100
1-kHz Input Signal Into 600 Ω
90
80
70
60
50
16-kHz Conversion Rate
= 25°C
T
A
40
30
20
10
0
–50
–40
–30
–20
–10
0
10
Input Signal Relative to V – dB
ref
Figure 5–15
D/A GAIN TRACKING (GAIN RELATIVE TO GAIN
AT 0-dB INPUT SIGNAL)
0.5
1-kHz Input Signal Into 600 Ω
16-kHz Conversion Rate
0.4
0.3
0.2
0.1
0
T
= 25°C
A
–0.1
–0.2
–0.3
–0.4
–0.5
–50
–40
–30
–20
–10
0
10
Input Signal Relative to V – dB
ref
Figure 5–16
5–8
A/D SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL
– 100
– 90
– 80
– 70
– 60
– 50
1-kHz Input Signal
16-kHz Conversion Rate
T
A
= 25°C
– 40
– 30
– 20
– 10
0
– 50
– 40
– 30
– 20
– 10
0
10
Input Signal Relative to V – dB
ref
Figure 5–17
D/A SECOND HARMONIC DISTORTION
vs
INPUT SIGNAL
– 100
1-kHz Input Signal Into 600 Ω
– 90 16-kHz Conversion Rate
= 25°C
T
A
– 80
– 70
– 60
– 50
– 40
– 30
– 20
– 10
0
– 50
– 40
– 30
– 20
– 10
0
10
Input Signal Relative to V – dB
ref
Figure 5–18
5–9
A/D THIRD HARMONIC DISTORTION
vs
INPUT SIGNAL
– 100
– 90
– 80
– 70
– 60
– 50
1-Hz Input Signal
16-kHz Conversion Rate
T
A
= 25°C
– 40
– 30
– 20
– 10
0
– 50
– 40
– 30
– 20
– 10
0
10
Input Signal Relative to V – dB
ref
Figure 5–19
D/A THIRD HARMONIC DISTORTION
vs
INPUT SIGNAL
– 100
– 90
– 80
– 70
– 60
– 50
1-kHz Input Signal Into 600 Ω
16-kHz Conversion Rate
T
A
= 25°C
– 40
– 30
– 20
– 10
0
– 50
– 40
– 30
– 20
– 10
0
10
Input Signal Relative to V – dB
ref
Figure 5–20
5–10
6 Application Information
TMS32020/C25
TLC32046
MSTR CLK
CLKOUT
FSX
V
+
+ 5 V
CC
REF
ANLG GND
FSX
C
C
DX
DX
†
FSR
FSR
BAT 42
C
DR
DR
V
CC
–
– 5 V
CLKR
CLKX
SHIFT CLK
V
DD
+ 5 V
0.1 µF
DGTL GND
D
A
C = 0.2 µF, Ceramic
Figure 6–1. AIC Interface to the TMS32020/C25 Showing Decoupling Capacitors
†
and Schottky Diode
†
Thomson Semiconductors
V
CC
R
3 V Output
500 Ω
0.01 µF
TL431
2500 Ω
D
FOR: V
= 12 V, R = 7200 Ω
= 10 V, R = 5600 Ω
= 5 V, R = 1600 Ω
CC
CC
CC
V
V
Figure 6–2. External Reference Circuit for TLC32046
6–1
6–2
相关型号：
©2020 ICPDF网 联系我们和版权申明