5962-9221503MRA [TI]
具有清零端的八路 D 型触发器 | J | 20 | -55 to 125;型号: | 5962-9221503MRA |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有清零端的八路 D 型触发器 | J | 20 | -55 to 125 逻辑集成电路 触发器 锁存器 |
文件: | 总7页 (文件大小:80K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT273T
SCCS020 - March 1995 - Revised February 2000
8-Bit Register
Features
Functional Description
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.8 ns max. (Com’l)
FCT-A speed at 7.2 ns max. (Com’l)
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
The FCT273T consists of eight edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The common
buffered clock (CP) and master reset (MR) load and reset all
flip-flops simultaneously. The FCT273T is an edge-triggered
register. The state of each D input (one set-up time before the
LOW-to-HIGH clock transition) is transferred to the corre-
sponding flip-flop’s Q output. All outputs will be forced LOW by
a low voltage level on the MR input.
• Power-off disable feature
• Matched rise and fall times
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
• ESD > 2000V
• Fully compatible with TTL input and output logic levels
• Extended commercial range of −40˚C to +85˚C
• Sink current
Source current
64 mA (Com’l), 32 mA (Mil)
32 mA (Com’l), 12 mA (Mil)
Logic Block Diagram
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
MR
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
FCT273T–1
PinConfigurations
Logic Symbol
LCC
DIP/SOIC/QSOP
Top View
Top View
MR
1
2
3
4
5
6
7
8
9
10
V
20
19
18
17
16
CC
Q
0
Q
7
7
6 5 4
8
Q
D
0
D
0
D
7
3
9
3
2
1
20
19
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
CP
Q
4
Q
0
MR
V
CC
10
11
12
13
D
1
D
CP
6
Q
1
Q
6
MR
Q
2
Q
5
15
14
D
4
Q
7
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
D
2
D
5
1516 17 18
14
D
D
3
13
12
11
4
Q
3
Q
4
FCT273T–4
GND
FCT273T–2
CP
FCT273T–3
Function Table[1]
Inputs
CP
Output
Operating Mode
Reset (clear)
Load ‘1’
MR
L
D
Q
L
X
X
h
l
H
H
L
Load ‘0’
H
Note:
1.
H
h
L
l
= HIGH Voltage Level steady state
= HIGH Voltage Level one set-up time prior to LOW-to-HIGH clock transition
= LOW Voltage Level steady state
= LOW Voltage Level one set-up time prior to the LOW-to-HIGH transition
= Don’t Care
X
= LOW-to-HIGH clock transition
Copyright © 2000, Texas Instruments Incorporated
CY54/74FCT273T
Maximum Ratings[2, 3]
Operating Range
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Ambient
Range
Range
Temperature
–40°C to +85°C
–55°C to +125°C
VCC
Storage Temperature .....................................−65°C to +150°C
Commercial All
Military[4]
5V ± 5%
5V ± 10%
Ambient Temperature with
Power Applied..................................................−65°C to +135°C
All
Supply Voltage to Ground Potential..................−0.5V to +7.0V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin).......120 mA
Power Dissipation ..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VCC=Min., IOH=–32 mA
Min.
2.0
Typ.[5]
Max.
Unit
V
VOH
Output HIGH Voltage
Com’l
Com’l
Mil
VCC=Min., IOH=–15 mA
VCC=Min., IOH=–12 mA
VCC=Min., IOL=64 mA
VCC=Min., IOL=32mA
2.4
3.3
3.3
0.3
0.3
V
2.4
V
VOL
Output LOW Voltage
Com’l
Mil
0.55
0.55
V
V
VIH
VIL
VH
VIK
II
Input HIGH Voltage
Input LOW Voltage
Hysteresis[6]
2.0
V
0.8
V
All inputs
0.2
V
Input Clamp Diode Voltage
Input HIGH Current
Input HIGH Current
Input LOW Current
VCC=Min., IIN=–18 mA
VCC=Max., VIN=VCC
VCC=Max., VIN=2.7V
VCC=Max., VIN=0.5V
–0.7
–1.2
5
V
µA
µA
µA
mA
µA
IIH
±1
IIL
±1
IOS
IOFF
Output Short Circuit Current[7] VCC=Max., VOUT=0.0V
–60
–120
–225
±1
Power-Off Disable
VCC=0V, VOUT=4.5V
Capacitance[6]
Parameter
Description
Typ.[5]
Max.
10
Unit
CIN
Input Capacitance
Output Capacitance
5
9
pF
pF
COUT
12
Notes:
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. TA is the “instant on” case temperature
5. Typical values are at VCC=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
2
CY54/74FCT273T
Power Supply Characteristics
Parameter
ICC
Description
Test Conditions
Typ.[5]
0.1
Max.
0.2
Unit
mA
mA
Quiescent Power Supply Current VCC=Max., VIN ≤ 0.2V, VIN ≥ VCC-0.2V
Quiescent Power Supply Current VCC=Max., VIN=3.4V, f1=0, Outputs Open [8]
∆ICC
0.5
2.0
(TTL inputs HIGH)
ICCD
Dynamic Power Supply Current[9] VCC=Max., One Bit Toggling, 50% Duty Cycle,
0.06
0.7
1.2
1.6
0.12
1.4
mA/MHz
mA
Outputs Open, MR=VCC
,
V
IN ≤ 0.2V or VIN ≥ VCC-0.2V
IC
Total Power Supply Current[10]
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling at f1=5 MHz,
MR=VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling at f1=5 MHz,
MR=VCC, VIN=3.4V or VIN=GND
3.4
mA
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, Eight Bits Toggling
3.2[11]
mA
at f1=2.5MHz, MR=VCC
,
V
IN ≤ 0.2V or VIN ≥ VCC-0.2V
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, Eight Bits Toggling
3.9
12.2[11]
mA
at f1=2.5 MHz, MR=VCC
,
VIN=3.4V or VIN=GND
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. IC
IC
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0
f1
N1
=
=
=
Clock frequency for registered devices, otherwise zero
Input signal frequency
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
3
CY54/74FCT273T
Switching Characteristics Over the Operating Range[12]
FCT273T
Commercial
FCT273AT
Military Commercial
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit Fig. No.[13]
tPLH
tPHL
Propagation Delay Clock to Output
2.0
13.0
2.0
8.3
2.0
7.2
ns
1, 5
tPLH
tPHL
Propagation Delay MR to Output
2.0
13.0
2.0
8.3
2.0
7.2
ns
1, 6
tS
Set-Up Time HIGH or LOW D to Clock
Hold Time HIGH or LOW D to Clock
Clock Pulse Width HIGH or LOW
MR Pulse Width LOW
2.0
1.5
6.0
6.0
2.0
2.0
1.5
6.0
6.0
2.5
2.0
1.5
6.0
6.0
2.0
ns
ns
ns
ns
ns
4
4
5
6
6
tH
tW
tW
tREC
Recovery Time MR to Clock
FCT273CT
Commercial
Parameter
Description
Min.
Max.
Unit
Fig. No.[13]
tPLH
tPHL
Propagation Delay Clock to Output
2.0
5.8
ns
1, 5
tPLH
tPHL
Propagation Delay MR to Output
2.0
6.1
ns
1, 6
tS
Set-Up Time HIGH or LOW D to Clock
Hold Time HIGH or LOW D to Clock
Clock Pulse Width HIGH or LOW
MR Pulse Width LOW
2.0
1.5
6.0
6.0
2.0
ns
ns
ns
ns
ns
4
4
5
6
6
tH
tW
tW
tREC
Recovery Time MR to Clock
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
5.8
CY74FCT273CTQCT
CY74FCT273CTSOC/SOCT
CY74FCT273ATQCT
Q5
20-Lead (150-Mil) QSOP
Commercial
Commercial
Military
S5
20-Lead (300-Mil) Molded SOIC
20-Lead (150-Mil) QSOP
7.2
8.3
Q5
CY74FCT273ATSOC/SOCT
CY54FCT273ATLMB
S5
20-Lead (300-Mil) Molded SOIC
20-Square Leadless Chip Carrier
20-Lead (300-Mil) CerDIP
L61
D6
CY54FCT273ATDMB
13.0
CY74FCT273TQCT
Q5
20-Lead (150-Mil) QSOP
Commercial
CY74FCT273TSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
Notes:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
Document #: 38-00380-A
4
CY54/74FCT273T
Package Diagrams
20-Pin Square Leadless Chip Carrier L61
20-Lead (300-Mil) CerDIP D6
MIL-STD-1835 D- 8 Config.A
MIL-STD-1835 C-2A
20-Lead Quarter Size Outline Q5
5
CY54/74FCT273T
Package Diagrams (continued)
20-Lead (300-Mil) Molded SOIC S5
6
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Copyright 2000, Texas Instruments Incorporated
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