5962-9222301M3A [TI]
具有三态输出的八路总线寄存收发器 | FK | 28 | -55 to 125;
| 型号： | 5962-9222301M3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的八路总线寄存收发器 | FK | 28 | -55 to 125 驱动 总线驱动器 总线收发器 |
| 文件： | 总8页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT646T
SCCS031 - July 1994 - Revised March 2000
8-Bit Registered Transceiver
Features
Functional Description
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.4 ns max. (Com’l)
FCT-A speed at 6.3 ns max. (Com’l)
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature permits live insertion
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
The FCT646T consists of a bus transceiver circuit with
three-state, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes to
a HIGH logic level. Enable Control G and direction pins are
provided to control the transceiver function. In the transceiver
mode, data present at the high-impedance port may be stored
in either the A or B register, or in both. The select controls can
multiplex stored and real-time (transparent mode) data. The
direction control determines which bus will receive data when
the enable control G is Active LOW. In the isolation mode
(enable Control G HIGH), A data may be stored in the B reg-
ister and/or B data may be stored in the A register.
• Sink current
Source current
64 mA (Com’l), 48 mA (Mil)
32 mA (Com’l), 12 mA (Mil)
The outputs of the FCT646T are designed with a power-off
disable feature to allow for live insertion of boards.
• Independent register for A and B buses
• Extended commercial range of −40˚C to +85˚C
Function Block Diagrams
Pin Configurations
LCC
QSOP, SOIC
Top View
G
Top View
1
V
CPAB
SAB
DIR
24
CC
DIR
CPBA
2
CPBA
SBA
G
23
1110 9
12
13
14
8 7 6 5
SBA
CPAB
SAB
3
22
A
7
4
3
2
1
DIR
SAB
4
A
1
21
A
8
GND
NC
A
2
5
CPAB
NC
V
CC
B
1
20
15
16
17
A
3
6
B
2
19
18
17
16
B
B
B
8
7
6
28
27
A
4
B
3
7
CPBA
SBA
A
5
B
4
18
26
8
D
19 20 21 22 23 24 25
A
6
B
5
9
C
A
7
B
6
10
11
12
15
14
A
8
B
7
GND
B
8
13
B
1 Logic Block Diagram
A
1
D
C
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CPAB
SAB
DIR
CPBA
SBA
G
B
B
B
B
B
B
B
B
8
1
2
3
4
5
6
7
TO 7 OTHER CHANNELS
Pin Description
Name
Description
A
Data Register A Inputs, Data Register B Outputs
Data Register B Inputs, Data Register A Outputs
Clock Pulse Inputs
B
CPAB, CPBA
SAB, SBA
DIR, G
Output Data Source Select Inputs
Output Enable Inputs
Copyright © 2000, Texas Instruments Incorporated
CY54/74FCT646T
BUS A
BUS B
BUS A
BUS B
DIR
L
G
L
CPAB
X
CPBA
X
SAB
X
SBA
L
DIR
H
G
L
CPAB
X
CPBA
X
SAB
L
SBA
X
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
BUS A
BUS B
BUS A
BUS A
[1]
DIR
H
L
G
L
L
CPAB
X
CPBA
X
SAB
X
X
SBA
X
X
DIR
L
H
G
L
L
CPAB
X
H or L
CPBA
H or L
X
SAB
X
H
SBA
H
X
X
H
X
X
Storage from
A and/or B
Transfer Stored Data
to A and/or B
Function Table[2]
Inputs
Data I/O[3]
Operation or Function
FCT646T
G
DIR
CPAB
CPBA
SAB
SBA
A1 thru A8
B1 thru B8
H
H
X
X
H or L
H or L
X
X
X
X
Input
Output
Input
Input
Isolation
Store A and B Data
L
L
L
L
X
X
X
X
X
L
H
Input
Real Time B Data to A Bus
Stored B Data to A Bus
H or L
L
L
H
H
X
X
X
L
H
X
X
Output
Real Time A Data to B Bus
Stored A Data to B Bus
H or L
Notes:
1. Cannot transfer data to A bus and B bus simultaneously.
2. H = HIGH Voltage Level, L = LOW Voltage Level, = LOW-to-HIGH Transition, X = Don’t Care.
3. The data output functions may be enabled or disabled by various signals at the G or DIR inputs. Data input functions are always enabled, i.e., data at the bus
pins will be stored on every LOW-to-HIGH transition of the clock inputs.
2
CY54/74FCT646T
Maximum Ratings[4, 5]
Power Dissipation..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–65°C to +135°C
Ambient
Range
Commercial
Military[6]
Range
All
Temperature
–40°C to +85°C
–55°C to +125°C
VCC
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin).......120 mA
5V ± 5%
5V ± 10%
All
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VCC=Min., IOH=–32 mA Com’l
Min.
2.0
Typ.[7]
Max.
Unit
V
VOH
Output HIGH Voltage
VCC=Min., IOH=–15 mA
VCC=Min., IOH=–12 mA
VCC=Min., IOL=64 mA
VCC=Min., IOL=48 mA
Com’l
Mil
2.4
3.3
3.3
0.3
0.3
V
2.4
V
VOL
Output LOW Voltage
Com’l
Mil
0.55
0.55
V
V
VIH
VIL
VH
VIK
II
Input HIGH Voltage
Input LOW Voltage
Hysteresis[8]
2.0
V
0.8
V
All inputs
0.2
V
Input Clamp Diode Voltage
Input HIGH Current
Input HIGH Current[8]
Input LOW Current[8]
VCC=Min., IIN=–18 mA
VCC=Max., VIN=VCC
VCC=Max., VIN=2.7V
VCC=Max., VIN=0.5V
–0.7
–1.2
5
V
µA
µA
µA
mA
µA
IIH
±1
IIL
±1
IOS
IOFF
Output Short Circuit Current[9] VCC=Max., VOUT=0.0V
–60
–120
–225
±1
Power-Off Disable
VCC=0V, VOUT=4.5V
Capacitance[8]
Parameter
Description
Typ.[7]
Max.
10
Unit
CIN
Input Capacitance
Output Capacitance
6
8
pF
pF
COUT
12
Notes:
4. Unless otherwise noted, these limits are over the operating free-air temperature range.
5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
6. TA is the “instant on” case temperature.
7. Typical values are at VCC=5.0V, TA=+25˚C ambient.
8. This parameter is specified but not tested.
9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
3
CY54/74FCT646T
Power Supply Characteristics
Parameter
ICC
Description
Test Conditions
Typ.[7]
0.1
Max.
0.2
Unit
mA
mA
Quiescent Power Supply Current VCC=Max., VIN≤0.2V, VIN≥VCC–0.2V
Quiescent Power Supply Current VCC=Max., VIN=3.4V, f1=0, Outputs Open[10]
(TTL inputs HIGH)
∆ICC
0.5
2.0
ICCD
Dynamic Power Supply
Current[11]
VCC=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
G=DIR=GND, GAB=GBA=GND,
0.06
0.7
0.12
1.4
mA/MHz
VIN≤0.2V or VIN≥VCC–0.2V
IC
Total Power Supply Current[12]
VCC=Max., f0=10 MHz,
mA
50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=5 MHz,
G=DIR=GND, GAB=GBA=GND,
VIN≤0.2V or VIN≥VCC–0.2V
VCC=Max., f0=10 MHz,
1.2
2.8
5.1
3.4
mA
mA
mA
50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=5 MHz,
G=DIR=GND, GAB=GBA=GND,
VIN=3.4V or VIN=GND
VCC=Max., f0=10 MHz,
5.6[13]
50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=5 MHz,
G=DIR=GND, GAB=GBA=GND,
VIN≤0.2V or VIN≥VCC–0.2V
VCC=Max., f0=10 MHz,
14.6[13]
50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=5 MHz,
G=DIR=GND, GAB=GBA=GND,
VIN=3.4V or VIN=GND
Notes:
10. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
12. IC
IC
= IQUIESCENT + IINPUTS + IDYNAMIC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH
NT
= Duty Cycle for TTL inputs HIGH
= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0
f1
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
4
CY54/74FCT646T
Switching Characteristics Over the Operating Range[14]
FCT646T
Military Commercial
Min. Max. Min. Max.
FCT646AT
Commercial
Fig.
Parameter
Description
Min.
Max.
Unit No.[15]
tPLH
tPHL
Propagation Delay Bus to Bus
2.0
2.0
2.0
2.0
2.0
4.5
2.0
6.0
11.0
15.0
11.0
10.0
12.0
1.5
1.5
1.5
1.5
1.5
4.0
2.0
6.0
9.0
14.0
9.0
1.5
6.3
ns
ns
ns
ns
ns
ns
ns
ns
1, 3
1, 7, 8
1, 7, 8
1, 5
1, 5
4
tPZH
tPZL
Output Enable Time
Enable to Bus and DIR to An or Bn
1.5
1.5
1.5
1.5
2.0
1.5
5.0
9.8
6.3
6.3
7.7
tPHZ
tPLZ
Output Disable Time
G to Bus and DIR to Bus
tPLH
tPHL
Propagation Delay
Clock to Bus
9.0
tPLH
tPHL
Propagation Delay
SBA or SAB to A or B
11.0
tS
Set-Up Time HIGH or LOW,
Bus to Clock
tH
tW
Hold Time HIGH or LOW,
Bus to Clock
Pulse Width, HIGH or LOW [8]
4
5
FCT646CT
Military Commercial
Fig.
Parameter
Description
Min.
Max.
Min.
Max.
Unit
No.[15]
tPLH
tPHL
Propagation Delay Bus to Bus
1.5
6.0
1.5
5.4
ns
ns
ns
ns
ns
1, 3
1, 7, 8
1, 7, 8
1, 5
tPZH
tPZL
Output Enable Time Enable to Bus and DIR to An or Bn
Output Disable Time G to Bus and DIR toBus
Propagation Delay Clock to Bus
1.5
1.5
1.5
1.5
8.9
7.7
6.3
7.0
1.5
1.5
1.5
1.5
7.8
6.3
5.7
6.2
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
Propagation Delay SBA or SAB to A or B
1, 5
tS
tH
Set-Up Time, HIGH or LOW, Bus to Clock
Hold Time, HIGH or LOW, Bus to Clock
Pulse Width,[8] HIGH or LOW
2.0
1.5
5.0
2.0
1.5
5.0
ns
ns
ns
4
4
5
tW
Notes:
14. Minimum limits are specified but not tested on Propagation Delays.
15. See “Parameter Measurement Information” in the General Information Section.
5
CY54/74FCT646T
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
24-Lead (150-Mil) QSOP
5.4
CY74FCT646CTQCT
CY74FCT646CTSOC/SOCT
CY54FCT646CTLMB
CY74FCT646ATQCT
Q13
S13
L64
Q13
S13
Q13
S13
L64
Commercial
24-Lead (300-Mil) Molded SOIC
28-Square Leadless Chip Carrier
24-Lead (150-Mil) QSOP
6.0
6.3
Military
Commercial
CY74FCT646ATSOC/SOCT
CY74FCT646TQCT
24-Lead (300-Mil) Molded SOIC
24-Lead (150-Mil) QSOP
9.0
Commercial
Military
CY74FCT646TSOC/SOCT
CY54FCT646TLMB
24-Lead (300-Mil) Molded SOIC
28-Square Leadless Chip Carrier
11.0
Document #: 38–00267–C
Package Diagrams
28-Square Leadless Chip Carrier L64
MIL–STD–1835 C–4
6
CY54/74FCT646T
Package Diagrams (continued)
24-Lead Quarter Size Outline Q13
24-Lead (300-Mil) Molded SOIC S13
7
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Copyright 2000, Texas Instruments Incorporated
相关型号：
5962-9222303M3X
Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, CQCC24, CERAMIC, LCC-24
IDT
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