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5962-9223302MEA [TI]

8 选 1 解码器 | J | 16 | -55 to 125;
5962-9223302MEA
型号： 5962-9223302MEA
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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8 选 1 解码器 | J | 16 | -55 to 125

驱动 解码器 驱动器
文件： 总7页 (文件大小：110K)
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CY54FCT138T, CY74FCT138T  
1-OF-8 DECODERS  
SCCS013B – MAY 1994 – REVISED OCTOBER 2001  
CY54FCT138T . . . D PACKAGE  
CY74FCT138T . . . Q OR SO PACKAGE  
(TOP VIEW)  
Function, Pinout, and Drive Compatible  
With FCT and F Logic  
Reduced V  
Equivalent FCT Functions  
(Typically = 3.3 V) Versions of  
OH  
A
A
A
E
E
E
O
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
0
1
2
1
2
3
7
O
O
O
O
O
O
O
0
1
2
3
4
5
6
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Matched Rise and Fall Times  
GND  
Fully Compatible With TTL Input and  
Output Logic Levels  
CY54FCT138T . . . L PACKAGE  
(TOP VIEW)  
Dual 1-of-8 Decoder With Enables  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
3
2 1 20 19  
18  
O
O
A
E
4
5
6
7
8
1
2
2
1
– 1000-V Charged-Device Model (C101)  
17  
16  
15  
14  
CY54FCT138T  
– 32-mA Output Sink Current  
– 12-mA Output Source Current  
NC  
NC  
O
3
O
4
E
2
E
3
CY74FCT138T  
9 10 11 12 13  
– 64-mA Output Sink Current  
– 32-mA Output Source Current  
NC – No internal connection  
description  
The ’FCT138T devices are 1-of-8 decoders. These devices accept three binary weighted inputs (A , A , A )  
0
1
2
and, when enabled, provide eight mutually exclusive active-low outputs (O –O ). The ’FCT138T devices  
0
7
feature three enable inputs: two active low (E , E ) and one active high (E ).  
1
2
3
All outputs are high unless E and E are low and E is high. This multiple-enable function allows easy parallel  
1
2
3
expansion of the device to a 1-of-32 (five lines to 32 lines) decoder with just four ’FCT138T devices and one  
inverter.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the device when it is powered down.  
PIN DESCRIPTION  
NAME  
DESCRIPTION  
Address inputs  
A
E , E  
Enable inputs (active low)  
Enable input (active high)  
Outputs  
1
2
E
3
O
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
CY54FCT138T, CY74FCT138T  
1-OF-8 DECODERS  
SCCS013B – MAY 1994 – REVISED OCTOBER 2001  
ORDERING INFORMATION  
SPEED  
(ns)  
ORDERABLE  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PART NUMBER  
CY74FCT138CTQCT  
CY74FCT138CTSOC  
CY74FCT138CTSOCT  
CY74FCT138ATQCT  
CY74FCT138ATSOC  
CY74FCT138ATSOCT  
CY74FCT138TQCT  
CY54FCT138CTLMB  
CY54FCT138TLMB  
CY54FCT138TDMB  
QSOP – Q  
SOIC – SO  
QSOP – Q  
SOIC – SO  
Tape and reel  
Tube  
5
5
FT138-3  
FCT138C  
FT138-1  
FCT138A  
FT138  
Tape and reel  
Tape and reel  
Tube  
5
–40°C to 85°C  
5.8  
5.8  
5.8  
9
Tape and reel  
Tape and reel  
Tube  
QSOP – Q  
LCC – L  
6
–55°C to 125°C  
LCC – L  
Tube  
12  
12  
CDIP – D  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
E
1
E
2
E
3
A
A
A
O
O
O
O
O
O
O
O
7
0
1
2
0
1
2
3
4
5
6
H
X
X
X
X
X
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
L
X
X
L
X
X
L
X
X
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H = High logic level, L = Low logic level, X = Don’t care  
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
CY54FCT138T, CY74FCT138T  
1-OF-8 DECODERS  
SCCS013B – MAY 1994 – REVISED OCTOBER 2001  
logic diagram (positive logic)  
15  
O
O
O
O
O
0
1
2
3
4
1
A
A
0
1
14  
13  
12  
11  
10  
9
2
3
A
2
O
O
O
5
6
7
6
4
E
3
E
1
E
2
7
5
Pin numbers shown are for the D, Q, and SO packages.  
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA  
Package thermal impedance, θ (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W  
JA  
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W  
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C  
A
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C  
stg  
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.  
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
CY54FCT138T, CY74FCT138T  
1-OF-8 DECODERS  
SCCS013B – MAY 1994 – REVISED OCTOBER 2001  
recommended operating conditions (see Note 2)  
CY54FCT138T  
MIN NOM MAX  
CY74FCT138T  
MIN NOM MAX  
UNIT  
V
V
V
Supply voltage  
4.5  
2
5
5.5  
4.75  
2
5
5.25  
V
V
CC  
High-level input voltage  
Low-level input voltage  
High-level output current  
Low-level output current  
Operating free-air temperature  
IH  
0.8  
–12  
32  
0.8  
–32  
64  
V
IL  
I
I
mA  
mA  
°C  
OH  
OL  
T
A
–55  
125  
–40  
85  
NOTE 2: All unused inputs of the device must be held at V  
or GND to ensure proper device operation.  
CC  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
CY54FCT138T  
CY74FCT138T  
PARAMETER  
TEST CONDITIONS  
UNIT  
†
TYP  
†
TYP  
MIN  
MAX  
MIN  
MAX  
V
V
V
= 4.5 V,  
= 4.75 V,  
= 4.5 V,  
I
I
I
I
I
I
I
= –18 mA  
= –18 mA  
–0.7  
–1.2  
CC  
CC  
CC  
IN  
V
V
IK  
–0.7  
–1.2  
IN  
= –12 mA  
= –32 mA  
= –15 mA  
= 32 mA  
= 64 mA  
2.4  
3.3  
OH  
OH  
OH  
OL  
OL  
V
OH  
2
V
V
CC  
= 4.75 V  
2.4  
3.3  
V
V
= 4.5 V,  
0.3  
0.2  
0.55  
CC  
V
V
V
V
OL  
= 4.75 V,  
0.3  
0.2  
0.55  
CC  
All inputs  
hys  
V
V
V
V
V
V
V
V
V
V
V
= 5.5 V,  
= 5.25 V,  
= 5.5 V,  
= 5.25 V,  
= 5.5 V,  
= 5.25 V,  
= 5.5 V,  
= 5.25 V,  
= 0 V,  
V
V
V
V
V
V
V
V
V
V
V
= V  
= V  
5
±1  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
IN  
CC  
CC  
I
I
I
µA  
I
5
±1  
±1  
IN  
= 2.7 V  
= 2.7 V  
= 0.5 V  
= 0.5 V  
IN  
µA  
µA  
IH  
IL  
IN  
±1  
IN  
IN  
= 0 V  
–60  
–120  
–225  
OUT  
OUT  
OUT  
‡
mA  
µA  
I
I
I
OS  
= 0 V  
–60  
–120  
–225  
±1  
= 4.5 V  
±1  
off  
= 5.5 V,  
= 5.25 V,  
≤ 0.2 V,  
V
V
≥ V  
≥ V  
– 0.2 V  
– 0.2 V  
0.1  
0.5  
0.2  
IN  
IN  
IN  
CC  
mA  
CC  
≤ 0.2 V,  
0.1  
0.5  
0.2  
2
IN  
CC  
§
2
V
CC  
V
CC  
V
CC  
= 5.5 V, V = 3.4 V , f = 0, Outputs open  
IN  
1
∆I  
mA  
CC  
§
= 5.25 V, V = 3.4 V , f = 0, Outputs open  
IN  
1
= 5.5 V, Outputs open, One bit switching at 50% duty  
– 0.2 V  
0.06  
0.12  
cycle, V ≤ 0.2 V or V ≥ V  
IN IN CC  
mA/  
MHz  
I
CCD  
V
CC  
= 5.25 V, Outputs open, One bit switching at 50%  
0.06  
0.12  
duty cycle, V ≤ 0.2 V or V ≥ V  
– 0.2 V  
IN IN CC  
†
‡
Typical values are at V  
CC  
= 5 V, T = 25°C.  
A
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus  
and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,  
prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In  
any sequence of parameter tests, I  
tests should be performed last.  
OS  
§
Per TTL-driven input (V = 3.4 V); all other inputs at V  
or GND  
IN CC  
This parameter is derived for use in total power-supply calculations.  
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
CY54FCT138T, CY74FCT138T  
1-OF-8 DECODERS  
SCCS013B – MAY 1994 – REVISED OCTOBER 2001  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted) (continued)  
CY54FCT138T  
CY74FCT138T  
PARAMETER  
TEST CONDITIONS  
UNIT  
†
TYP  
†
TYP  
MIN  
MAX  
MIN  
MAX  
One output  
switching  
V
V
≤ 0.2 V or  
≥ V – 0.2 V  
CC  
V
= 5.5 V,  
IN  
IN  
CC  
Outputs open,  
Switch E , E , or  
0.7  
1
1.4  
at f = 10 MHz  
1
1
2
at 50% duty  
cycle  
E
3
V
IN  
= 3.4 V or GND  
2.4  
#
I
C
mA  
One output  
switching  
V
V
≤ 0.2 V or  
V
= 5.25 V,  
IN  
IN  
CC  
||  
||  
0.7  
1
1.4  
≥ V  
CC  
– 0.2 V  
Outputs open,  
Switch E , E , or  
at f = 10 MHz  
1
1
2
at 50% duty  
cycle  
E
3
V
IN  
= 3.4 V or GND  
2.4  
C
C
5
9
10  
12  
5
9
10  
12  
pF  
pF  
i
o
†
#
Typical values are at V  
CC  
= 5 V, T = 25°C.  
A
I
= I  
+ ∆I  
× D × N + I  
(f /2 + f × N )  
C
CC  
CC  
H
T
CCD 0 1 1  
Where:  
I
I
∆I  
D
N
= Total supply current  
= Power-supply current with CMOS input levels  
C
CC  
CC  
H
T
= Power-supply current for a TTL high input (V = 3.4 V)  
IN  
= Duty cycle for TTL inputs high  
= Number of TTL inputs at D  
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)  
= Clock frequency for registered devices, otherwise zero  
= Input signal frequency  
CCD  
0
1
N
= Number of inputs changing at f  
1
1
All currents are in milliamperes and all frequencies are in megahertz.  
||  
Values for these conditions are examples of the I  
CC  
formula.  
switching characteristics over operating free-air temperature range (see Figure 1)  
CY54FCT138T CY54FCT138CT  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
ns  
MIN  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MAX  
12  
MIN  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MAX  
6
t
t
t
t
t
t
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
A
O
O
O
12  
6
12.5  
12.5  
12.5  
12.5  
6.1  
6.1  
6.1  
6.1  
ns  
E
1
or E  
2
E
3
ns  
switching characteristics over operating free-air temperature range (see Figure 1)  
CY74FCT138T  
CY74FCT138AT  
CY74FCT138CT  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
ns  
MIN  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MAX  
MIN  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MAX  
5.8  
5.8  
5.9  
5.9  
5.9  
5.9  
MIN  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MAX  
t
t
t
t
t
t
9
9
9
9
9
9
5
5
5
5
5
5
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
A
O
O
O
ns  
E
1
or E  
2
E
3
ns  
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
CY54FCT138T, CY74FCT138T  
1-OF-8 DECODERS  
SCCS013B – MAY 1994 – REVISED OCTOBER 2001  
PARAMETER MEASUREMENT INFORMATION  
7 V  
Open  
GND  
S1  
500 Ω  
From Output  
Under Test  
From Output  
Under Test  
Test  
Point  
TEST  
S1  
t
/t  
Open  
7 V  
PLH PHL  
t /t  
C
= 50 pF  
C
= 50 pF  
L
L
500 Ω  
500 Ω  
PLZ PZL  
/t  
(see Note A)  
(see Note A)  
t
Open  
PHZ PZH  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
LOAD CIRCUIT FOR  
3-STATE OUTPUTS  
3 V  
0 V  
1.5 V  
Timing Input  
Data Input  
t
w
t
h
t
3 V  
su  
3 V  
0 V  
1.5 V  
Input  
1.5 V  
1.5 V  
1.5 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
3 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Input  
t
t
t
t
t
t
PLH  
PHL  
PLH  
PZL  
PZH  
PLZ  
≈3.5 V  
V
Output  
Waveform 1  
(see Note B)  
OH  
In-Phase  
Output  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
V
V
+ 0.3 V  
OL  
V
OL  
V
OL  
t
t
PHL  
PHZ  
V
V
V
OH  
OH  
Output  
Waveform 2  
(see Note B)  
Out-of-Phase  
Output  
– 0.3 V  
OH  
1.5 V  
1.5 V  
≈0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. The outputs are measured one at a time with one input transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess  
in which TI products or services are used. Information published by TI regarding third–party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Mailing Address:  
Texas Instruments  
Post Office Box 655303  
Dallas, Texas 75265  
Copyright 2001, Texas Instruments Incorporated  

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5962-9223303M2X

 3-To-8-Line Demultiplexer
ETC

5962-9223303MEX

 3-To-8-Line Demultiplexer
ETC

5962-9223304M2A

 Decoder/Driver, FCT Series, Inverted Output, CMOS, CQCC20, CERAMIC, LLCC-20
CYPRESS

5962-9223304M2X

 3-To-8-Line Demultiplexer
ETC

5962-9223304MEX

 3-To-8-Line Demultiplexer
ETC

5962-9223304MFX

 3-To-8-Line Demultiplexer
ETC

5962-9223305M2X

 3-To-8-Line Demultiplexer
ETC

5962-9223305MEX

 3-To-8-Line Demultiplexer
ETC

5962-9223306M2A

 8 选 1 解码器 | FK | 20 | -55 to 125
TI

5962-9223306M2A

 Decoder/Driver, FCT Series, Inverted Output, CMOS, CQCC20, CERAMIC, LLCC-20
CYPRESS
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