5962-9323901QXA [TI]
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP CONCATENATORS; 与4位的识别巴士扫描路径LINKERS扫描控IEEE标准1149.1 JTAG TAP CONCATENATORS
| 型号： | 5962-9323901QXA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP CONCATENATORS |
| 文件： | 总28页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
SN54ACT8997 . . . JT PACKAGE
SN74ACT8997 . . . DW OR NT PACKAGE
(TOP VIEW)
Members of the Texas Instruments
SCOPE Family of Testability Products
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Serial Test Bus
DCO
MCO
DCI
MCI
TRST
ID1
ID2
ID3
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Allow Partitioning of System Scan Paths
Can Be Cascaded Horizontally or Vertically
2
DTDO1
DTDO2
DTDO3
DTDO4
GND
DTMS1
DTMS2
DTMS3
DTMS4
DTCK
3
4
Select Up to Four Secondary Scan Paths to
Be Included in a Primary Scan Path
5
6
Include 8-Bit Programmable Binary Counter
to Count or Initiate Interrupt Signals
ID4
7
V
8
CC
Include 4-Bit Identification Bus for
Scan-Path Identification
DTDI1
DTDI2
DTDI3
DTDI4
TDI
9
10
11
12
13
14
Inputs Are TTL Compatible
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
TDO
TMS
TCK
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
SN54ACT8997 . . . FK PACKAGE
(TOP VIEW)
description
The ’ACT8997 are members of the Texas
Instruments SCOPE testability integrated-
circuit family. This family of components facilitates
testing of complex circuit-board assemblies.
4
3
2 1 28 27 26
5
6
7
8
9
25
24
23
22
21
20
19
TRST
MCI
DCI
DCO
MCO
DTDI3
DTDI4
TDI
TCK
TMS
The ’ACT8997 enhance the scan capability of TI’s
SCOPE family by allowing augmentation of a
system’s primary scan path with secondary scan
paths (SSPs), which can be individually selected
by the ’ACT8997 for inclusion in the primary scan
path. These devices also provide buffering of test
signals to reduce the need for external logic.
10
11
DTDO1
DTDO2
TDO
DTCK
12 13 14 15 16 17 18
By loading the proper values into the instruction
register and data registers, the user can select up
to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any
of the device’s six data registers or the instruction register can be placed in the device’s scan path, i.e., placed
between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.
All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit
programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and
output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on
either the rising or falling edge of DCI.
The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.
The SN54ACT8997 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ACT8997 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
functional block diagram
3
4
5
6
DTDO1
DTDO2
V
CC
CC
CC
CC
CC
16
TDI
DTDI1
DTDI2
Scan-Path
Configuration
V
DTDO3
DTDO4
20
V
19
V
18
DTDI3
DTDI4
V
17
2
1
MCO
DCO
(3 state or
open drain)
28
8
DCI
MCI
DTMS1
9
DTMS2
27
10
DTMS3
Data
Registers
11
DTMS4
22–25
ID(1–4)
13
TDO
Instruction
Register
V
CC
14
Test Port
TMS
15
12
TCK
DTCK
V
CC
26
TRST
Pin numbers shown are for the DW, JT, and NT packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
functional block description
The ’ACT8997 is intended to link secondary scan paths for inclusion in a primary scan path. Any combination
of the four secondary scan paths can be linked, or the device can be bypassed entirely.
The least-significant bit (LSB) of any value scanned into any register of the device is the first bit shifted in
(nearest to TDO). The most-significant bit (MSB) is the last bit shifted in (nearest to TDI).
The ’ACT8997 is divided into functional blocks as detailed below.
test port
The test port decodes the signals on TCK, TMS, and TRST to control the operation of the circuit. The test port
includes a TAP controller that issues the proper control instructions to the data registers according to the
IEEE Standard 1149.1 protocol. The TAP controller state diagram is shown in Figure 1.
instruction register
The instruction register (IR) is an 8-bit-wide serial-shift register that issues commands to the device. Data is
input to the instruction register via TDI (or one of the DTDI pins) and shifted out via TDO. All device operations
are initiated by loading the proper instruction or sequence of instructions into the IR.
data registers
Six parallel data registers are included in the ’ACT8997: bypass, control, counter, boundary-scan, ID-bus, and
select. The ID bus register is a part of the boundary-scan register. Each data register is serially loaded via TDI
or DTDI and outputs data via TDO. Table 1 summarizes the registers in the ’ACT8997.
scan-path-configuration circuit
This circuit decodes bits in the select and control registers to determine which, if any, of the secondary scan
paths are to be included in the primary scan path.
Table 1. Register Summary
REGISTER
NAME
LENGTH
(BITS)
FUNCTION
Instruction
Control
8
10
8
Issue command information to the device
Configuration and enable control
Counter
Select
Count events on DCI, output interrupts via DCO
Select one or more secondary scan paths
Capture and force test data at device periphery
Provide subsystem identification code
Remove the ’ACT8997 from the scan path
8
Boundary Scan
ID Bus
10
4
Bypass
1
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
Device condition input. DCI receives interrupt and protocol signals from the secondary scan path(s). When the
counter register is instructed to count up or down, DCI is configured as the counter clock.
DCI
I
Device condition output. DCO is configured by the control register to output protocol and interrupt signals and can
be configured by the control register to output an error signal if the instruction register is loaded with an invalid value.
DCO is further configured by the control register as:
DCO
O
Active high or active low (reset condition = active low)
Open drain or 3 state (reset condition = open drain)
DTCK
O
I
Device test clock. DTCK outputs the buffered test clock TCK to the secondary scan path(s).
DTDI1
DTDI2
DTDI3
DTDI4
Device test data input 1–4. DTDI1–DTDI4 receive the serial test data output(s) of the selected secondary scan
path(s). An internal pullup forces DTDI1–DTDI4 to a high logic level if it is left unconnected.
DTDO1
DTDO2
DTDO3
DTDO4
O
O
Device test data output 1–4. These outputs send serial test data to the TDI input(s) of the secondary scan path(s).
DTMS1
DTMS2
DTMS3
DTMS4
Device test mode select 1–4. Any combination of these four outputs can be selected to follow TMS to direct the
secondary scan path(s) through the TAP controller states in Figure 1. The unselected DTMS outputs can be set
independently to a high or low logic level. The TMS circuit monitors input from the select register to determine the
configuration of the DTMS outputs.
GND
Ground
IDI
ID2
ID3
ID4
Identification 1–4. This 4-bit data bus can be hardwired to provide identification of the subsystem under test. The
value present on the bus can be scanned out through the boundary scan or ID bus registers.
I
Master condition input. MCI receives interrupt and protocol signals from a primary bus controller (PBC). The level
on MCI is buffered and output on MCO.
MCI
I
MCO
O
Master condition output. MCO transmits interrupt and protocol signals to the secondary scan path(s).
Test clock. One of four terminals required by IEEE Standard 1149.1. All operations of the ’ACT8997 except for the
count function are synchronous to TCK. Data on the device inputs is captured on the rising edge of TCK, and outputs
change on the falling edge of TCK.
TCK
TDI
I
I
Testdatainput. OneoffourterminalsrequiredbyIEEEStandard1149.1. TDIistheserialinputforshiftinginformation
into the instruction register or selected data register. TDI is typically driven by the TDO of the PBC. An internal pullup
forces TDI to a high level if left unconnected.
Test data output. One of four terminals required by IEEE Standard 1149.1. TDO is the serial output for shifting
information out of the instruction register or selected data register. TDO is typically connected to the TDI of the next
scannable device in the primary scan path.
TDO
TMS
TRST
O
I
Test mode select. One of four terminals required by IEEE Standard 1149.1. The level of TMS at the rising edge of
TCK directs the ’ACT8997 through its TAP controller states. An internal pullup forces TMS to a high level if left
unconnected.
Test reset. This active-low input implements the optional reset terminal of IEEE Standard 1149.1. When asserted,
TRST causes the ’ACT8997 to go to the Test-Logic-Reset state and configure the instruction register and data
registers to their power-up values. An internal pullup forces TRST to a high level if left unconnected.
I
V
CC
Supply voltage
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
state diagram description
The TAP proceeds through the states in Figure 1 according to IEEE Standard 1149.1. There are six stable states
(indicated by a looping arrow) and ten unstable states in the diagram. A stable state is a state the TAP can retain
for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to manipulate a data register and one to manipulate
the instruction register. No more than one register can be manipulated at a time.
Test-Logic-Reset
TMS = H
TMS = H
TMS = L
TMS = H
TMS = H
Select-DR-Scan
TMS = L
Select-IR-Scan
Run-Test/Idle
TMS = L
TMS = L
TMS = H TMS = H
Capture-DR
TMS = L
Capture-IR
TMS = L
Shift-DR
TMS = H
Shift-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
Exit1-DR
TMS = L
Exit1-IR
TMS = L
Pause-DR
TMS = H
Pause-IR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = L
Exit2-DR
Exit2-IR
TMS = H
TMS = H
Update-DR
Update-IR
TMS = L
TMS = L
TMS = H
TMS = H
Figure 1. TAP-Controller State Diagram
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
Test-Logic-Reset
In this state, the test logic is inactive and an internal reset signal is applied to all registers in the device. During
device operation, the TAP returns to this state in no more than five TCK cycles if the test mode select (TMS)
input is high. The TMS pin has an internal pullup that forces it to a high level if it is left unconnected or if a board
defect causes it to be open circuited. The device powers up in the Test-Logic-Reset state.
Run-Test/Idle
The TAP must pass through this state before executing any test operations. The TAP may retain this state
indefinitely, and no registers are modified while in Run-Test/Idle. The 8-bit programmable up/down counter can
be operated in this state.
Select-DR-Scan, Select-IR-Scan
No specific function is performed in these states; the TAP exits either of them on the next TCK cycle.
Capture-DR
The selected data register is placed in the scan path (i.e., between TDI and TDO). Depending on the current
instruction, data may or may not be loaded or captured by that register on the rising edge of TCK, causing the
TAP state to change.
Shift-DR
In this state, data is serially shifted through the selected data register from TDI to TDO on each TCK cycle. The
first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK
cycle in which the TAP changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). On the falling edge
of TCK in Shift-DR, TDO goes from the high-impedance state to the active state. TDO enables to the value
present in the least-significant bit of the selected data register.
Exit1-DR, Exit2-DR
These are temporary states that end the shifting process. It is possible to return to the Shift-DR state from either
Exit1-DR or Exit2-DR without recapturing the data register. The last shift occurs on the TCK cycle in which the
TAP state changes from Shift-DR to Exit-DR. TDO changes from the active state to the high-impedance state
on the falling edge of TCK in Exit1-DR.
Pause-DR
The TAP can remain in this state indefinitely. The Pause-DR state suspends and resumes shift operations
without loss of data.
Update-DR
If the current instruction calls for the latches in the selected data register to be updated with current data, the
latches are updated only during this state.
Capture-IR
The instruction register is preloaded with the IR status word (see Table 4) and placed in the scan path.
Shift-IR
In this state, data is serially shifted through the instruction register from TDI to TDO on each TCK cycle. The
first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK
cycle in which the TAP changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). On the falling edge of
TCK in Shift-IR, TDO goes from the high-impedance state to the active state, and will enable to a high level.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
Exit1-IR, Exit2-IR
These are temporary states that end the shifting process. It is possible to return to the Shift-IR state from either
Exit1-IR or Exit2-IR without recapturing the instruction register. The last shift occurs on the TCK cycle in which
the TAP state changes from Shift-IR to Exit1-IR. TDO changes from the active state to the high-impedance state
on the falling edge of TCK in Exit1-IR.
Pause-IR
TheTAPcanremaininthisstateindefinitely. ThePause-IRstatesuspendsandresumesshiftoperationswithout
loss of data.
Update-IR
In this state, the latches shadowing the instruction register are updated with the new instruction.
instruction-register description
The instruction register (IR) is an 8-bit serial register that outputs control signals to the device. Table 2 lists the
instructions implemented in the ’ACT8997 and the data register selected by each instruction. The MSB of the
IR is an even-parity bit. If the value scanned into the IR during Shift-IR does not contain even parity, an error
signal (IRERR) is generated internally as shown in Table 3. The ’ACT8997 can be configured to output IRERR
via DCO if the TAP enters the Pause-IR state.
During the Capture-IR state, the IR status word is loaded.The IR status word contains information about the
most recently loaded value of the instruction register and the logic level present at the DCI input. The IR status
word is encoded as shown in Table 4. Figure 2 shows the order of scan for the IR.
Bit 7
(MSB)
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TDI or DTDI
TDO
Figure 2. Instruction-Register Bits and Order of Scan
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
Table 2. Instruction-Register Opcodes
BINARY CODE
BIT 7 → BIT 0
MSB → LSB
HEX
VALUE
SELECTED DATA
SCOPE OPCODE
DESCRIPTION
MODE
REGISTER
00000000
10000001
10000010
00000011
10000100
00000101
00000110
10000111
10001000
00001001
00001010
10001011
00001100
10001101
10001110
00001111
11111010
01111011
11111100
01111101
01111110
All others
00
81
82
03
84
05
06
87
88
09
0A
8B
0C
8D
8E
0F
FA
7B
FC
7D
7E
EXTEST
Boundary scan
Bypass scan
Boundary scan
Bypass
Test
†
BYPASS
Normal
Normal
Test
SAMPLE/PRELOAD
INTEST
Sample boundary
Boundary scan
Bypass scan
Boundary scan
Boundary scan
Bypass
†
†
†
†
BYPASS
BYPASS
BYPASS
BYPASS
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Bypass scan
Bypass
Bypass scan
Bypass
Bypass scan
Bypass
COUNT
COUNT
Count
Bypass
Count
Bypass
†
BYPASS
BYPASS
BYPASS
Bypass scan
Bypass
†
†
Bypass scan
Bypass
Bypass scan
Bypass
BYPASS
SCANCN
SCANCN
SCANCNT
READCNT
SCANIDB
READIDB
SCANSEL
BYPASS
Bypass scan
Bypass
Control register scan
Control register scan
Counter scan
Counter read
Control
Control
Counter
Counter
ID bus
ID bus register scan
ID bus register read
Select register scan
Bypass scan
ID bus
Select
Bypass
†
A SCOPE opcode exists but is not supported by the ’ACT8997.
Table 3. IRERR Function Table
NO. OF INSTRUCTION
REGISTER BITS = 1
IRERR
0, 2, 4, 6, 8
1, 3, 5, 7
1
0
Table 4. Instruction-Register Status Word
†
VALUE
IR BIT
7
6
5
4
3
2
1
0
IRERR (see Table 3)
0
0
0
DCI (1 = active, 0 = inactive)
0
0
1
†
This value is loaded in the instruction
register during the Capture-IR TAP state.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
instruction-register opcode description
The operation of the ’ACT8997 is dependent on the instruction loaded into the IR. Each instruction selects one
of the data registers to be placed between TDI or DTDI and TDO during the Shift-DR TAP state. All the required
instructions of IEEE Standard 1149.1 are implemented in the ’ACT8997.
boundary scan
This instruction implements the required EXTEST and optional INTEST operations of IEEE Standard 1149.1.
The boundary-scan register (which includes the ID-bus register) is placed in the scan path. Data appearing at
input pins included in the boundary-scan register is captured. Data previously loaded into the output pins
included in the boundary-scan register is forced through the outputs.
bypass scan
This instruction implements the required BYPASS operation of IEEE Standard 1149.1. The bypass register is
placed in the scan path and preloads with a logic 0 during Capture-DR.
sample boundary
This instruction implements the required SAMPLE/PRELOAD operation of IEEE Standard 1149.1. The
boundary-scan register is placed in the scan path, and data appearing at the inputs and outputs included in the
boundary-scan register is sampled on the rising edge of TCK in Capture-DR.
count
The counter register begins counting on each DCI transition. The count begins from the value present in the
register before the count instruction was loaded. The counter can be configured by the control register to count
up or down on either the low-to-high or high-to-low transition of DCI. Counting occurs only while in the
Run-Test/Idle TAP state.
control-register scan
The control register is placed in the scan path for a subsequent shift operation. The register is not preloaded
during Capture-DR.
counter-register scan
The counter register is placed in the scan path. During Capture-DR, the current value of the counter is loaded
in the counter register. At Update-DR, the newly shifted value is preloaded to the counter.
counter-register read
The counter register is placed in the scan path. During Capture-DR, the prior preload value of the counter is
loaded into the counter register. At Update-DR, the newly shifted value is preloaded to the counter.
ID-bus-register scan
The ID-bus register (a subset of the boundary-scan register) is placed in the scan path for a subsequent shift
operation. The data appearing on the ID bus is loaded into the ID-bus register on the rising edge of TCK in
Capture-DR.
ID-bus-register read
The ID-bus register is placed in the scan path for a subsequent shift operation. The register is not preloaded
during Capture-DR.
select-register scan
The select register is placed in the scan path for a subsequent shift operation. The register is not preloaded
during Capture-DR.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
control register description
The control register (CTLR) is a 10-bit serial register that controls the enable and select functions of the
’ACT8997. A reset operation forces all bits to a low logic level. The contents of the CTLR are latched and
decoded during the Update-DR TAP state. The specific function of each bit is listed in Table 5. The enable and
select functions of the CTLR bits are mapped as follows:
Table 5. Control-Register Bit Mapping
BIT
VALUE
FUNCTION
0
1
Configure counter to count up
Configure counter to count down
9
0
Do not stop counting when the count reaches 00000000
Stop counting when the count reaches 00000000 (count down only)
Configure DCO as an active-low output
8
7
1
0
1
Configure DCO as an active-high output
00
01
10
11
0
DCO = Inactive (level depends on CTLR bit 7)
DCO = IRERR
6, 5
DCO = CE, an internal logic 0 generated when the count is 00000000 (count down) or 11111111 (count up)
DCO = DCI
Do not mask IRERR from DCO
Mask IRERR from DCO
4
3
2
1
0
1
0
Configure DCO as an open-drain output
Configure DCO as a 3-state output
Disable DCO
1
0
1
Enable DCO
0
Configure DCI as an active-low input
1
Configure DCI as an active-high input
0
Enable DTCK, DTDO(1–4), and DTMS(1–4) [outputs DTDO(1–4) depend on select register (see Table 7)]
Disable DTCK, DTDO(1–4), and DTMS(1–4)
1
Bit 9–Up/Down
This bit sets the count mode of the counter register (reset condition = count up).
Bit 8 – Latch on Zero
The counter register can be configured to stop counting when its value is 00000000 and ignore subsequent
transitions on the counter clock, DCI. The latch-on-zero option is valid only in the count-down mode
(reset condition = do not latch on zero). The value of this bit has no effect on the operation of the counter if
CTLR bit 9 = 0.
Bit 7 – DCO Polarity Select
DCO can be configured as an active-low or active-high output (reset condition = active low).
Bit 6/Bit 5 – DCO Source Select 1/DCO Source Select 0
DCO can be used to output the IRERR signal generated by the ’ACT8997 (see Table 3). Bits 6 and 5 can be
set to output IRERR via DCO on the falling edge of TCK in the Pause-IR state. DCO can also be configured
to become active when the value of the counter is 00000000, to follow DCI, or be set to a static high or low level
(reset condition = static high level).
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
Bit 4 – Parity Mask
The signal IRERR can be masked from appearing on DCO even if bits 6 and 5 are set such that it is output in
the Pause-IR state (reset condition = do not mask IRERR).
Bit – DCO Drive Select
DCO can be configured as either an open-drain or 3-state output (reset condition = open drain). The open-drain
configuration allows multiple DCO outputs to be used in a wired-OR or wired-AND application. The 3-state
configuration allows the DCO output to be connected to a bus.
Bit 2 – DCO Enable
When configured as
a
3-state output, DCO can be placed in the high-impedance state
(reset condition = disabled). If configured as an open-drain output and disabled, DCO outputs a high level.
Bit 1 – DCI Polarity Select
DCI can be configured as an active-low or active-high input (reset condition = active low).
Bit 0 – Device Test Pins Output Enable (active low)
DTCK, DTDO1–4, and DTMS1–4 pins can be placed in the high-impedance state (disabled) with this bit
(reset condition = not disabled). If DTDO1–4 pins are not disabled using this control bit, then their drive state
is dependent on the value of the select register (see Table 7).
SeveralCTLRbitsaffectthefunctionalityoftheDCOoutput. TheDCOfunctiontableisgiveninTable 6. Figure 3
illustrates the order of scan for the CTLR.
Bit 9
(MSB)
Bit 0
(LSB)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TDI or DTDI
TDO
Figure 3. Control-Register Bits and Order of Scan
11
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SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
Table 6. DCO Function Table
INTERNAL
SIGNALS
‡
CONTROL-REGISTER BITS
†
DCI
DCO
CE
X
X
X
X
X
X
X
X
X
X
0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
IRERR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
0
X
X
0
1
0
1
0
0
1
1
0
1
0
1
1
1
0
0
1
1
0
0
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
H
Z
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
1
§
0
L in Pause-IR , H otherwise
1
0
H
§
0
0
H in Pause-IR , L otherwise
1
0
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
H
H
L
1
1
X
X
X
X
X
X
X
X
H
L
L
1
L
0
L
L
1
H
L
H
H
H
H
0
1
H
H
L
0
1
†
‡
§
These signals are generated as described elsewhere in this data sheet.
The control register must contain these values after the TAP has passed through its most recent Update-DR state.
DCO becomes active on the falling edge of TCK as the TAP enters the Pause-IR state and becomes inactive on the
falling edge of TCK as the TAP enters Exit2-IR.
12
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select register description
The select register (SR) is an 8-bit serial register that determines which, if any, of the secondary scan paths
(SSPs) will be included in the primary scan path. A reset operation forces all bits to a logic 0. The register is
divided into four 2-bit sections, each of which controls one SSP. Figure 4 shows the mapping of the bits to the
SSPs and the order of scan. For each SSP, the higher-order bit is the MSB and the lower-order bit is the LSB
(e.g., bit 3 is the MSB of SSP2 and bit 2 is the LSB of SSP2).
Bit 7
(MSB)
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TDI or DTDI
TDO
SSP4
SSP3
SSP2
SSP1
Figure 4. Select Register Bits and Order of Scan
When a new 8-bit value is loaded into the SR, the configuration of one or more DTMS pins may change. If the
new value of the SR configures a DTMS pin to a static (high or low) level, it assumes that level on the falling
edge of TCK in the Update-DR TAP state. This condition is independent of any previous SR configurations. If
the new value of the SR forces a DTMS pin to follow TMS (i.e., select the secondary scan path) and one or more
DTMS pins are currently in the TMS-follow mode, the transfer of DTMS lines occurs on the falling edge of TCK
in the Update-DR TAP state. If, however, the new configuration forces a DTMS pin to follow TMS while no other
DTMS pin is selected, the DTMS pin is forced low and does not begin following TMS until the falling edge of
TCK in the Run-Test/Idle TAP state; therefore, when an SSP is initially selected, the TAP state should travel from
Update-DR to Run-Test/Idle, not from Update-DR to Select-DR-Scan.
Although any combination of SSPs can be selected, the order of scan for each combination is fixed (see data
flow description for details). The SR bit decoding is shown in Table 7.
Table 7. Select Register-Bit Decoding
DTMS
SOURCE
DTDO
STATUS
MSB
LSB
0
0
1
0
1
H
L
Z
Z
†
Active
X
TMS
†
The DTDO1–4 outputs are active only in
the Shift-IR and Shift-DR TAP states.
13
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boundary-scan register/ID-bus register description
The boundary-scan register (BSR) is a 10-bit serial register that can be used to capture data appearing at
selected device inputs, force data through device outputs, and apply data to the device’s internal logic. The BSR
is made up of boundary-scan cells (BSCs). Table 8 lists the device signal for each of the 10 BSCs that comprise
the BSR. A reset operation does not affect the contents of the BSR.
Table 8. Boundary-Scan Register Bit Mapping
TERMINAL
NAME
BIT
SIGNAL DESCRIPTION
9
8
7
6
5
4
3
2
1
0
MCI
Master condition in
Master condition out
Device condition in
MCO
DCI
†
DCOTS
DCOOD
DCO
ID4
Enable control for DCO in 3-state configuration (active low)
Enable control for DCO in open-drain configuration (active low)
Device condition out
†
Identification bus bit 4
ID3
Identification bus bit 3
ID2
Identification bus bit 2
ID1
Identification bus bit 1
†
This internal signal cannot be observed from the I/O terminals of the device.
The four BSCs connected to the ID(1–4) terminals form a subset of the BSR called the ID-bus register (IDBR).
The IDBR can be scanned without accessing the remaining BSCs of the BSR. Figure 5 shows the order of scan
for the BSR and IDBR.
Bit 9
(MSB)
Bit 0
(LSB)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TDI or DTDI
TDI or DTDI
TDO
IDBR
BSR
Figure 5. Boundary-Scan Register Bits and Order of Scan
bypass register description
The bypass register (BR) is a 1-bit serial register. The BR provides a means of effectively removing the
’ACT8997 from the primary scan path when it is not needed for the current test operation. Any selected
secondary scan paths remain active in the primary scan path as described in the data flow description. At power
up, the BR is placed in the scan path. During Capture-DR, the BR is preloaded with a low logic level. Figure 6
shows the order of scan for the bypass register.
TDI or DTDI
Bit 0
TDO
Figure 6. Bypass-Register Bit and Order of Scan
14
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counter register description
The counter register (CNTR) is an 8-bit serial register and an associated 8-bit parallel-load up/down counter.
A reset operation forces all bits of the shift register to a logic 0 but does not affect the counter. The counter can
be preloaded with an initial value before counting begins, and the current value of the counter scanned out via
the shift register. The CNTR can be used to count events occurring on the secondary scan path(s) using the
DCI pin as a counter clock and can output interrupt signals via DCO when the count has reached its end value.
An internal signal, CE, is generated as a logic 0 when the count reaches its end value (i.e., 00000000 for count
down, 11111111 for count up). For any other count value, CE is a logic 1. Many of the features of the CNTR are
configured by a bit in the CTLR including:
Count direction up or down (control register bit 9; reset condition = count up).
Stopcountinguponcountingdownto00000000(controlregisterbit8;resetcondition=donotlatchonzero).
Output CE signals at DCO (control register bits 5 and 6; reset condition = do not output CE at DCO).
Edge of DCI on which to trigger (control register bit 1; reset condition = positive edge).
Figure 7 shows the order of scan for the CNTR.
Bit 7
(MSB)
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TDI or DTDI
TDO
Figure 7. Counter-Register Bits and Order of Scan
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data flow description
The direction of serial-data flow in the ’ACT8997 is dependent on the current instruction and value of the SR.
Figure 8 shows the data flow when one or more SSPs have been selected. When more than one SSP has been
selected, theorderofscanisdeterminedbywhichSSPshavebeenselectedasshowninTable9. The’ACT8997
add one bit of delay from TDI or DTDI to DTDO.
’ACT8997
IR or
Selected DR
TDI
TDO
NO SECONDARY SCAN PATH SELECTED
Selected Scan Path
’ACT8997
’ACT8997
IR or
Selected DR
TDI
(1-bit delay) DTDOn
TDI
SSPn
TDO
DTDIn
TDO
ONE SECONDARY SCAN PATH SELECTED
Selected Scan Path
’ACT8997
TDI
(1-bit delay) DTDOx
TDI
TDI
TDI
SSPx
TDO
TDO
TDO
Selected Scan Path
SSPn
’ACT8997
DTDIx (1-bit delay) DTDOn
Selected Scan Path
SSPm
’ACT8997
’ACT8997
IR or
Selected DR
DTDIn (1-bit delay) DTDOm
DTDIm
TDO
MULTIPLE SECONDARY SCAN PATHS SELECTED
Figure 8. Data Flow in the ’ACT8997
16
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Table 9. Scan-Path Configurations
SR BIT
SSP CONFIGURATION
†‡
SCAN-PATH CONFIGURATION
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
5
3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SSP4
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Active
SSP3
Inactive
Inactive
Inactive
Inactive
Active
SSP2
Inactive
Inactive
Active
SSP1
Inactive
Active
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TDI–SPL–TDO
TDI–(1)–SSP1–SPL–TDO
Inactive
Active
TDI–(1)–SSP2–SPL–TDO
Active
TDI–(1)–SSP1–(1)–SSP2–SPL–TDO
TDI–(1)–SSP3–SPL–TDO
Inactive
Inactive
Active
Inactive
Active
Active
TDI–(1)–SSP1–(1)–SSP3–SPL–TDO
TDI–(1)–SSP2–(1)–SSP3–SPL–TDO
Active
Inactive
Active
Active
Active
TDI–(1)–SSP1–(1)–SSP2–(1)–SSP3–SPL–TDO
TDI–(1)–SSP4–SPL–TDO
Inactive
Inactive
Inactive
Inactive
Active
Inactive
Inactive
Active
Inactive
Active
Active
TDI–(1)–SSP1–(1)–SSP4–SPL–TDO
Active
Inactive
Active
TDI–(1)–SSP2–(1)–SSP4–SPL–TDO
Active
Active
TDI–(1)–SSP1–(1)–SSP2–(1)–SSP4–SPL–TDO
TDI–(1)–SSP3–(1)–SSP4–SPL–TDO
Active
Inactive
Inactive
Active
Inactive
Active
Active
Active
TDI–(1)–SSP1–(1)–SSP3–(1)–SSP4–SPL–TDO
TDI–(1)–SSP2–(1)–SSP3–(1)–SSP4–SPL–TDO
TDI–(1)–SSP1–(1)–SSP2–(1)–SSP3–(1)–SSP4–SPL–TDO
Active
Active
Inactive
Active
Active
Active
Active
†
‡
The scan-path configuration is the order of scan, beginning with the TDI of the ’ACT8997 and ending with the TDO of the ’ACT8997.
A (1) indicates one bit of delay through the ’ACT8997. SPL indicates the selected scan register within the ’ACT8997.
§
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
I I CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.7 W
O
O
CC
A
NT package . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
§
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the NT package, which has trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
17
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recommended operating conditions
SN54ACT8997 SN74ACT8997
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
V
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0
0
V
V
0
0
V
V
CC
CC
Output voltage
O
CC
–7
CC
TDO, DTDO(1–4), MCO
DTMS(1–4), DCO (3 state), DTCK
TDO, DTDO(1–4), MCO
DCO (open drain or 3 state)
DTMS(1–4)
–10
–16
10
I
High-level output current
mA
OH
OL
–11
7
11
16
I
Low-level output current
mA
16
32
125
24
DTCK
48
T
Operating free-air temperature
–55
0
70
°C
A
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ACT8997
SN74ACT8997
PARAMETER
TEST CONDITIONS
UNIT
†
MIN
MAX
MIN TYP
MAX
I
I
I
I
I
I
I
I
I
I
I
I
= –7 mA
= –10 mA
= –11 mA
= –16 mA
= 7 mA
3.6
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
OL
TDO, DTDO(1–4), MCO
V
V
V
V
V
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
CC
CC
CC
CC
CC
3.7
3.7
V
V
OH
3.6
DTMS(1–4), DCO (3 state),
DTCK
0.5
0.5
0.5
0.5
TDO, DTDO(1–4), MCO
DCO (open drain or 3 state)
DTMS(1–4)
= 10 mA
= 11 mA
= 16 mA
= 16 mA
= 24 mA
= 32 mA
= 48 mA
0.5
0.5
0.5
V
OL
V
DTCK
V
CC
CC
0.5
DTDO(1–4), DTMS(1–4),
DCO, DTCK
‡
I
OZ
V
= 5.5 V,
= 5.5 V,
V
= V
or GND
±10
±5
µA
µA
O
CC
CC
I
I
I
DCO (open drain)
V
V
V
= V
20
±1
10
±1
OH
CC
O
MCI, DCI, TCK, ID(1–4)
= 5.5 V, V = V
or GND
CC
CC
I
V = V
±1
±1
µA
I
TDI, DTDI(1–4),
TMS, TRST
I
CC
V
CC
= 5.5 V
V = GND
–0.1
–20
100
–0.1
–20
100
I
V
V
= 5.5 V, V = V
or GND, I = 0
µA
CC
CC
I
CC
O
= 5.5 V, One input at V = 3.4 V,
CC
I
§
1
1
mA
∆I
CC
Other inputs at V
or GND
CC
V = V or GND
CC
C
C
C
6
pF
pF
pF
i
I
DCO
V
= V
or GND
or GND
15
10
o
o
O
O
CC
CC
All other outputs
V
= V
†
‡
Typical values are at V
CC
For I/O pins, the parameter I
current.
= 5 V.
includes the input-leakage current. For the DCO pin, the parameter I
includes the open-drain output-leakage
OZ
OZ
§
This is the increase in supply current for each input being driven at TTL levels rather than V
or GND.
CC
19
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timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SN54ACT8997 SN74ACT8997
UNIT
MIN
MAX
MIN
MAX
TCK
0
20
0
20
f
t
Clock frequency
Pulse duration
MHz
ns
clock
DCI (count mode)
TCK high or low
DCI high or low (count mode)
TRST low
0
20
0
20
12
7
12
7
w
7
7
TMS before TCK↑
TDI before TCK↑
Any DTDI before TCK↑
MCI before TCK↑
DCI before TCK↑
Any ID before TCK↑
TMS after TCK↑
TDI after TCK↑
8
8
9
9
7
7
t
su
Setup time
ns
3
3
3
2
2
2
2
2
2
2
Any DTDI after TCK↑
MCI after TCK↑
2
2
t
t
Hold time
ns
ns
h
4
4
DCI after TCK↑
4
4
Any ID after TCK↑
Power up to TCK↑
4
4
Delay time
100*
100
d
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
20
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switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 9)
SN54ACT8997 SN74ACT8997
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
20
20
2
MAX
MIN
20
20
3
MAX
TCK
f
max
DCI (count mode)
t
t
t
t
t
t
t
t
14
16
28
26
27
26
31
31
33
32
34
31
21
23
23
22
30
29
29
26
17
16
19
20
23
28
23
24
30
31
31
33
31
35
37
35
12
14
25
24
25
24
29
29
31
30
32
29
19
21
20
20
27
26
25
23
15
14
17
18
21
26
21
22
27
28
28
30
29
33
35
32
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
TCK
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
TMS
DTCK
TDO
2
3
7
9
ns
7
9
7
9
Any DTDO
Any DTMS
ns
7
9
9
11
12
12
12
12
12
6
ns
9
DCO (open drain)
DCO (3 state)
9
t
PLH
PHL
9
ns
DCO (open drain)
DCO (3 state)
9
t
9
t
t
t
t
4
PLH
PHL
PLH
PHL
Any DTMS
MCO
ns
ns
5
7
5
7
MCI
5
7
DCO (open drain)
DCO (3 state)
9
11
10
10
9
t
DCI
PLH
PHL
6
ns
DCO (open drain)
DCO (3 state)
7
t
DCI
6
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3
5
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PZH
PZL
PZH
PZL
PZH
PZL
PZH
PZL
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
TDO
Any DTDO
Any DTMS
DCO
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
5
5
7
6
7
6
9
6
9
6
9
8
10
10
11
11
11
13
14
13
TDO
8
9
Any DTDO
Any DTMS
DCO
9
8
10
9
8
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
APPLICATION INFORMATION
Subsystem
TDI
TDI
TDI
TDI
TDO
TCK
TMS
SSP4
SSP3
SSP2
SSP1
TDO
TCK
TMS
TDO
TCK
TMS
TDO
TCK
TMS
4
4
4
DCI
MCO
’ACT8997
V
CC
V
CC
V
CC
V
CC
or GND
or GND
or GND
or GND
ID1
ID2
ID3
ID4
TDO
INT1
RSTOUT
To Remainder
of Primary
Scan Path
PBC
TMSOUT
TCKOUT
INT2
TDI
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
0 V
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
For testing pulse duration: t = 1 to 3 ns, t = 1 to 3 ns. Pulse polarity may be either high-to-low-to-high or a low-to-high-to-low.
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 9. Load Circuit and Voltage Waveforms
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
SOIC
Drawing
5962-9323901Q3A
5962-9323901QXA
SN74ACT8997DW
ACTIVE
ACTIVE
ACTIVE
FK
28
28
28
1
1
TBD
TBD
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
JT
DW
20
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
SN74ACT8997DWR
ACTIVE
SOIC
DW
28
1000
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
SN74ACT8997NT
SNJ54ACT8997FK
SNJ54ACT8997JT
OBSOLETE
ACTIVE
PDIP
LCCC
CDIP
NT
FK
JT
28
28
28
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
1
1
Level-NC-NC-NC
Level-NC-NC-NC
ACTIVE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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