5962-9557801NXD [TI]
具有三态输出的 36 位寄存总线收发器 | PZ | 100 | -40 to 85;
| 型号： | 5962-9557801NXD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的 36 位寄存总线收发器 | PZ | 100 | -40 to 85 驱动 总线驱动器 总线收发器 |
| 文件： | 总9页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
Members of the Texas Instruments
Widebus+ Family
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
< 0.8 V at V
(Output Ground Bounce)
Package Options Include 100-Pin Plastic
Thin Quad Flat (PZ) Package With
OLP
= 5 V, T = 25°C
CC
A
14 × 14-mm Body Using 0.5-mm Lead Pitch
High-Impedance State During Power Up
and Power Down
and Space-Saving 100-Pin Ceramic Quad
†
Flat (HS) Package
Released as DSCC SMD 5962-9557801NXD
’ABTH32543 . . . PZ PACKAGE
(TOP VIEW)
1009998 9796 959493 92 9190 89 8887 86 8584 83 8281 8079 7877 76
1A9
1A10
GND
1A11
1A12
1A13
1A14
GND
1A15
1A16
1A17
1A18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75 1B9
74 1B10
73 GND
72 1B11
71 1B12
70 1B13
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1B14
GND
1B15
1B16
1B17
1B18
V
V
CC
CC
2A1
2A2
2A3
2A4
GND
2A5
2A6
2A7
2A8
GND
2A9
2A10
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
2B8
GND
2B9
2B10
26 272829 3031 32 33 343536 3738 3940 4142 43 4445 46 474849 50
†
The HS package is not production released.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
†
SN54ABTH32543 . . . HS PACKAGE
(TOP VIEW)
1A6
1A7
1A8
1B7
1B8
1B9
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1A9
1B10
GND
1B11
1B12
1B13
1B14
GND
1B15
1B16
1B17
1B18
1A10
GND
1A11
1A12
1A13
1A14
GND
1A15
1A16
1A17
1A18
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
CC
V
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
2B8
GND
2B9
2B10
2B11
2B12
2B13
CC
2A1
2A2
2A3
2A4
GND
2A5
2A6
2A7
2A8
GND
2A9
2A10
2A11
2A12
†
For HS package availability, please contact the factory or your local TI Field Sales Office.
description
The’ABTH32543are36-bitregisteredtransceiversthatcontaintwosetsofD-typelatchesfortemporarystorage
of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit
transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided
for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
inthestoragemode. WithCEABandOEABbothlow, the3-stateBoutputsareactiveandreflectthedatapresent
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and
OEBA inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
description (continued)
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH32543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32543 is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
(each 18-bit section)
INPUTS
OUTPUT
B
CEAB
LEAB
OEAB
A
X
X
X
L
H
X
L
L
L
X
X
H
L
X
H
L
Z
Z
‡
B
0
L
L
L
L
H
H
†
‡
A-to-Bdataflowisshown;B-to-Aflowcontrolisthe
sameexcept that it uses CEBA, LEBA, and OEBA.
Output level before the indicated steady-state
input conditions were established
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
logic diagram (positive logic)
90
1OEBA
91
1CEBA
89
1LEBA
86
1OEAB
85
1CEAB
87
1LEAB
C1
1D
92
1A1
84
1B1
C1
1D
To 17 Other Channels
36
2OEBA
35
2CEBA
37
2LEBA
40
2OEAB
41
2CEAB
39
2LEAB
C1
1D
14
2A1
62
2B1
C1
1D
To 17 Other Channels
Pin numbers shown are for the PZ package.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABTH32543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABTH32543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): PZ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50°C/W
Storage temperature range, T
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH32543 SN74ABTH32543
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ABTH32543
SN74ABTH32543
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= – 3 mA
= – 3 mA
= – 24 mA
= – 32 mA
= 48 mA
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
V
= 4.5 V
= 4.5 V
CC
CC
2
0.55
0.55
0.55
V
V
V
V
OL
= 64 mA
100
100
mV
hys
Control inputs
A or B ports
Control inputs
A or B ports
V
V
= 0 to 5.5 V,
V = V
or GND
or GND
±1
CC
I
CC
CC
= 2.1 V to 5.5 V,
V = V
I
±20
CC
µA
I
I
±1
V
= 5.5 V,
= 4.5 V
V = V
I
or GND
CC
CC
CC
±20
V = 0.8 V
I
100
I
A or B ports
V
µA
I(hold)
V = 2 V
I
–100
‡
I
I
I
I
I
V
V
V
V
V
= 0 to 2.1 V, V = 0.5 V to 2.7 V, OE = X
±50
±50
±50
±50
±100
50
µA
µA
µA
µA
mA
OZPU
OZPD
off
CC
CC
CC
CC
CC
O
‡
= 2.1 V to 0, V = 0.5 V to 2.7 V, OE = X
O
= 0,
V or V ≤ 4.5 V
I O
= 5.5 V, V = 5.5 V
O
Outputs high
= 2.5 V
50
–180
3
CEX
§
= 5.5 V,
V
–50
–100
–50
–100
–180
3
O
O
Outputs high
Outputs low
V
= 5.5 V, I = 0,
O
or GND
CC
CC
I
20
20
mA
CC
V = V
I
Outputs disabled
2
2
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1
1
mA
∆I
CC
or GND
CC
Control inputs V = 2.5 V or 0.5 V
C
C
3.5
9.5
3.5
9.5
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
†
‡
§
¶
All typical values are at V
This parameter is specified by characterization.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
= 5 V, T = 25°C.
A
CC
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
A
= 5 V,
CC
= 25°C
SN54ABTH32543 SN74ABTH32543
#
UNIT
MIN
3.3
2.1
1.7
0.6
0.9
MAX
MIN
3.3
2.6
2
MAX
MIN
3.3
2.1
1.7
0.6
0.9
MAX
t
t
Pulse duration, LEAB or LEBA low
ns
ns
w
Data before LEAB↑ or LEBA↑
Setup time
Hold time
su
Data before CEAB↑ or CEBA↑
Data after LEAB↑ or LEBA↑
Data after CEAB↑ or CEBA↑
1.1
1.2
t
h
ns
#
These limits apply only to the SN74ABTH32543.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
A
= 5 V,
CC
= 25°C
SN54ABTH32543 SN74ABTH32543
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
UNIT
MIN
TYP
3.5
3.5
4.6
4.3
4.3
5.2
3.8
4.6
3.8
4.7
3.4
4.2
MAX
5.2
5.1
6.3
5.9
6.7
8
MIN
0.5
0.5
0.8
0.8
0.8
1
MAX
6.3
5.9
7.9
6.9
8.3
8.8
7.4
7.9
7.6
8.2
6.7
7.2
MIN
1
MAX
5.9
5.7
7.5
6.6
8
t
t
t
t
t
t
t
t
t
t
t
t
1
1
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
A or B
B or A
A or B
A or B
A or B
A or B
A or B
ns
ns
ns
ns
ns
ns
1
1.9
1.9
1.7
2.6
1.6
2.4
1.4
2.3
1.3
2
1.9
1.9
1.7
2.6
1.6
2.4
1.4
2.3
1.3
2
LE
CE
CE
OE
OE
8.8
7.1
7.5
7.3
8.1
6.5
6.9
6.6
7
0.5
1
6.1
7.4
6.1
6.6
0.5
1
0.5
0.8
†
These limits apply only to the SN74ABTH32543.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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