5962-9584101QXA [TI]
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS; 16位总线收发器和寄存器具有三态输出型号: | 5962-9584101QXA |
厂家: | TEXAS INSTRUMENTS |
描述: | 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
文件: | 总14页 (文件大小:235K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
SN54ABT16652 . . . WD PACKAGE
SN74ABT16652 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
1OEAB
1CLKAB
1SAB
GND
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
2
3
4
Typical V
< 1 V at V
(Output Ground Bounce)
OLP
CC
1A1
1A2
5
= 5 V, T = 25°C
A
6
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
V
V
7
CC
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
8
Flow-Through Architecture Optimizes PCB
Layout
9
10
11
12
13
14
15
16
17
18
19
20
21
22
High-Drive Outputs (–32-mA I , 64-mA I
)
OL
OH
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
The ’ABT16652 are 16-bit bus transceivers that
consist of D-type flip-flops and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. These devices can be used as
two 8-bit transceivers or one 16-bit transceiver.
V
V
CC
CC
2A7 23
2A8 24
34 2B7
33 2B8
GND 25
32 GND
31 2SBA
30 2CLKBA
29 2OEBA
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the ’ABT16652.
2SAB 26
2CLKAB 27
2OEAB 28
Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions
at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control inputs. When SAB
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all
other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last
state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
description (continued)
To ensure the high-impedance state during power up or power down, OEBA should be tied to V
through a
CC
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
The SN54ABT16652 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16652 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
†
DATA I/O
INPUTS
OPERATION OR FUNCTION
OEAB
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
Input
OEBA
L
L
H
H
H
H
X
L
H or L
H or L
Isolation
↑
↑
X
X
Input
Input
Store A and B data
‡
X
H
L
↑
H or L
X
X
Input
Unspecified
Output
Input
Store A, hold B
‡
X
↑
↑
X
Input
Store A in both registers
Hold A, store B
‡
H or L
↑
X
X
Unspecified
Output
Output
Output
Input
‡
X
L
↑
X
↑
X
X
X
X
L
Input
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
L
L
Input
L
L
X
H or L
X
H
X
X
Input
H
H
H
H
X
Output
Output
H or L
X
H
Input
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
Output
†
‡
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
CLKAB CLKBA SAB
SBA
L
CLKAB CLKBA SAB
SBA
X
OEAB OEBA
OEAB OEBA
L
L
X
X
X
H
H
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
CLKAB CLKBA SAB
SBA
X
CLKAB CLKBA SAB
SBA
H
OEAB OEBA
OEAB OEBA
X
L
L
H
X
H
X
↑
X
X
X
H
L
H or L
H or L
H
↑
X
X
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
†
logic symbol
56
EN1 [BA]
EN2 [AB]
C3
1OEBA
1OEAB
1CLKBA
1SBA
1
55
54
2
G4
1CLKAB
1SAB
C5
3
G6
29
28
30
31
27
26
EN7 [BA]
EN8 [AB]
C9
2OEBA
2OEAB
2CLKBA
2SBA
G10
2CLKAB
2SAB
C11
G12
52
≥ 1
5
3D
2
1B1
4
4
1A1
1
1
≥ 1
5D
6
6
1
6
51
49
48
47
45
44
43
42
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
8
9
10
12
13
14
≥ 1
10
15
9D
2A1
7
10 1
≥ 1
11D 12
1 12
8
16
17
19
20
21
23
24
41
40
38
37
36
34
33
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
logic diagram (positive logic)
56
1OEBA
1
1OEAB
55
1CLKBA
54
1SBA
2
1CLKAB
3
1SAB
One of Eight Channels
1D
C1
5
1A1
52
1B1
1D
C1
To Seven Other Channels
29
2OEBA
28
2OEAB
30
2CLKBA
31
2SBA
27
2CLKAB
26
2SAB
One of Eight Channels
1D
C1
15
2A1
42
2B1
1D
C1
To Seven Other Channels
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT16652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT16652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16652 SN74ABT16652
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
48
–32
64
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
–55
125
–40
85
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT16652 SN74ABT16652
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
hys
Control
inputs
±1
±1
±1
I
I
V
CC
= 5.5 V, V = V
I
or GND
µA
CC
A or B ports
±20
10
±20
10
±20
10
‡
I
I
I
V
V
V
= 5.5 V,
= 5.5 V,
= 0,
V
V
= 2.7 V
= 0.5 V
µA
µA
µA
OZH
CC
CC
CC
CC
O
‡
–10
±100
–10
–10
±100
OZL
off
O
V or V ≤ 4.5 V
I
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
= 2.5 V
50
50
50
µA
CEX
O
§
I
O
V
CC
= 5.5 V,
V
O
–50
–100
–180
2
–50
–180
2
–50
–180
2
mA
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
Data inputs
32
2
32
2
32
2
mA
CC
V = V
I
or GND
CC
Outputs disabled
V
CC
= 5.5 V,
Outputs enabled
Outputs disabled
50
50
50
50
50
50
50
50
50
One input at 3.4 V,
Other inputs at
¶
µA
∆I
CC
V
CC
or GND
Control
inputs
V
CC
= 5.5 V, One input at 3.4 V,
or GND
Other inputs at V
CC
Control
inputs
C
C
V = 2.5 V or 0.5 V
4
8
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
and I
The parameters I
include the input leakage current.
OZL
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT16652
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
125
0
4.3
4
125
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
4.3
3.5
0.5
w
ns
su
h
0.5
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT16652
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
125
0
4.3
3
125
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
4.3
3
w
ns
su
h
0
0
ns
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 2)
L
SN54ABT16652
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
MIN
MAX
MIN
125
1.5
1.5
1
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
125
1
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
3.1
3.2
2.3
3
4
4.1
3.2
4.1
4.3
4.6
4.1
4.4
4.7
4
5
5
CLK
B or A
1
0.6
0.6
0.6
0.6
0.6
1
4
A or B
B or A
ns
ns
ns
ns
ns
ns
1
4.9
5.3
5.3
5.2
5.4
5.3
5.3
4.7
5
1
2.9
3.1
2.8
3.1
3.4
2.7
2.6
2.8
4.2
3.4
†
B or A
SAB or SBA
OEBA
1
1
A
A
B
B
1.5
1.5
1.5
1
0.8
1
OEBA
3.6
4.5
5.9
4.9
0.8
1
OEAB
1.5
2
1
6.4
5.9
OEAB
1.5
1
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 2)
L
SN74ABT16652
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
MIN
MAX
MIN
125
1.5
1.5
1
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
125
1.5
1.5
1
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
3.1
3.2
2.3
3
4
4.1
3.2
4.1
4.3
4.3
4.1
4.4
4.4
3.6
3.6
3.9
5.5
4.5
4.9
4.7
3.9
4.6
5
CLK
B or A
A or B
B or A
ns
ns
ns
ns
ns
ns
1
1
1
2.9
3.1
2.8
3.1
3.4
2.7
2.6
2.8
4.2
3.4
1
†
B or A
SAB or SBA
OEBA
1
1
5
1
1
5
A
A
B
B
1.5
1.5
1.5
1
1.5
1.5
1.5
1
5.3
4.9
4
OEBA
4.2
4.6
5.9
5.2
OEAB
1.5
2
1.5
2
OEAB
1.5
1.5
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16652, SN74ABT16652
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9584101QXA
SN74ABT16652DL
ACTIVE
ACTIVE
CFP
WD
56
56
1
TBD
Call TI
Level-NC-NC-NC
SSOP
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ABT16652DLG4
SN74ABT16652DLR
SN74ABT16652DLRG4
SNJ54ABT16652WD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
CFP
DL
DL
56
56
56
56
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
WD
1
TBD
Call TI
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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