5962-9676801Q2A [TI]
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS; 具有三态输出翻两番总线缓冲器GATES
| 型号： | 5962-9676801Q2A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| 文件： | 总18页 (文件大小：637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002
Typical V
(Output Ground Bounce)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
OLP
<1 V at V
= 5 V, T = 25°C
CC
A
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
High-Drive Outputs (–32-mA I , 64-mA I
)
OH
OL
I
and Power-Up 3-State Support Hot
off
Insertion
SN54ABT125 . . . J OR W PACKAGE
SN74ABT125 . . . D, DB, N, NS,
OR PW PACKAGE
SN74ABT125 . . . RGY PACKAGE
(TOP VIEW)
SN54ABT125 . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
V
CC
4OE
1
2
3
4
5
6
7
14
13
12
11
10
9
1
14
3
2
1
20 19
18 4A
1Y
NC
4
5
6
7
8
13
12
11
10
9
2
3
4
5
6
1A
1Y
2OE
2A
4OE
4A
4Y
3OE
3A
17
16
15
14
NC
4Y
4A
4Y
3OE
3A
3Y
2OE
NC
NC
3OE
2A
2Y
9 10 11 12 13
7
8
GND
8
NC – No internal connection
description/ordering information
The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE) input is high.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
Tube
SN74ABT125N
SN74ABT125N
QFN – RGY
Tape and reel
Tube
SN74ABT125RGYR AB125
SN74ABT125D
ABT125
SOIC – D
–40°C to 85°C
–55°C to 125°C
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
SN74ABT125DR
SOP – NS
SSOP – DB
TSSOP – PW
CDIP – J
SN74ABT125NSR
SN74ABT125DBR
SN74ABT125PWR
SNJ54ABT125J
ABT125
AB125
AB125
SNJ54ABT125J
SNJ54ABT125W
SNJ54ABT125FK
CFP – W
Tube
SNJ54ABT125W
SNJ54ABT125FK
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
H
L
H
X
Z
logic diagram (positive logic)
1
10
1OE
3OE
3A
2
3
9
8
1A
1Y
2Y
3Y
4Y
4
13
12
2OE
4OE
4A
5
6
11
2A
Pin numbers shown are for the D, DB, J, N, NS, PW, RGY, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002
recommended operating conditions (see Note 4)
SN54ABT125 SN74ABT125
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
10
10
200
200
CC
T
Operating free-air temperature
–55
125
–40
85
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT125
SN74ABT125
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
V
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
µA
µA
µA
µA
µA
µA
hys
I
I
I
I
I
I
V
V
V
V
V
V
= 0 to 5.5 V,
V = V or GND
I CC
±1
±50
±50
10
±1
±50
±50
10
±1
±50
±50
10
I
CC
CC
CC
CC
CC
CC
CC
= 0 to 2.1 V, V = 0.5 V to 2.7 V, OE = X
OZPU
OZPD
OZH
OZL
off
O
= 2.1 V to 0, V = 0.5 V to 2.7 V, OE = X
O
= 2.1 V to 5.5 V,
= 2.1 V to 5.5 V,
= 0,
V
V
= 2.7 V, OE ≥ 2 V
= 0.5 V, OE ≥ 2 V
O
–10
±100
–10
–10
±100
O
V or V ≤ 4.5 V
I
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
= 2.5 V
50
50
50
µA
CEX
O
‡
§
§
§
–50 –200
I
O
V
CC
= 5.5 V,
V
O
–50
–100 –200
–50 –200
mA
µA
Outputs high
Outputs low
1
24
250
30
250
30
250
30
V
I
= 5.5 V,
= 0,
CC
O
I
mA
µA
CC
V = V
I
or GND
CC
Outputs disabled
0.5
250
250
250
V
= 5.5 V,
CC
Outputs enabled
Outputs disabled
1.5
0.05
1.5
1.5
0.05
1.5
1.5
0.05
1.5
Data
One input at 3.4 V,
Other inputs at
inputs
¶
∆I
CC
mA
V
CC
or GND
Control
inputs
V
CC
= 5.5 V, One input at 3.4 V,
or GND
Other inputs at V
CC
V = 2.5 V or 0.5 V
C
C
3
7
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This limit may vary among suppliers.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT125 SN74ABT125
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
TYP
3.2
2.5
3.6
2.5
3.8
3.3
MAX
4.6
4.6
5
MIN
1
MAX
6
MIN
1
MAX
4.9
4.9
5.9
6.8
6.2
6.2
†
†
†
t
t
t
t
t
t
PLH
PHL
A
Y
Y
Y
ns
ns
ns
1
1
6.2
6
1
1
1
1
PZH
OE
OE
†
1
6.2
5.4
5.3
1
7.5
6.3
6.5
1
PZL
1
1
1
PHZ
†
1
1
1
PLZ
†
This limit may vary among suppliers.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. includes probe and jig capacitance.
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9676801Q2A
5962-9676801QCA
5962-9676801QDA
SN74ABT125D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
14
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
D
1
SOIC
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74ABT125DBLE
SN74ABT125DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
None
Call TI
Call TI
2000
2500
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74ABT125DR
SN74ABT125N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
SO
D
N
14
14
14
14
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74ABT125NSR
SN74ABT125PW
NS
PW
2000
90
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TSSOP
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74ABT125PWLE
SN74ABT125PWR
OBSOLETE TSSOP
PW
PW
14
14
None
Call TI
Call TI
ACTIVE
TSSOP
2000
1000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74ABT125RGYR
ACTIVE
QFN
RGY
14
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR
SNJ54ABT125FK
SNJ54ABT125J
SNJ54ABT125W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
5962-9677001QXX
IC 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, CQFP100, CERAMIC, QFP-100, Serial IO/Communication Controller
WEDC
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