5962-9686301QCA [TI]

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS; 具有三态输出翻两番总线缓冲器GATES
5962-9686301QCA
元器件型号: 5962-9686301QCA
生产厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述和应用:

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
具有三态输出翻两番总线缓冲器GATES

总线驱动器总线收发器逻辑集成电路输出元件
PDF文件: 总20页 (文件大小:747K)
下载文档:  下载PDF数据表文档文件
型号参数:5962-9686301QCA参数
Brand NameTexas Instruments
是否无铅 含铅
是否Rohs认证 不符合
生命周期Obsolete
IHS 制造商TEXAS INSTRUMENTS INC
零件包装代码DIP
包装说明CERAMIC, DIP-14
针数14
Reach Compliance Codenot_compliant
HTS代码8542.39.00.01
风险等级5.65
Is SamacsysN
其他特性DUMMY VAL
控制类型ENABLE HIGH
系列AHCT/VHCT/VT
JESD-30 代码R-GDIP-T14
长度19.56 mm
负载电容(CL)50 pF
逻辑集成电路类型BUS DRIVER
最大I(ol)0.008 A
位数4
功能数量1
端口数量2
端子数量14
最高工作温度125 °C
最低工作温度-55 °C
输出特性3-STATE
输出极性TRUE
封装主体材料CERAMIC, GLASS-SEALED
封装代码DIP
封装等效代码DIP14,.3
封装形状RECTANGULAR
封装形式IN-LINE
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
Prop。Delay @ Nom-Sup8.5 ns
传播延迟(tpd)8.5 ns
认证状态Not Qualified
筛选级别MIL-PRF-38535 Class Q
座面最大高度5.08 mm
子类别Bus Driver/Transceiver
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度7.62 mm
Base Number Matches1
MAX34334CSE前5页PDF页面详情预览
SN54AHCT126, SN74AHCT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS265O – DECEMBER 1995 – REVISED JULY 2003
D
D
D
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
SN54AHCT126 . . . J OR W PACKAGE
SN74AHCT126 . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
The ’AHCT126 devices are quadruple bus buffer
gates featuring independent line drivers with
3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low. When
OE is high, the respective gate passes the data
from the A input to its Y output.
To ensure the high-impedance state during power
up or power down, OE should be tied to GND
through a pulldown resistor; the minimum value of
the resistor is determined by the current-sourcing
capability of the driver.
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4OE
4A
4Y
3OE
3A
3Y
SN54AHCT126 . . . FK PACKAGE
(TOP VIEW)
1A
1OE
NC
V
CC
4OE
1Y
NC
2OE
NC
2A
3
4
5
6
7
8
2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3OE
NC – No internal connection
ORDERING INFORMATION
TA
PDIP – N
SOIC – D
SOP – NS
SSOP – DB
TSSOP – PW
TVSOP – DGV
CDIP – J
–55°C to 125°C
CFP – W
LCCC – FK
PACKAGE†
Tube
Tube
Tape and reel
–40°C to 85°C
Tape and reel
Tape and reel
Tube
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74AHCT126N
SN74AHCT126D
SN74AHCT126DR
SN74AHCT126NSR
SN74AHCT126DBR
SN74AHCT126PW
SN74AHCT126PWR
SN74AHCT126DGVR
SNJ54AHCT126J
SNJ54AHCT126W
SNJ54AHCT126FK
AHCT126
HB126
HB126
HB126
SNJ54AHCT126J
SNJ54AHCT126W
SNJ54AHCT126FK
TOP-SIDE
MARKING
SN74AHCT126N
AHCT126
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
1
SN54AHCT126, SN74AHCT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS265O – DECEMBER 1995 – REVISED JULY 2003
FUNCTION TABLE
(each buffer)
INPUTS
OE
H
H
L
A
H
L
X
OUTPUT
Y
H
L
Z
logic diagram (positive logic)
1OE
1A
1
2
3
3OE
1Y
3A
10
9
8
3Y
2OE
2A
4
5
6
4OE
2Y
4A
13
12
11
4Y
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN54AHCT126, SN74AHCT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS265O – DECEMBER 1995 – REVISED JULY 2003
recommended operating conditions (see Note 3)
SN54AHCT126
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
0
4.5
2
0.8
5.5
VCC
–8
8
20
0
0
MAX
5.5
SN74AHCT126
MIN
4.5
2
0.8
5.5
VCC
–8
8
20
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
II
IOZ
ICC
∆I
CC†
Ci
Co
TEST CONDITIONS
IOH = –50
m
A
IOH = –8 mA
IOL = 50
m
A
IOL = 8 mA
VI = 5.5 V or GND
VO = VCC or GND
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
VI = VCC or GND
VO = VCC or GND
VCC
4.5
45V
4.5
45V
0 V to 5.5 V
5.5 V
5.5 V
5.5 V
5V
5V
4
15
TA = 25°C
MIN
TYP
MAX
4.4
3.94
0.1
0.36
±0.1
±0.25
2
1.35
10
4.5
SN54AHCT126
MIN
4.4
3.8
0.1
0.44
±1*
±2.5
20
1.5
MAX
SN74AHCT126
MIN
4.4
3.8
0.1
0.44
±1
±2.5
20
1.5
10
MAX
UNIT
V
V
m
A
m
A
m
A
mA
pF
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
† This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
SN54AHCT126, SN74AHCT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS265O – DECEMBER 1995 – REVISED JULY 2003
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
FROM
(INPUT)
A
TO
(OUTPUT)
Y
Y
Y
LOAD
CAPACITANCE
CL = 15 pF
CL = 15 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
3.8*
3.8*
3.6*
3.6*
4.6*
4.6*
5.3
5.3
5.1
5.1
6.1
6.1
5.5*
5.5*
5.1*
5.1*
6.8*
6.8*
7.5
7.5
7.1
7.1
8.8
8.8
1**
SN54AHCT126
MIN
1*
1*
1*
1*
1*
1*
1
1
1
1
1
1
MAX
6.5*
6.5*
6*
6*
8*
8*
8.5
8.5
8
8
10
10
SN74AHCT126
MIN
1
1
1
1
1
1
1
1
1
1
1
1
MAX
6.5
6.5
6
6
8
8
8.5
8.5
8
8
10
10
1
UNIT
ns
ns
ns
OE
OE
A
Y
Y
Y
ns
ns
ns
ns
OE
OE
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25°C (see Note 4)
PARAMETER
VOL(P)
VOL(V)
VOH(V)
VIH(D)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
4.4
2
0.8
SN74AHCT126
MIN
MAX
0.8
–0.8
UNIT
V
V
V
V
V
VIL(D)
Low-level dynamic input voltage
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load,
f = 1 MHz
TYP
14
UNIT
pF
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN54AHCT126, SN74AHCT126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS265O – DECEMBER 1995 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
S1
VCC
Open
GND
From Output
Under Test
CL
(see Note A)
Test
Point
From Output
Under Test
CL
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
S1
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3V
Timing Input
tw
3V
tsu
Data Input
0V
1.5 V
1.5 V
0V
th
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
1.5 V
tPZL
50% VCC
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
1.5 V
0V
tPLZ
≈V
CC
VOL + 0.3 V
VOL
tPHZ
VOH – 0.3 V
VOH
≈0
V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
1.5 V
1.5 V
0V
tPHL
50% VCC
VOH
50% VCC
VOL
tPLH
50% VCC
VOH
50% VCC
VOL
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
Ω,
tr
3 ns, tf
3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
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