5962-9686501QSA [TI]

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS; 八路边沿触发D型触发器具有​​三态输出
5962-9686501QSA
元器件型号: 5962-9686501QSA
生产厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述和应用:

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
八路边沿触发D型触发器具有​​三态输出

总线驱动器总线收发器触发器逻辑集成电路输出元件
PDF文件: 总17页 (文件大小:555K)
下载文档:  下载PDF数据表文档文件
型号参数:5962-9686501QSA参数
Brand NameTexas Instruments
生命周期Active
零件包装代码DFP
包装说明DFP, FL20,.3
针数20
Reach Compliance Codenot_compliant
ECCN代码EAR99
HTS代码8542.39.00.01
风险等级5.38
Is SamacsysN
控制类型ENABLE LOW
计数方向UNIDIRECTIONAL
系列AHCT/VHCT/VT
JESD-30 代码R-GDFP-F20
长度13.09 mm
负载电容(CL)50 pF
逻辑集成电路类型BUS DRIVER
最大频率@ Nom-Sup75000000 Hz
最大I(ol)0.008 A
位数8
功能数量1
端口数量2
端子数量20
最高工作温度125 °C
最低工作温度-55 °C
输出特性3-STATE
输出极性TRUE
封装主体材料CERAMIC, GLASS-SEALED
封装代码DFP
封装等效代码FL20,.3
封装形状RECTANGULAR
封装形式FLATPACK
包装方法TUBE
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
最大电源电流(ICC)0.04 mA
Prop。Delay @ Nom-Sup11.5 ns
传播延迟(tpd)11.5 ns
认证状态Qualified
筛选级别MIL-PRF-38535 Class Q
座面最大高度2.45 mm
子类别Bus Driver/Transceiver
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子形式FLAT
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
触发器类型POSITIVE EDGE
宽度6.92 mm
Base Number Matches1
MAX34334CSE前5页PDF页面详情预览
SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241L – OCTOBER 1995 – REVISED JULY 2003
D
D
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54AHCT374 . . . FK PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
1D
1Q
OE
V
CC
8Q
2D
2Q
3Q
3D
4D
3 2
4
5
6
7
8
1 20 19
18
17
16
15
14
9 10 11 12 13
SN54AHCT374 . . . J OR W PACKAGE
SN74AHCT374 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
8D
7D
7Q
6Q
6D
description/ordering information
The ’AHCT374 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable
for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without interface or pullup components.
ORDERING INFORMATION
TA
PDIP – N
SOIC – DW
–40°C to 85°C
40°C
SOP – NS
SSOP – DB
TSSOP – PW
TVSOP – DGV
CDIP – J
–55°C to 125°C
CFP – W
LCCC – FK
PACKAGE†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74AHCT374N
SN74AHCT374DW
SN74AHCT374DWR
SN74AHCT374NSR
SN74AHCT374DBR
SN74AHCT374PW
SN74AHCT374PWR
SN74AHCT374DGVR
SNJ54AHCT374J
SNJ54AHCT374W
SNJ54AHCT374FK
TOP-SIDE
MARKING
SN74AHCT374N
AHCT374
AHCT374
HB374
HB374
HB374
SNJ54AHCT374J
SNJ54AHCT374W
SNJ54AHCT374FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4Q
GND
CLK
5Q
5D
1
SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241L – OCTOBER 1995 – REVISED JULY 2003
description/ordering information (continued)
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
logic diagram (positive logic)
OE
1
CLK
11
C1
2
1D
3
1D
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±75
mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241L – OCTOBER 1995 – REVISED JULY 2003
recommended operating conditions (see Note 3)
SN54AHCT374
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
0
4.5
2
0.8
5.5
VCC
–8
8
20
0
0
MAX
5.5
SN74AHCT374
MIN
4.5
2
0.8
5.5
VCC
–8
8
20
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
II
IOZ
ICC
∆I
CC†
Ci
Co
TEST CONDITIONS
IOH = –50
m
A
IOH = –8 mA
IOL = 50
m
A
IOL = 8 mA
VI = 5.5 V or GND
VO = VCC or GND,
VI = VIH or VIL
IO = 0
VCC
4.5
45V
4.5
45V
0 V to 5.5 V
5.5 V
5.5 V
5.5 V
5V
5V
4
9
TA = 25°C
MIN
TYP MAX
4.4
3.94
0.1
0.36
±0.1
±0.25
4
1.35
10
4.5
SN54AHCT374
MIN
4.4
3.8
0.1
0.44
±1*
±2.5
40
1.5
MAX
SN74AHCT374
MIN
4.4
3.8
0.1
0.44
±1
±2.5
40
1.5
10
MAX
UNIT
V
V
m
A
m
A
m
A
mA
pF
pF
VI = VCC or GND,
One input at 3.4 V,
Other inputs at VCC or GND
VI = VCC or GND
VO = VCC or GND
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
† This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
tsu
th
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
6.5
2.5
2.5
SN54AHCT374
MIN
6.5
2.5
2.5
MAX
SN74AHCT374
MIN
6.5
2.5
2.5
MAX
UNIT
ns
ns
ns
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241L – OCTOBER 1995 – REVISED JULY 2003
switching characteristics over recommended free-air temperature operating range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLK
Q
Q
Q
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 15 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
90**
85
140**
130
5.6**
5.6**
6.5**
6.5**
6.2**
6.2**
6.4
6.4
7.3
7.3
7
7
9.4**
9.4**
10.2**
10.2**
10.2**
10.2**
10.4
10.4
11.2
11.2
11.2
11.2
1***
SN54AHCT374
MIN
80**
75
1**
1**
1**
1**
1**
1**
1
1
1
1
1
1
10.5**
10.5**
11.5**
11.5**
11**
11**
11.5
11.5
12.5
12.5
12
12
MAX
SN74AHCT374
MIN
80
75
1
1
1
1
1
1
1
1
1
1
1
1
10.5
10.5
11.5
11.5
11
11
11.5
11.5
12.5
12.5
12
12
1
MAX
UNIT
MHz
ns
ns
ns
OE
OE
CLK
Q
Q
Q
ns
ns
ns
ns
OE
OE
tsk(o)
CL = 50 pF
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25°C (see Note 4)
PARAMETER
VOL(P)
VOL(V)
VOH(V)
VIH(D)
VIL(D)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low-level dynamic input voltage
3.8
2
0.8
SN74AHCT374
MIN
TYP
0.8
–0.8
MAX
1.2
–1.2
UNIT
V
V
V
V
V
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load,
f = 1 MHz
TYP
27
UNIT
pF
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN54AHCT374, SN74AHCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS241L – OCTOBER 1995 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
S1
VCC
Open
GND
From Output
Under Test
CL
(see Note A)
Test
Point
From Output
Under Test
CL
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
S1
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3V
Timing Input
1.5 V
0V
3V
tsu
Data Input
0V
1.5 V
th
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
1.5 V
tPZL
50% VCC
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
1.5 V
0V
tPLZ
≈V
CC
VOL + 0.3 V
VOL
tPHZ
VOH – 0.3 V
VOH
≈0
V
tw
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
1.5 V
1.5 V
0V
tPHL
50% VCC
VOH
50% VCC
VOL
tPLH
50% VCC
VOH
50% VCC
VOL
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
Ω,
tr
3 ns, tf
3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
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