5962-F8961501QPA [TI]
LINE TRANSCEIVER, CDIP8, CERDIP-8;
| 型号： | 5962-F8961501QPA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LINE TRANSCEIVER, CDIP8, CERDIP-8 CD |
| 文件： | 总17页 (文件大小：769K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Texas Instruments.
Search http://www.ti.com/ for the latest technical
information and details on our current products and services.
September 2005
DS16F95QML
EIA-485/EIA-422A Differential Bus Transceiver
The driver is designed to accommodate loads of up to 60 mA
of sink or source current and features positive and negative
current limiting in addition to thermal shutdown for protection
from line fault conditions.
General Description
The DS16F95 Differential Bus Transceiver is a monolithic
integrated circuit designed for bidirectional data communica-
tion on balanced multipoint bus transmission lines. The
transceiver meets EIA standard RS-485 as well as RS-422A.
The DS16F95 can be used in transmission line applications
employing the DS96F172 and the DS96F174 quad differen-
tial line drivers and the DS96F173 and DS96F175 quad
differential line receivers.
The DS16F95 offers improved performance due to the use
of state-of-the-art L-FAST bipolar technology. The L-FAST
technology allows for higher speeds and lower currents by
utilizing extremely short gate delay times. Thus, the
DS16F95QML features lower power, extended temperature
range and improved specifications.
The DS16F95 combines a TRI-STATE® differential input line
receiver, both of which operate from a single 5.0V power
supply. The driver and receiver have an active Enable that
can be externally connected to function as a direction con-
trol. The driver differential outputs and the receiver differen-
tial inputs are internally connected to form differential input/
output (I/O) bus ports that are designed to offer minimum
loading to the bus whenever the driver is disabled or when
VCC = 0V. These ports feature wide positive and negative
common mode voltage ranges, making the device suitable
for multipoint applications in noisy environments.
Features
n Radiation features DS16F95 guaranteed to 300k rd(Si)
n Meets EIA-485 and EIA-422A
n Meets SCSI-1 (5 MHZ) specifications
n Designed for multipoint transmission
n Wide positive and negative input/output bus voltage
ranges
n Thermal shutdown protection
n Driver positive and negative current-limiting
n High impedance receiver input
n Receiver input hysteresis of 50 mV typical
n Operates from single 5.0V supply
n Reduced power consumption
n Pin compatible with DS3695 and SN75176A
Ordering Information
NS PART NUMBER
DS16F95E/883
SMD PART NUMBER
5962–89615012A
5962–8961501PA
5962–8961501VPA
5962F8961501QPA
300k rd(Si)
NS PACKAGE NUMBER
PACKAGE DISCRIPTION
20LD LCC
E20A
J08A
J08A
DS16F95J/883
8LD CERDIP
DS16F95J-QMLV
8LD CERDIP
DS16F95JFQML
DS16F95JFQMLV
J08A
J08A
8LD CERDIP
5962F8961501VPA
300k rd(Si)
8LDS CERDIP
DS16F95W-SMD
DS16F95W/883
5962–8961501HA
W10A
W10A
W10A
10LD CERPACK
10LD CERPACK
10LD CERPACK
DS16F95W-QMLV
5962–8961501VHA
5962F8961501QHA
300k rd(Si)
DS16F95WFQML
DS16F95WFQMLV
W10A
W10A
10LD CERPACK
10LD CERPACK
5962F8961501VHA
300k rd(Si)
DS16F95WG/883
5962–8961501QXA
5962–8961501VXA
5962F8961501QXA
300k rd(Si)
WG10A
WG10A
10LD Ceramic SOIC
10LD Ceramic SOIC
DS16F95WG-QMLV
DS16F95WGFQML
DS16F95WGFQMLV
WG10A
WG10A
10LD Ceramic SOIC
10LD Ceramic SOIC
5962F8961501VXA
300k rd(Si)
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation
DS201425
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Connection Diagrams
20-Lead Ceramic Leadless Chip Carrier
20142521
See NS Package Number E20A
8-Lead Dual-In-Line Package
20142501
See NS Package Number J08A
10-Lead Flatpak/SOIC Package
20142522
See NS Package Number W10A, WG10A
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2
Logic Diagram
20142520
Function Tables
Driver
Driver Input
Enable
Outputs
DI
H
L
DE
H
A
H
L
B
L
H
H
Z
X
L
Z
Receiver
Differential Inputs
A–B
Enable
Output
RE
L
RO
H
VID ≥ 0.2V
VID ≤ −0.2V
X
L
L
H
Z
H = High Level
L = Low Level
X = Immaterial
Z = High Impedance (Off)
3
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Absolute Maximum Ratings (Note 1)
Storage Temperature Range
Lead Temperature
−65˚C ≤ TA ≤ +175˚C
(Soldering, 60 sec.)
Maximum Power Dissipation at 25˚C (Note 2)
LCC ’E’ Package
300˚C
1800 mW
1274 mW
725 mW
725 mW
7.0V
Cerdip ’J’ Package
Cerpack ’W’ Package
Ceramic SOIC ’WG’ Package
Supply Voltage
Input Voltage (Bus Terminal)
Enable Input Voltage
Junction Temperature (TJ)
Thermal Resistance
θJA
+15V/−10V
5.5V
+175˚C
@
83˚C/W 0.5W
LCC ’E’ Package
@
118˚C/W 1.0W
Cerdip ’J’ Package
@
207˚C/W 0.5W
Cerpack ’W’ Package
Ceramic SOIC ’WG’ Package
θJC
@
207˚C/W 0.5W
LCC ’E’ Package
17˚C/W
14˚C/W
18˚C/W
18˚C/W
500V
Cerdip ’J’ Package
Cerpack ’W’ Package
Ceramic SOIC ’WG’ Package
ESD Tolerance (Note 3)
Recommended Operating Conditions
Supply Voltage (VCC
)
4.50 to 5.50V
Voltage at Any Bus Terminal
(Separately or Common Mode)
(VI or VCM
)
−7.0V to +12V
−7.0V to 12V
Differential Input Voltage (VID
)
Output Current HIGH (IOH
)
Driver
−60mA
−400µA
Receiver
Output Current LOW (IOL
)
Driver
60mA
Receiver
16mA
Operating Temperature (TA)
−55˚C to +125˚C
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4
Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp ( C)
+25
1
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
+25
5
+125
-55
6
7
+25
8A
8B
9
+125
-55
+25
10
11
+125
-55
DC - Driver Electrical Characteristics (Note 10)
The following conditions apply to all parameters, unless otherwise specified. VCC = 5.5V
Symbol
Parameter
Conditions
Notes
Min
Max Unit
Sub-group
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VCC = 5.5V, IO = 0A, VIN = .8V
VCC = 5.5V, IO = 0A, VIN = 2V
VCC = 4.5V, RL = 100Ω
VCC = 4.5V, RL = 54Ω
VCC = 4.5V, RL = 100Ω
VCC = 4.5V, RL = 54Ω
6
6
V
VOD1
Differential Vout
V
VOD2
Differential Vout
2
V
Figure 1
1.5
V
Delta VOD Change In Differential Vout
(Note 4) -200 200
mV
mV
mV
mV
V
(Note 4) -200 200
Delta VOC Change In Common Mode Vout VCC = 4.5V, RL = 100Ω
VCC = 4.5V, RL = 54Ω
(Note 4) -200 200
(Note 4) -200 200
VOC
Common Mode Vout
RL = 100Ω
3
RL = 54Ω
3
V
IIH
IO
Logical "1" Input Current
Output Current
VI = 2.4V
20
uA
mA
mA
mA
Output Disable, VO = 12V
Output Disable, VO = -7V
VCC = 0, Output Disable,
VO = 12V
1
(Note 5) -0.8
1
VCC = 0, Output Disable,
VO = -7V
(Note 5) -0.8
mA
1, 2, 3
IOS
Output Short Circuit
VIN = 3V, VOUT = VCC
VIN = 3V, VOUT = -7V
VIN = 3V, VOUT = 0V
VIN = 3V, VOUT = 12V
VIN = 0V, VOUT = 12V
VIN = 0V, VOUT = VCC
VIN = 0V, VOUT = -7V
VIN = 0V, VOUT = 0V
VCC = 4.5V, IO = -20mA
VCC = 4.5V, IO = 20mA
VCM = -7V to 12V
150
mA
mA
mA
mA
mA
mA
mA
mA
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
(Note 5) -250
(Note 5) -150
250
250
150
(Note 5) -250
(Note 5) -150
VOH
Logical "1" Output Voltage
Logical "0" Output Voltage
Differential Vout
3
2
1
VOL
V
VOD3
V
5
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DC - Receiver Electrical Characteristics (Note 10)
The following conditions apply to all parameters, unless otherwise specified. VCC = 5.5V
Symbol
VOH
Parameter
Conditions
Notes
Min
Max Unit
Sub-group
1, 2, 3
Logical "1" Output Voltage
Figure 2
VCC = 4.5V, VLD = 200mV,
IOH = -400uA
2.5
V
VOL
Logical "0" Output Voltage
Figure 2
VCC = 4.5V, VLD = -200mV,
IOL = 8mA
.45
.5
1
V
V
1, 2, 3
VCC = 4.5V, VLD = -200mV,
IOL = 16mA
1, 2, 3
II
Line Input Current
Untested Input = 0V, VI = 12V
Untested Input = 0V, VI = -7V
mA
mA
mA
1, 2, 3
1, 2, 3
1, 2, 3
(Note 5)
-.8
-.8
VCC = 0V, Untested Input = 0V, (Note 5)
VI = 12V
1
VCC = 0V, Untested Input = 0V,
VI = -7V
mA
1, 2, 3
IIH
Logical "1" Input Current
Input Resistance
VI = 2.7V (Receiver)
20
uA
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
RIN
Untested Input = 0V, VI = 12V
Untested Input = 0V, VI = -7V
(Note 6)
(Note 6)
10
10
10
KΩ
KΩ
KΩ
VCC = 0V, Untested Input = 0V, (Note 6)
VI = 12V
VCC = 0V, Untested Input = 0V, (Note 6)
VI = -7V
10
KΩ
1, 2, 3
IOZ
High Impedance State
VI = .4V
-20
-20
-85
20
20
-15
.2
uA
uA
mA
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VI = 2.4V
IOS
Output Short Circuit
Differential Input High
Threshold
VIN = 1V, VOUT = 0V
VCC = 4.5V, VO = 2.5V,
VCM = 12V & 0V & -7V,
IO = -.4mA
VTH
VCC = 5.5V, Vo = 2.5V,
VCM = 12V & 0V & -7V,
IO = -.4mA
.2
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
VT1
Differential Input Low Threshold VCC = 4.5V, VO = .5V,
VCM = 12V & 0V & -7V,
IO = 8mA
-.2
-.2
VCC = 5.5V, VO = .5V,
VCM = 12V & 0V & -7V,
IO = 8mA
V
TH+ -
Hyteresis
VCC = 4.5V, VCM = 0V
VCC = 5.5V, VCM = 0V
35
35
mV
mV
1, 2, 3
1, 2, 3
(VTH-)
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6
DC - Both Driver and Receiver Electrical Characteristics (Note 10)
The following conditions apply to all parameters, unless otherwise specified. VCC = 5.5V
Symbol
ICC
Parameter
Conditions
Notes
Min
Max Unit
Sub-group
1, 2, 3
Supply Current ICC Both
Disable
RE = 2V, DE = .8V
RE =.8V, DE = 2V
25
28
mA
mA
ICC
Supply Current ICC Both
Enable
1, 2, 3
VIC
VIH
VIL
VIH
Input Clamp Volt
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Enable Input
Voltage
II = -18mA
-1.3
2
V
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
.8
.8
2
VIL
I IL
Logical "0" Enable Input
Voltage
V
1, 2, 3
1, 2, 3
Logical "0" Input Current
VI = .4V
(Note 5)
-50
uA
AC - Driver Electrical Characteristics (Note 10)
The following conditions apply to all parameters, unless otherwise specified.
VCC = 5V, PRR = 1MHZ, TR ≤ TF ≤ 6nS, 50% duty cycle, AMP = 3V, VLO, ZOUT = 50Ω
Symbol
Parameter
Conditions
RL = 60Ω
RL = 60Ω
Notes
(Note 9)
(Note 9)
(Notes 8,
9)
Min
8
Max Unit
Sub-group
25
30
25
nS
nS
nS
9
Differential Output Delay Time
tDD
Figure 3
8
10, 11
9
tTD
Differential Output Transition
8
Time
Figure 3
(Notes 8,
9)
8
30
nS
10, 11
tPLH
Propagation Delay Time Low to RL = 27Ω
High
6
6
6
6
18
25
18
25
nS
nS
nS
nS
9
10, 11
9
Figure 4
tPHL
Propagation Delay Time high to RL = 27Ω
Low
10, 11
Figure 4
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time to H
RL = 110Ω
RL = 110Ω
RL = 110Ω
RL = 110Ω
35
45
40
50
30
40
30
40
6
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
9
Figure 5
10, 11
9
Output Enable Time to L
Figure 6
10, 11
9
Output Disable Time to H
Figure 5
10, 11
9
Output Disable Time to L
Figure 6
10, 11
9
TSKEW
Differential Output Skew Time
Figure 3
12
10, 11
7
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AC - Receiver Electrical Characteristics (Note 10)
The following conditions apply to all parameters, unless otherwise specified.
VCC = 5V, PRR = 1MHZ, TR ≤ TF ≤ 6nS, 50% duty cycle, AMP = 3V, VLO, ZOUT = 50Ω
Symbol
Parameter
Conditions
CL = 15pF
CL = 15pF
Notes
Min
10
Max Unit
Sub-group
27
38
27
38
20
30
20
30
8
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
9
Propagation Delay Time Low to
tPLH
High Figure 7
10
10, 11
tPHL
Propagation Delay Time High
10
9
to Low Figure 7
10
10, 11
tPZH
tPZL
Output Enable Time to H
CL = 15pF
CL = 15pF
9
Figure 8
10, 11
Output Enable Time to L
9
Figure 8
10, 11
|tPLH - tPHL| Output to Output Delay Time
9
Figure 7
16
30
10, 11
9
tPHZ
Output Disable Time From H
CL = 20pF
(Notes 7,
15)
Figure 8
(Note 7)
(Note 7)
(Note 7)
40
20
30
20
30
nS
nS
nS
nS
nS
10, 11
9
CL = 5pF
CL = 5pF
10, 11
9
tPLZ
Output Disable Time From L
Figure 8
10, 11
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
Note 2: Above T = 25˚C, derate E package 12.1mW˚C, J package 8.5 mW/˚C, W & WG package 4.8mW/˚C.
A
Note 3: Human body model, 1.5kΩ in series with 100pF
Note 4: ∆|V | and ∆|V | are the changes in magnitude of V
and V , respectively, that occur when the input is changed from a high level to a low level.
OC
OD
OC
OD
Note 5: Negative sign of the limits indicates the direction of the current flow only.
Note 6: R is guaranteed by testing “Line Input Current” (II).
IN
Note 7: Testing at 20pF assures conformance to spec at 5pF.
Note 8: tTD = Non-inverting output rise time + inverting output fall time / 2, Non-inverting output fall time + inverting output rise time / 2.
Note 9: Rise time 20% to 80%, Fall time 80% to 20%.
Note 10: Pre and post irradiation limits are identical to those listed under A C and DC electrical characteristics. These parts may be dose rate sensitive in a space
environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified
in MIL-STD 883, Method 1019, condition A.
Parameter Measurement Information
20142502
FIGURE 1. Driver VOD and VOC (Note 14)
20142503
FIGURE 2. Receiver VOH and VOL
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8
Parameter Measurement Information (Continued)
20142504
20142505
t
= |t
–t
|
SKEW
PLHD PHLD
FIGURE 3. Driver Differential Output Delay and Transition Times (Notes 11, 13)
20142506
20142507
FIGURE 4. Driver Propagation Times (Notes 11, 12)
9
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Parameter Measurement Information (Continued)
20142509
20142508
FIGURE 5. Driver Enable and Disable Times (tZH, tHZ) (Notes 11, 12, 13)
20142511
20142510
FIGURE 6. Driver Enable and Disable Times (tZL, tLZ) (Notes 11, 12, 13)
20142513
20142512
FIGURE 7. Receiver Propagation Delay Times (Notes 11, 12)
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10
Parameter Measurement Information (Continued)
20142517
20142514
20142518
20142515
20142516
FIGURE 8. Receiver Enable and Disable Times (Notes 11, 12, 14)
Note 11: The input pulse is supplied by a generator having the following characteristics: PRR = 1.0 MHz, 50% duty cycle, t ≤ 6.0 ns, t ≤ 6.0 ns, Z = 50Ω.
r
f
O
Note 12: C includes probe and stray capacitance.
L
Note 13: DS16F95 Driver enable is Active-High.
Note 14: All diodes are 1N916 or equivalent.
Note 15: Testing at 20 pF assures conformance to 5 pF specification.
11
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Typical Application
20142519
The line should be terminated at both ends in its characteristic impedance, typically 120Ω.
Stub lengths off the main line should be kept as short as possible.
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12
Revision History
Date
Released
Revision
Section
New Release, Corporate format
Originator
Changes
A
R. Malone 1 MDS data sheet converted into
Corporate data sheet format. MDS data
sheet MNDS16F95-X-RH, Rev. 0A1 will
be Archived.
13
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Ceramic Leadless Chip Carrier (E)
NS Package Number E20A
8 Narrow Lead Ceramic Dual-In-Line Package (J)
NS Package Number J08A
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14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
10-Lead Ceramic SOIC (WG)
NS Package Number WG10A
10-Lead Ceramic Flatpak (W)
NS Package Number W10A
15
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Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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