5962R1124201VFA [TI]
具有 RHA 的 QML V 类 2×2 1Gbps LVDS 交叉点开关 | W | 16 | -55 to 125;
| 型号： | 5962R1124201VFA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 RHA 的 QML V 类 2×2 1Gbps LVDS 交叉点开关 | W | 16 | -55 to 125 开关 |
| 文件： | 总25页 (文件大小：1619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN55LVCP22A-SP
ZHCSNB2 –FEBRUARY 2021
SN55LVCP22A-SP QML V 类2×2 1Gbps LVDS 交叉点开关
• 卫星电力系统(EPS)
1 特性
3 说明
• QML V 类、RHA、SMD 5962-11242
• 辐射性能
SN55LVCP22A-SP 是一款2×2 交叉点开关，使每个路
径实现大于 1000Mbps 的运行速度。两个通道组装有
宽共模（0V 至 4V）接收器，从而实现对 LVDS、
LVPECL 和 CML 信号的接收。两路输出为 LVDS 驱动
器， 用于实现低功耗、低 EMI 、高速运转。
SN55LVCP22A-SP 器件支持 2:2 缓冲（重复）、1:2
分配、2:1 复用、2×2 交换，以及每个通道上的
LVPECL/CML 到LVDS 电平转换。SN55LVCP22A-SP
的灵活运行可满足光网络、无线基础设施和数据通信系
统中容错交换系统对于冗余串行总线传输的需求（运转
和保护交换卡）。
– RHA 能力高达100krad(Si)
– 在100 krad(Si) 的条件下无ELDRS
– SEL 对于LET 的抗扰度= 75 MeV⋅cm2/mg
– SEE 对于LET 的额定值= 75MeV⋅cm2/mg
• 高速（高达1000Mbps）
• 低抖动完全差分数据路径
• 50ps（典型值）的峰峰值抖动，
PRBS = 223-1 模式
• 总功率耗散少于227mW（典型值），313mW（最
大值）
• 输出（通道间）延迟为80ps（典型值）
• 可配置为2:1 多路复用器，1:2 多路信号分离器，
中继器或者1:2 信号分配器
• 输入可接受LVDS、LVPECL 和CML 信号
• 1.7ns（典型值）的快速交换时间
• 0.65ns（典型值）的快速传播延迟
• 与TIA/EIA-644-A LVDS 标准互操作
• 支持国防、航空航天和医疗应用：
SN55LVCP22A-SP 使用一个完全差分数据路径来确保
低噪声生成、快速交换时间、低脉宽失真和低抖动。
80ps（典型值）的输出通道间延迟确保所有应用中输
出的准确一致。
器件信息
封装尺寸（标
封装(1)
器件型号
等级
QMLV RHA
工程样片(2)
称值）
5962R11242
01VFA
6.73mm x
10.3mm
CFP (16)
CFP (16)
– 受控基线
– 一个组装/测试厂和一个制造厂
– 延长产品生命周期和延长产品变更通知
– 产品可追溯性
SN55LVCP2
2W/EM
6.73mm x
10.3mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 这些器件仅适用于工程评估。以非合规性流程对其进行了处理
（例如，未进行老化处理），并且仅在25°C 的额定温度下进
行了测试。这些器件不适用于鉴定、生产、辐射测试或飞行用
途。
2 应用
• 命令和数据处理(C&DH)
• 通信负载
• 雷达成像有效载荷
• 光学成像有效载荷
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFI8
SN55LVCP22A-SP
ZHCSNB2 –FEBRUARY 2021
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
10 Power Supply Recommendations..............................19
11 Layout...........................................................................20
11.1 Layout Guidelines................................................... 20
11.2 Layout Example...................................................... 20
12 Device and Documentation Support..........................21
12.1 Trademarks.............................................................21
12.2 静电放电警告.......................................................... 21
12.3 术语表..................................................................... 21
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 Handling Ratings ........................................................4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Switching Characteristics ...........................................6
6.7 Typical Characteristics................................................7
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................14
8.1 Overview...................................................................14
Information.................................................................... 21
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
February 2021
*
Initial Release
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5 Pin Configuration and Functions
W PACKAGE
(TOP VIEW)
SEL1
SEL0
IN0+
IN0-
16
15
14
13
12
11
10
9
EN0
1
2
3
4
5
EN1
OUT0+
OUT0-
GND
VCC
IN1+
IN1-
OUT1+
OUT1-
NC
6
7
NC
8
NC - No internal connection
表5-1. Pin Functions
TERMINAL
I/O
DESCRIPTION
NAME
SEL1
SEL0
IN0+
IN0-
NO.
1
Input
Input
Switch Selection Control 1
Switch Selection Control 2
LVDS Receiver Positive Input 0
LVDS Receiver Negative Input 0
3.3V Supply Voltage
2
3
Input
4
Input
VCC
5
Power
Input
IN1+
IN1-
6
LVDS Receiver Positive Input 1
LVDS Receiver Negative Input 1
No Internal Connection
7
Input
NC
8
N/A
NC
9
N/A
No Internal Connection
OUT1-
OUT1+
GND
OUT0-
OUT0+
EN1
10
11
12
13
14
15
16
Output
Output
Ground
Output
Output
Input
LVDS Driver Negative Output 1
LVDS Driver Positive Output 1
Ground
LVDS Driver Negative Output 0
LVDS Driver Positive Output 0
Output Enable for Driver 1
Output Enable for Driver 0
EN0
Input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage(2), VCC
–0.5 V to 4 V
–0.5 V to 4 V
–0.7 V to 4.3 V
–0.5 V to 4 V
150°C
CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1)
LVDS receiver input voltage (IN+, IN–)
LVDS driver output voltage (OUT+, OUT–)
Maximum Junction temperature
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminals.
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
-65
125
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
-5000
-500
5000
500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
3
NOM MAX UNIT
Supply voltage, VCC
3.3
3.6
4
V
V
Receiver input voltage
0
(1)
Operating case (top) temperature, TC
125
3
°C
V
–55
0.1
Magnitude of differential input voltage, |VID|
(1) Maximum case temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
6.4 Thermal Information
SN55LVCP22A-SP
THERMAL METRIC(1)
W (CFP)
16 PINS
118.1
51.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
107.2
28.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
95.1
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1)
VIH
VIL
IIH2
IIH
High-level input voltage
Low-level input voltage
High-level input current
High-level input current
Low-level input current
Low-level input current
Input clamp voltage
2
GND
-250
-25
1.5
1.5
±3
VCC
0.8
250
25
V
V
VIN = 3.6 V or 2.0 V, VCC = 0 V
VIN = 3.6 V or 2.0 V, VCC = 3.6 V
VIN = 0.0 V or 0.8 V, VCC = 0 V
VIN = 0.0 V or 0.8 V, VCC = 3.6 V
ICL = –18 mA
µA
µA
µA
µA
V
±3
IIL2
IIL
-150
-15
±1
150
15
±1
VCL
-0.8
-1.5
LVDS OUTPUT SPECIFICATIONS (OUT0, OUT1)
255
320
390
390
475
430
RL = 75 Ω, See 图7-3
|VOD
|
Differential output voltage
mV
RL = 75 Ω, VCC = 3.3 V, TA = 25°C, See 图
7-3
Change in differential output voltage magnitude
between logic states
25
1.45
25
mV
V
Δ|VOD
|
VID = ±100 mV, See 图7-3
See 图7-4
–25
1
VOS
Steady-state offset voltage
1.2
50
Change in steady-state offset voltage between
logic states
mV
ΔVOS
See 图7-4
–25
VOC(PP) Peak-to-peak common-mode output voltage
mV
µA
µA
See 图7-4
IOZ
High-impedance output current
Power-off leakage current
VOUT = GND or VCC
-15
-15
15
15
IOFF
VCC = 0 V, 1.5 V; VOUT = 3.6 V or GND
High-impedance output current, after HDR 100
krad
IOZH
VOUT = VCC, TA = 25°C
-120
-50
350
150
µA
µA
Power-off leakage current, after after HDR 100
krad
IOFFH
VCC = 0 V, 1.5 V; VOUT = 3.6 V, TA = 25°C
IOS
Output short-circuit current
VOUT+ or VOUT- = 0 V
-8
8
mA
mA
pF
IOSB
CO
Both outputs short-circuit current
Differential output capacitance
VOUT+ and VOUT- = 0 V
VI = 0.4 sin(4E6πt) + 0.5 V
–8
3
LVDS RECEIVER DC SPECIFICATIONS (IN0, IN1)
VTH
VTL
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
100
mV
mV
mV
V
See 图7-2 and 表7-1
See 图7-2 and 表7-1
–100
VID(HYS) Differential input voltage hysteresis
20
150
3.95
18
VCMR
Common-mode voltage range
VID = 100 mV, VCC = 3.0 V to 3.6 V
VIN = 4 V, VCC = 3.6 V or 0.0
VIN = 0 V, VCC = 3.6V or 0.0
VI = 0.4 sin (4E6πt) + 0.5 V
0.05
-18
±1
±1
3
IIN
Input current
µA
pF
-18
18
CIN
Differential input capacitance
SUPPLY CURRENT
ICCQ
ICCD
ICCZ
Quiescent supply current
60
63
25
87
87
35
mA
mA
mA
RL = 75 Ω, EN0=EN1=High
RL = 75 Ω, CL = 5 pF, 500 MHz (1000
Mbps), EN0=EN1=High
Total supply current
3-state supply current
EN0 = EN1 = Low
(1) All typical values are at 25°C and with a 3.3-V supply.
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MAX UNIT
6.6 Switching Characteristics
over recommended operating conditions unless otherwise noted
parameter
TEST CONDITIONS
MIN
TYP
0.8
1.0
1.7
2
tSET
Input to SEL setup time
Input to SEL hold time
2.2
2.2
2.6
8
ns
ns
ns
ns
ns
ns
ns
ps
ps
See 图7-7
See 图7-7
See 图7-7
See 图7-6
See 图7-6
See 图7-6
See 图7-6
tHOLD
tSWITCH SEL to switched output
tPHZ
tPLZ
tPZH
tPZL
tLHT
tHLT
Disable time, high-level-to-high-impedance
Disable time, low-level-to-high-impedance
2
8
Enable time, high-impedance -to-high-level output
Enable time, high-impedance-to-low-level output
Differential output signal rise time (20%-80%)(1)
Differential output signal fall time (20%-80%)(1)
2
8
2
8
280
280
620
620
CL = 5 pF, See 图7-5
CL = 5 pF, See 图7-5
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 50 MHz, CL = 5 pF
13.7
13.4
14.4
68.3
73.2
0.97
0.85
0.86
22.2
24.5
35.7
204
282
1.5
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 240 MHz, CL = 5 pF
ps
ps
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 500 MHz, CL = 5 pF
tJIT
Added peak-to-peak jitter(3)
VID = 200 mV, PRBS = 215-1 data pattern,
VCM = 1.2 V, 240 Mbps, CL = 5 pF
VID = 200 mV, PRBS = 215-1 data pattern,
VCM = 1.2 V, 1000 Mbps, CL = 5 pF
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 50 MHz, CL = 5 pF
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 240 MHz, CL = 5 pF
tJrms
Added random jitter (rms)(3)
1.53 psRMS
1.79
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 500 MHz, CL = 5 pF
tPLHD
tPHLD
tskew
tCCS
Propagation delay time, low-to-high-level output(1)
Propagation delay time, high-to-low-level output(1)
Pulse skew (|tPLHD –tPHLD|)(2)
200
200
650
650
45
2350
2350
160
ps
ps
(5)
ps
CL = 5 pF, See 图7-5
CL = 5 pF, See 图7-5
Output channel-to-channel skew, splitter mode
Maximum operating frequency(4)
80
ps
(5)
fMAX
1
GHz
(1) Input: VIC = 1.2 V, VID = 200 mV, 50% duty cycle, 1 MHz, tr/tf = 500 ps
(2) tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device.
(3) Not production tested.
(4) Signal generator conditions: 50% duty cycle, tr or tf ≤100 ps (10% to 90%), transmitter output criteria: duty cycle = 45% to 55% VOD ≥
300 mV.
(5) tskew and fMAX parameters are guaranteed by characterization, but not production tested.
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6.7 Typical Characteristics
600
500
400
300
200
100
0
75
50
25
0
0
40
80
120
160
200
0
400
800
1200
1600
2000
C002
Resistive Load (ꢀ)
Frequency (MHz)
C001
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
|VID| = 200 mV
图6-1. Differential Output Voltage vs Resistive
Load
图6-2. Supply Current vs Frequency
900
30
25
20
15
10
5
300 mV
t
PLH
400 mV
500 mV
600 mV
800 mV
tPHL
825
750
675
600
0
0
20
40
60
80
100
0
100
200
300
400
500
600
œ60
œ40
œ20
Free-Air Temperature (°C)
Frequency (MHz)
C003
C004
VCC = 3 V - 3.6 V
Input = 1 MHz
VIC = 1.2 V
|VID| = 300 mV
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = Clock
图6-3. Propagation Delay Time bs Ffree-Air
图6-4. Peak-To-Peak Jitter vs Frequency
Temperature
60
30
300 mV
300 mV
400 mV
400 mV
50
25
500 mV
500 mV
600 mV
800 mV
600 mV
800 mV
40
30
20
10
0
20
15
10
5
0
0
200
400
600
800
1000
1200
0
100
200
300
400
500
600
Data Rate (Mbps)
Frequency (MHz)
C005
C006
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
Input = PRBS 223 −1
Input = Clock
图6-6. Peak-To-Peak Jitter vs Frequency
图6-5. Peak-To-Peak Jitter vs Data Rate
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60
30
25
20
15
10
5
300 mV
300 mV
400 mV
500 mV
600 mV
800 mV
400 mV
50
500 mV
600 mV
800 mV
40
30
20
10
0
0
0
200
400
600
800
1000
1200
0
100
200
300
400
500
600
C008
Data Rate (Mbps)
Frequency (MHz)
C007
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
VCC = 3.3 V
TA = 25°C
VIC = 1.6 V
Input = PRBS 223 −1
Input = Clock
图6-8. Peak-To-Peak Jitter vs Frequency
图6-7. Peak-To-Peak Jitter vs Data Rate
60
30
300 mV
300 mV
400 mV
50
500 mV
400 mV
25
500 mV
600 mV
800 mV
600 mV
800 mV
40
30
20
10
0
20
15
10
5
0
0
200
400
600
800
1000
1200
0
100
200
300
400
500
600
Data Rate (Mbps)
Frequency (MHz)
C009
C010
VCC = 3.3 V
TA = 25°C
VIC = 1.6 V
VCC = 3.3 V
TA = 25°C
VIC = 3.3 V
Input = PRBS 223 −1
Input = Clock
图6-10. Peak-To-Peak Jitter vs Frequency
图6-9. Peak-To-Peak Jitter vs Data Rate
400
350
300
250
200
150
100
50
80
70
60
50
40
30
20
10
0
60
300 mV
400 mV
50
500 mV
600 mV
40
800 mV
30
Added Random Jitter
20
10
0
0
0
400
800
1200
1600
2000
Frequency (MHz)
C012
0
200
400
600
800
1000
1200
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
Data Rate (Mbps)
C011
|VID| = 200 mV
VCC = 3.3 V
TA = 25°C
VIC = 3.3 V
Input = PRBS 223 −1
图6-12. Differential Output Voltage vs Frequency
图6-11. Peak-To-Peak Jitter vs Data Rate
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230
200
170
140
110
80
50
20
0
500
1000
1500
2000
2500
3000
3500
Data Rate (Mbps)
C013
VCC = 3.3 V
TA = 25°C
Input = PRBS 223 −1
VIC = 1.2 V
|VID| = 200 mV
图6-13. Peak-To-Peak Jitter vs Data Rate
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7 Parameter Measurement Information
INPUTS
V
CC
IN +
IN -
400 Ω
SEL, EN
300 kΩ
7 V
7 V
7 V
OUTPUTS
V
CC
OUT +
OUT -
7 V
7 V
图7-1. Equivalent Input and Output Schematic Diagrams
I
IN+
OUT +
IN+
V
ID
V
OD
V
IN+
V
OY
IN-
V
IC
OUT -
IN+ + IN-
2
V
OUT+
+ V
2
OUT-
V
OZ
I
IN-
V
IN-
图7-2. Voltage And Current Definitions
3.74 kΩ
Y
+
_
0 V ≤ V
≤ 2.4 V
V
OD
75 Ω
(test)
Z
3.74 kΩ
图7-3. Differential Output Voltage (VOD) Test Circuit
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IN+
IN-
≈1.4 V
≈1 V
37.4 Ω 1%
37.4 Ω 1%
OUT+
OUT-
IN+
IN-
V
ID
V
V
OS
OC(PP)
V
OS
1 pF
V
OC
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1 ns, pulse-repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ±10 ns; RL = 100 Ω; CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.; the
measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
图7-4. Test Circuit And Definitions For The Driver Common-Mode Output Voltage
OUT+
IN+
75 Ω
1 pF
OUT-
V
ID
V
OD
V
OUT+
IN-
V
IN+
5 pF
V
IN-
V
OUT-
V
IN+
1.3 V
V
IN-
1.1 V
0.2 V
0 V
V
ID
-0.2 V
t
t
PLHD
PHLD
+V
OD
80%
0 V
Vdiff = (OUT+) - (OUT-)
20%
-V
OD
t
t
LHT
HLT
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤.25 ns, pulse-repetition rate (PRR) = 0.5
Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
图7-5. Timing Test Circuit And Waveforms
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37.4 Ω 1%
37.4 Ω 1%
OUT+
OUT-
1 V or 1.4 V
1.2 V
V
OUT+
1.2 V
EN
5 pF
V
OUT-
3 V
EN
1.5 V
0 V
V
OH
OUT
OUT
50%
1.2 V
t
t
PHZ
PZH
1.2 V
50%
V
OL
t
t
PLZ
PZL
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1 ns, pulse-repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
图7-6. Enable And Disable Time Circuit And Definitions
表7-1. Receiver Input Voltage Threshold Test
RESULTING DIFFERENTIAL RESULTING COMMON-
APPLIED VOLTAGES
OUTPUT(1)
INPUT VOLTAGE
VID
MODE INPUT VOLTAGE
VIA
VIB
VIC
1.25 V
1.15 V
4.0 V
3.9 V
0.1 V
0.0 V
1.7 V
0.7 V
4.0 V
3.0 V
1.0 V
0.0 V
1.15 V
1.25 V
3.9 V
4. 0 V
0.0 V
0.1 V
0.7 V
1.7 V
3.0 V
4.0 V
0.0 V
1.0 V
100 mV
1.2 V
1.2 V
3.95 V
3.95 V
0.05 V
0.05 V
1.2 V
1.2 V
3.5 V
3.5 V
0.5 V
0.5 V
H
L
–100 mV
100 mV
H
L
–100 mV
100 mV
H
L
–100 mV
1000 mV
–1000 mV
1000 mV
–1000 mV
1000 mV
–1000 mV
H
L
H
L
H
L
(1) H = high level, L = low level
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IN0
IN1
SEL
t
t
HOLD
SET
OUT
IN0
t
IN1
SWITCH
EN
IN0
IN1
SEL
t
t
SET
HOLD
IN1
t
IN0
OUT
SWITCH
EN
tSET and tHOLD times specify that data must be in a stable state before and after mux control switches.
图7-7. Input To Select For Both Rising And Falling Edge Setup And Hold Times
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8 Detailed Description
8.1 Overview
The SN55LVCP22A-SP is a high-speed 1-Gbps 2x2 LVDS redriving cross-point switch that can be used in mux
or demux or splitter configurations. The SN55LVCP22A-SP provides multiple signal switching options that allow
system implementation flexibility as described in 表 8-1. The SN55LVCP22A-SP incorporates wide common-
mode (0 V to 4 V) receivers, allowing for the receipt of LVDS, LVPECL, and CML signals and low-power LVDS
drivers to provide high-speed operations. The SN55LVCP22A-SP uses a fully differential data path to ensure
low-noise generation, fast switching times, low pulse width distortion, and low jitter.
8.2 Functional Block Diagram
OUT 0
OUT 1
EN 0
EN 1
SEL 1
SEL 0
IN 0
0
1
0
1
IN 1
8.3 Feature Description
8.3.1 Input Select Pins
SEL0 pin selects which differential input lane will be routed to Lane 0 driver differential output OUT0 and SEL1
pin selects which differential input lane will be routed to Lane 1 driver differential output OUT1
8.3.2 Output Enable Pins
EN0 pin is an active high enable for OUT0 driver differential output and EN1 pin is an active high enable for
OUT1 driver differential output.
8.4 Device Functional Modes
表8-1. Function Table
SEL0
SEL1
EN0
EN1
OUT0
OUT1
FUNCTION
SIGNAL FLOW
1:2 Splitter
OUT0 +
OUT0 -
1:2 Splitter
Input IN0
IN0 +
IN0 -
0
0
1
1
IN0
IN0
OUT1 +
OUT1 -
1:2 Splitter
OUT0 +
OUT0 -
1:2 Splitter
Input IN1
INꢀ +
INꢀ -
1
1
1
1
IN1
IN1
OUT1 +
OUT1 -
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SEL0
表8-1. Function Table (continued)
SEL1
EN0
EN1
OUT0
OUT1
FUNCTION
SIGNAL FLOW
Dual Repeater
OUT0 +
IN0 +
IN0 -
IN1 +
OUT0 -
OUT1 +
OUT1 -
0
1
1
1
IN0
IN1
2-lane Repeater
IN1 -
2 X 2 Crosspoint
IN0 +
IN0 -
IN1 +
OUT0 +
OUT0 -
1
0
1
1
0
1
0
1
IN1
IN0
Cross-switch
OUT1 +
OUT1 -
IN1 -
2:1 Mux
0
1
IN0
IN1
IN0 +
2:1 Mux Output
OUT0
OUTꢀ +
OUTꢀ -
IN0 -
X
High-Z
MUX
IN1 +
IN1 -
2:1 Mux
0
1
IN0
IN1
IN0 +
IN0 -
IN1 +
2:1 Mux
Output OUT1
OUTꢀ +
OUTꢀ -
X
High-Z
MUX
IN1 -
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The SN55LVCP22A-SP can support different kind of signaling at the receiver with proper termination network.
The output drivers will output LVDS differential signals.
9.2 Typical Application
9.2.1 Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
50 1
3.3 V or 5 V
3.3 V
5HGULYLQJꢀ
/9'6ꢀ
A
B
6ZLWFK
ECL
50 1
50 1
50 1
V
TT
= V -2 V
CC
V
TT
图9-1. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
9.2.1.1 Design Requirements
表9-1. Design Parameters
DESIGN PARAMETER
Single-ended termination
VTT termination voltage
EXAMPLE VALUE
50 Ω
VCC -2 V
9.2.1.2 Detailed Design Procedure
Use two 50 Ω termination resistors (as close to the input pins as possible) with termination voltage of VTT as
described in 图9-1 to receive LVPECL input signals.
9.2.2 Current-Mode Logic (CML)
3.3 V
5HGULYLQJ
50 1
/9'6
50 1
3.3 V
3.3 V
6ZLWFK
A
B
CML
50 1
50 1
3.3 V
图9-2. Current-Mode Logic (CML)
9.2.2.1 Design Requirements
表9-2. Design Parameters
DESIGN PARAMETER
Single-ended termination
EXAMPLE VALUE
50 Ω
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表9-2. Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
Termination Voltage
VCC = 3.3V
9.2.2.2 Detailed Design Procedure
Use two 50 Ω termination resistors (as close to the input pin as possible) with termination voltage of VCC as
described in 图9-2 to receive CML input signals.
9.2.3 Single-Ended (LVPECL)
3.3 V
5HGULYLQJꢀ
3.3 V
/9'6ꢀ
50 1
A
6ZLWFK
ECL
B
50 1
1.1 k1
3.3 V
1.5 k1
V
TT
= V -2 V
CC
V
TT
图9-3. Single-Ended (LVPECL)
9.2.3.1 Design Requirements
表9-3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
50 Ω
Single-ended termination for input used
VTT termination voltage
VCC - 2 V
1.1 kΩ
Unused input pull-up termination to VCC
Unused input pull-down termination to Gound
1.5 kΩ
9.2.3.2 Detailed Design Procedure
Use a 50 Ω termination resistor (as close to the input pin as possible) with termination voltage of VTT as
described in 图 9-3 to receive Single-ended LVPECL input signals. Terminate Unused input pin with 1.1 kΩ pull-
up to VCC and 1.5 kΩpull-down to ground.
9.2.4 Low-Voltage Differential Signaling (LVDS)
50 1
3.3 V or 5 V
3.3 V
5HGULYLQJꢀ
/9'6ꢀ
A
B
6ZLWFK
LVDS
100 1
50 1
图9-4. Low-Voltage Differential Signaling (LVDS)
9.2.4.1 Design Requirements
表9-4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Differential Termination
100 Ω
9.2.4.2 Detailed Design Procedure
Use a 100 Ω differential termination resistor (as close to the input pins as possible) as described in 图 9-4 to
receive LVDS input signals.
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9.2.5 Cold Sparing
VCCA
TXA
VCCA
RXA
100 Ω
GND
GND
GND
GND
ENA
VCCB
TXB
ENA
VCCB
RXB
ENB
ENB
图9-5. LVDS Cold sparing example
SN55LVCP22A-SP can be used in cold sparing application where a redundant device is on the data bus without
drawing additional power. One of the devices TXA or TXB form transmitter redundant pair can be powered down
in cold spare mode. Similarly, one for the devices RXA or RXB from receiver redundant pair can be powered
down in cold spare mode.
SN55LVCP22A-SP remains in a high impedance power-off state, when VCC is grounded at 0V (within 250mV of
GND).
表9-5. Cold sparing TX configuration example
Transmitter redundant pair
Operating state
VCCA
VCCB
TXA
TXB
TXA
TXB
Active
3.3 V
0 V
Cold spare
Cold spare
Active
0 V
3.3 V
表9-6. Cold sparing RX configuration example
Receiver redundant pair
Operating state
VCCA
VCCB
RXA
RXB
RXA
RXB
Active
3.3 V
0 V
Cold spare
Cold spare
Active
0 V
3.3 V
9.2.6 Application Curves
1 Gbps
23
2
-1 PRBS
OUTPUT 1
V
= 3.3 V
CC
|V | = 200 mV, V = 1.2 V
ID IC
Vertical Scale = 200 mV/div
OUTPUT 2
500 MHz
Horizontal Scale = 300 ps
图9-6. LVDS Output
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10 Power Supply Recommendations
There is no power supply sequence required for SN55LVCP22A-SP. It is recommended that at least a 0.1uF
decoupling capacitor is placed at the device VCC near the pin.
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11 Layout
11.1 Layout Guidelines
High performance layout practices are paramount for board layout for high speed signals to ensure good signal
integrity. Even minor imperfection can cause impedance mismatch resulting reflection. Special care is warranted
for traces, connections to device, and connectors.
11.2 Layout Example
Via to
VDD33
Plane
Via to
GND
Plane
EN0
EN1
SEL1
SEL0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD33
GND
OUT0+
IN0+
From Main
Controller
To FPGA 1
input
100 O
IN0-
OUT0-
VDD33
GND
GND
GND
0.1 uF
IN1+
OUT1+
From Backup
Controller
To FPGA 2
input
100 O
OUT1-
IN1-
图11-1. Layout Example with LVDS input signals
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12 Device and Documentation Support
12.1 Trademarks
所有商标均为其各自所有者的财产。
12.2 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.3 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962R1124201VFA
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962R1124201VF
A
LVCP22W-SP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
CFP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962R1124201VFA
W
16
1
506.98
26.16
6220
NA
Pack Materials-Page 1
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