5962R1320202VXC_技术文档

TPS7H1101A-SP

www.ti.com

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

TPS7H1101A-SP 1.5-V to 7-V Input, 3-A, Radiation-Hardened LDO Regulator

PMOS pass element configuration. It operates over

1 Features

a wide range of input voltage, from 1.5 V to 7 V

while offering excellent PSRR. The TPS7H1101A-SP

features a precise and programmable foldback current

limit implementation with a very-wide adjustment

range. To support the complex power requirements of

FPGAs, DSPs, or microcontrollers, the TPS7H1101A-

SP provides enable on and off functionality,

programmable soft start, current sharing capability,

and a Power Good open-drain output.

•

5962R13202 ⁽¹⁾

:

– Radiation hardness assurance (RHA) qualified

up to total ionizing dose (TID) 100 krad(Si)

– ELDRS-free: 100 krad(Si)

– Dose rate: 10 mrad(Si)/s

– Single event latch-up (SEL) immune to

LET = 85 MeV-cm²/mg

– SEB and SEGR immune to

LET = 85 MeV-cm²/mg

Device Information

– SET/SEFI onset threshold > 40 MeV-cm²/mg⁽²⁾

PART NUMBER⁽¹⁾

GRADE

PACKAGE

•

Specifically designed to always upset low

to avoid damage to critical downstream

component

KGD Flight Grade

RHA 100 krad(Si)

5962R1320202V9A

Flight Grade RHA

100 krad(Si)

5962R1320202VXC

TPS7H1101HKR/EM

TPS7H1101AHKR/EM

TPS7H1101SPEVM

16-Pin CFP

– SET/SEFI cross-section plot⁽²⁾

Ultra-low V_INrange: 1.5 V to 7 V

3-A maximum output current

Current share/parallel operation to provide up to

6-A output current

Stable with ceramic output capacitor

±2% accuracy over line, load, and temperature

Programmable soft start through external capacitor

Input enable across all input voltages and power-

good output for power sequencing

Ultra-low dropout LDO voltage:

62 mV at 1 A (25°C), V_OUT= 1.8 V

Low noise:

20.33 µVRMS, V_IN= 2 V, V_OUT= 1.8 V at 3 A

PSRR: over 45 dB at 1 kHz

Excellent load/line transient response

Foldback current limit

See the Design and development tab

Thermally-enhanced CFP package, 0.4° C/W R_θJC

9.60 mm × 11.00 mm

Weight: 1.55 g⁽⁴⁾

Engineering

•

Modules^{(3) (5)}

Engineering

Modules⁽³⁾

Ceramic

Evaluation Board

EVM

•

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(2) See Radiation Report (SNAA257) for details.

(3) These units are intended for engineering evaluation only.

They are processed to a noncompliant flow (that is, no

burn-in, and so forth) and are tested to a temperature

rating of 25°C only. These units are not suitable for

qualification, production, radiation testing or flight use. Parts

are not warranted for performance over the full MIL specified

temperature range of –55°C to 125°C or operating life.

(4) Weight is accurate to ±10%.

•

(5) TPS7H1101HKR/EM with device Date Code newer than 1705

is equivalent to TPS7H1101AHKR/EM using rev A silicon.

2 Applications

TPS7H1101A-SP

5 V

Power

V

•

Space satellite point of load supply for FPGAs,

microcontrollers, ASICs, and data converters

Radiation-hardened low-noise linear regulator

power supply for RF, VCOs, receivers, and

amplifiers

IN

Good

C

IN

R

CS

COMP

EN

3.3 V

C

•

V

OUT

CS

R

PCL

T

OUT

Soft

Start

Feed

Back

R

PCL

GND

•

Clean analog supply requirements

Command and data handling (C&DH)

Optical imaging payload

Radar imaging payload

Satellite electrical power system (EPS)

R

B

C

SS

Typical Application Circuit

3 Description

The TPS7H1101A-SP is an improved version of

the TPS7H1101-SP allowing the use of the enable

feature across the entire input voltage range. It is a

radiation-hardened LDO linear regulator that uses a

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Product Folder Links: TPS7H1101A-SP

Submit Document Feedback

1

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................7

6.6 Typical Characteristics..............................................10

7 Detailed Description......................................................12

7.1 Overview...................................................................12

7.2 Functional Block Diagram.........................................12

7.3 Feature Description...................................................13

7.4 Device Functional Modes..........................................13

8 Application and Implementation..................................14

8.1 Application Information............................................. 14

8.2 Typical Application.................................................... 15

9 Power Supply Recommendations................................26

10 Layout...........................................................................26

10.1 Layout Guidelines................................................... 26

10.2 Layout Example...................................................... 26

11 Device and Documentation Support..........................27

11.1 Device Support........................................................27

11.2 Documentation Support.......................................... 27

11.3 Receiving Notification of Documentation Updates..27

11.4 Support Resources................................................. 27

11.5 Trademarks............................................................. 27

11.6 Electrostatic Discharge Caution..............................27

11.7 Glossary..................................................................27

12 Mechanical, Packaging, and Orderable

Information.................................................................... 27

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (June 2020) to Revision C (April 2021)

Page

•

Updated the numbering format for tables, figures, and cross-references throughout the document..................1

Added TPS7H1101AHKR/EM to Device Information table.................................................................................1

Changes from Revision A (August 2017) to Revision B (June 2020)

Page

•

Added package weight to Device Information table............................................................................................1

Added note to Pin Functions table for thermal pad and lid.................................................................................3

Added updated thermal metrics in Thermal Information table............................................................................6

Changed and relaxed V_CSoperating range........................................................................................................7

Added table note for V_CS................................................................................................................................... 7

Changed CSR ratio. Added limits by temperature .............................................................................................7

Added clarification for T_EN................................................................................................................................. 7

Changed Overview section for improved clarity .............................................................................................. 12

Changed and clarifed V_REFvoltage in C_SScalculation .................................................................................... 13

Changed Stability applications section............................................................................................................. 14

Changed and corrected PCL section description............................................................................................. 16

Changed and clarified High-Side Current Sense section description ..............................................................17

Changed and clarified Current Foldback section description........................................................................... 19

Changed and improved Layout Example section............................................................................................. 26

Changes from Revision * (April 2017) to Revision A (August 2017)

Page

Added Bare Die Information table.......................................................................................................................3

Added Bond Pad Coordinates in Microns table..................................................................................................3

•

2

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

5 Pin Configuration and Functions

SS

EN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

FB

COMP

VOUT

CS

VIN

PCL

GND

Thermal

Pad

PG/OC

Not to scale

Figure 5-1. HKR Package

16-Pin CFP

Bottom View

Table 5-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

Soft-start terminal. Connecting an external capacitor slows down the output voltage ramp rate after enable

event.

SS

1

I/O

I

Enable terminal. Driving this terminal to logic high enables the device; driving the terminal to logic low

disables the device.

EN

2

3

4

5

6

V_IN

I

Unregulated supply voltage. TI recommends to connect an input capacitor as a good analog circuit practice.

Programmable current limit. A resistor to GND sets the overcurrent limit activation point.

The range of resistor that can be used on the PCL terminal to GND is 8.2 kΩ to 160 kΩ.

PCL

7

8

I/O

—

GND

Ground/thermal pad.^{(1) (2)}

Power Good terminal. PG is an open-drain output to indicate the output voltage reaches 90% of target. PG

terminal is also used as indicator when an overcurrent condition is activated. PG pin should have a pull-up

resistor to the V_OUTpin.

PG/OC

CS

9

O

Current sense terminal. Resistor connected from CS to V_IN. CS terminal indicates voltage proportional to

output current.

CS terminal low: Foldback current limit disabled.

10

I/O

CS terminal high: Foldback current limit enabled.

11

12

13

14

15

16

V_OUT

O

Regulated output.

COMP

FB

I/O

I

Internal compensation point for error amplifier.

The output voltage feedback input through voltage dividers. See Section 8.2.1.1.

(1) Thermal pad must be connected to GND.

(2) Thermal pad and package lid are internally connected to GND.

Submit Document Feedback

3

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

Table 5-2. Bare Die Information

BACKSIDE

POTENTIAL

BOND PAD

METALLIZATION COMPOSITION

DIE THICKNESS

BACKSIDE FINISH

BOND PAD THICKNESS

15 mils

Silicon with backgrind

Ground

AlCu

30 kA

All dimensions are in microns.

4

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

Table 5-3. Bond Pad Coordinates in Microns

DESCRIPTION

PAD NUMBER

X MIN

Y MIN

X MAX

287.19

Y MAX

4224.105

3670.65

3198.645

2926.305

2731.005

2458.665

2263.365

1991.025

1795.725

837.585

496.755

287.235

1523.385

556.92

SS

EN

1

109.89

4046.805

3493.35

3021.345

2749.005

2553.705

2281.365

2086.065

1813.725

1618.425

660.285

319.455

109.935

1346.085

379.62

2

109.89

287.19

VIN

3

1359.99

109.89

1537.29

287.19

VIN

4

VIN

5

VIN

6

VIN

7

VIN

8

VIN

9

PCL

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GND

VIN

109.89

287.19

392.58

569.88

1359.99

2898.945

2829.105

2898.945

1537.29

3076.245

3006.405

3076.245

PG/OC

CS

724.32

901.62

VOUT

COMP

FB

1384.695

1579.815

1852.335

2047.455

2319.975

2515.095

2787.615

2982.735

3519.72

3956.535

1561.995

1757.115

2029.635

2224.755

2497.275

2692.395

2964.915

3160.035

3697.02

4133.835

Submit Document Feedback

5

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

0.001

–55

MAX

7.5

UNIT

V_IN, PG

Input voltage

V

FB, COMP, PCL, CS, EN

V_IN+ 0.3

7.5

Output voltage

V_OUT, SS

V

PG terminal sink current

5

mA

°C

Maximum operating junction temperature, T_J

Storage temperature, T_stg

150

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

±1000

V_(ESD)Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

T_J

Operating junction temperature

–55

125

°C

6.4 Thermal Information

TPS7H1101A-SP

THERMAL METRIC^{(1) (2) (3)}

HKR (CFP)

16 PINS

24.3

UNIT

R_{θ JA}

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_{θ JC(top)}

R_{θ JB}

5.5

8.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.3

ψ_JB

8.1

R_θJC(bot)

0.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Do not allow package body temperature to exceed 265°C at any time or permanent damage may result.

(3) Maximum power dissipation may be limited by overcurrent protection.

6

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

6.5 Electrical Characteristics

1.5 V ≤ V_IN≤ 7 V, V_OUT(target)= V_IN– 0.35 V, I_OUT= 10 mA, V_EN= 1.1 V, C_OUT= 22 µF, PG terminal pulled up to V_INwith

50 kΩ, over operating temperature range (T_J= –55°C to 125°C), unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Input voltage range

1.5

7

V

V_FB

V_OUT

Feedback terminal voltage⁽¹⁾0 A ≤ I_OUT≤ 3 A, 1.5 V ≤ V_IN≤ 7 V

0.594

0.8

0.605

0.616

V_IN

Output voltage range

0 A ≤ I_OUT≤ 3 A, 1.5 V ≤ V_IN≤ 7 V,

Output voltage accuracy⁽¹⁾

–2%

2%

V_OUT= 0.8 V, 1.2 V, 1.8 V, 6.65 V

ΔV_OUT%/

ΔV_IN

Line regulation

Load regulation

1.5 V ≤ V_IN≤ 7 V

–0.07

0.01

0.08

0.5

0.07

%/V

%/A

ΔV_OUT%/

ΔI_OUT

0.8 V ≤ V_OUT≤ 6.65 V, 0 ≤ I_Load≤ 3 A

1.5 V ≤ V_IN≤ 7 V, V_OUT= 0.8 V, 1.2 V, 1.8 V,

I_OUT= 10 mA, T_J= –55°C⁽²⁾

3

0.6

1

1.5 V ≤ V_IN≤ 7 V, V_OUT= 0.8 V, 1.2 V, 1.8 V,

I_OUT= 10 mA, T_J= 25°C⁽²⁾

ΔV_OUT

DC input line regulation

0.2

mV

1.5 V ≤ V_IN≤ 7 V, V_OUT= 0.8 V, 1.2 V, 1.8 V,

I_OUT= 10 mA, T_J= 125°C⁽²⁾

0.2

Submit Document Feedback

7

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

6.5 Electrical Characteristics (continued)

1.5 V ≤ V_IN≤ 7 V, V_OUT(target)= V_IN– 0.35 V, I_OUT= 10 mA, V_EN= 1.1 V, C_OUT= 22 µF, PG terminal pulled up to V_INwith

50 kΩ, over operating temperature range (T_J= –55°C to 125°C), unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

0.4

0.6

0.8

1.3

1.6

1.1

1.9

2.5

0.3

0.5

0.6

0.8

1.1

1.5

1

MAX

UNIT

V_OUT= 0.8 V, 0 ≤ I_Load≤ 1 A, T_J= –55°C⁽²⁾

V_OUT= 0.8 V, 0 ≤ I_Load≤ 1 A, T_J= 25°C⁽²⁾

V_OUT= 0.8 V, 0 ≤ I_Load≤ 1 A, T_J= 125°C⁽²⁾

V_OUT= 0.8 V, 0 ≤ I_Load≤ 2 A, T_J= –55°C⁽²⁾

V_OUT= 0.8 V, 0 ≤ I_Load≤ 2 A, T_J= 25°C⁽²⁾

V_OUT= 0.8 V, 0 ≤ I_Load≤ 2 A, T_J= 125°C⁽²⁾

V_OUT= 0.8 V, 0 ≤ I_Load≤ 3 A, T_J= –55°C⁽²⁾

V_OUT= 0.8 V, 0 ≤ I_Load≤ 3 A, T_J= 25°C⁽²⁾

V_OUT= 0.8 V, 0 ≤ I_Load≤ 3 A, T_J= 125°C⁽²⁾

V_OUT= 1.2 V, 0 ≤ I_Load≤ 1 A, T_J= –55°C⁽²⁾

V_OUT= 1.2 V, 0 ≤ I_Load≤ 1 A, T_J= 25°C⁽²⁾

V_OUT= 1.2 V, 0 ≤ I_Load≤ 1 A, T_J= 125°C⁽²⁾

V_OUT= 1.2 V, 0 ≤ I_Load≤ 2 A, T_J= –55°C⁽²⁾

V_OUT= 1.2 V, 0 ≤ I_Load≤ 2 A, T_J= 25°C⁽²⁾

V_OUT= 1.2 V, 0 ≤ I_Load≤ 2 A, T_J= 125°C⁽²⁾

V_OUT= 1.2 V, 0 ≤ I_Load≤ 3 A, T_J= –55°C⁽²⁾

V_OUT= 1.2 V, 0 ≤ I_Load≤ 3 A, T_J= 25°C⁽²⁾

V_OUT= 1.2 V, 0 ≤ I_Load≤ 3 A, T_J= 125°C⁽²⁾

V_OUT= 1.8 V, 0 ≤ I_Load≤ 1 A, T_J= –55°C⁽²⁾

V_OUT= 1.8 V, 0 ≤ I_Load≤ 1 A, T_J= 25°C⁽²⁾

V_OUT= 1.8 V, 0 ≤ I_Load≤ 1 A, T_J= 125°C⁽²⁾

V_OUT= 1.8 V, 0 ≤ I_Load≤ 2 A, T_J= –55°C⁽²⁾

V_OUT= 1.8 V, 0 ≤ I_Load≤ 2 A, T_J= 25°C⁽²⁾

V_OUT= 1.8 V, 0 ≤ I_Load≤ 2 A, T_J= 125°C⁽²⁾

V_OUT= 1.8 V, 0 ≤ I_Load≤ 3 A, T_J= –55°C⁽²⁾

V_OUT= 1.8 V, 0 ≤ I_Load≤ 3 A, T_J= 25°C⁽²⁾

V_OUT= 1.8 V, 0 ≤ I_Load≤ 3 A, T_J= 125°C⁽²⁾

V_OUT= 6.65 V, 0 ≤ I_Load≤ 1 A, T_J= –55°C⁽²⁾

V_OUT= 6.65 V, 0 ≤ I_Load≤ 1 A, T_J= 25°C⁽²⁾

V_OUT= 6.65 V, 0 ≤ I_Load≤ 1 A, T_J= 125°C⁽²⁾

V_OUT= 6.65 V, 0 ≤ I_Load≤ 2 A, T_J= –55°C⁽²⁾

V_OUT= 6.65 V, 0 ≤ I_Load≤ 2 A, T_J= 25°C⁽²⁾

V_OUT= 6.65 V, 0 ≤ I_Load≤ 2 A, T_J= 125°C⁽²⁾

V_OUT= 6.65 V, 0 ≤ I_Load≤ 3 A, T_J= –55°C⁽²⁾

V_OUT= 6.65 V, 0 ≤ I_Load≤ 3 A, T_J= 25°C⁽²⁾

V_OUT= 6.65 V, 0 ≤ I_Load≤ 3 A, T_J= 125°C⁽²⁾

I_OUT= 3 A, V_OUT= 1.3 V, V_IN= V_OUT+ V_DO

1

1.1

1.3

1.8

2.4

1.9

2.6

3.4

1.2

1.3

1.6

2.1

1.7

2.4

3.5

0.9

1.2

2.4

1.4

1.9

3.9

2.1

2.5

2.9

2.6

3.5

5.9

4.7

8

1.1

2.2

0.1

0.3

0.4

1.4

0.7

0.6

2.5

1.2

1.5

0.4

2.8

3.5

1.1

5.8

5.6

3.7

13

ΔV_O

DC output load regulation⁽³⁾

mV

9.3

8

25

V_DO

Dropout voltage⁽³⁾

210

335

mV

mA

V_IN= 1.5 V, V_OUT= 1.2 V,

PCL resistance = 47 kΩ

500

200

0

750

3500⁽⁴⁾

V_IN

Programmable output current

limit range

I_CL

V_IN= 1.5 V, V_OUT= 1.2 V,

PCL resistance varies

Operating voltage range at

CS (see Section 7)⁽⁵⁾

V_CS

V

8

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

6.5 Electrical Characteristics (continued)

1.5 V ≤ V_IN≤ 7 V, V_OUT(target)= V_IN– 0.35 V, I_OUT= 10 mA, V_EN= 1.1 V, C_OUT= 22 µF, PG terminal pulled up to V_INwith

50 kΩ, over operating temperature range (T_J= –55°C to 125°C), unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_LOAD/ I_CS, V_IN= 2.3 V, V_OUT= 1.9 V, T_J=

–55°C, I_LOAD≥ 500 mA

45000

55500

65000

_LOAD/ I_CS, V_IN= 2.3 V, V_OUT= 1.9 V, T_J=

25°C, I_LOAD≥ 500 mA

CSR

Current sense ratio

45000

52000

51000

59000

56000

A/A

_LOAD/ I_CS, V_IN= 2.3 V, V_OUT= 1.9 V, T_J=

125°C, I_LOAD≥ 500 mA

I_GND

I_Q

GND terminal current

V_IN= 1.5 V, V_OUT= 1.2 V, I_OUT= 2 A

V_IN= V_OUT+ 0.5 V, I_OUT= 0 A

10

7

16

10

mA

Quiescent current (no load)

1.5 V ≤ V_IN≤ 7 V, pre and post 100 krad(Si),

T_J= 25°C⁽⁶⁾

I_SHDN

Shutdown current

26

230

µA

I_SNS, I_FB

I_EN

FB/SNS terminal current

EN terminal input current

V_IN= 7 V, V_OUT= 6.65 V

1

5

nA

V_IN= 7 V, V_EN= 7 V, V_OUT= 6.65 V

20

150

EN terminal input low

(disable)

V_ILEN

1.5 V < V_IN< 7 V

0.55

V

EN terminal input high

(enable)

V_IHEN

1.5 V < V_IN< 7 V

V_IN– 0.7

Enable terminal propagation

delay

Eprop Dly

T_EN

V_IN= 2.2 V, EN rise to I_OUTrise

650

1.4

1000

1.6

µs

ms

Enable terminal turn-on delay V_IN= 2.2 V, V_OUT= 1.8 V, I_LOAD= 1 A,

(delay to PG assertion)

C_OUT= 220 µF, C_SS= 2 nF

No load, 0.8 V ≤ V_OUT≤ 6.65 V

1.5 V ≤ V_IN≤ 7 V

V_THPG

PG threshold

86%

90%

2%

120

0.2

0.5

2.5

5

V_THPGHYS

V_{OL PG}

PG hysteresis

PG terminal output low

I_PG= 0 mA to –1 mA

300

1.5

2.5

3.5

10

mV

µA

V_OUT> V_THPG, V_PG= 1.2 V

V_OUT> V_THPG, V_PG= 7 V

V_IN= 1.5 V to 7 V

I_LKGPG

PG terminal leakage current

I_SS

SS terminal charge current

SS terminal disable current

µA

I_SSdisb

V_IN= 1.5 V to 7 V

SS terminal voltage (device

enabled)⁽⁷⁾

V_SS

V_IN= 1.5 V to 7 V

1.232

0.4

V

SS terminal low-level input

voltage to disable device

V_SSdisb

1 kHz

48

25

V_IN= 2.5 V, V_OUT= 1.8 V,

C_OUT= 220 µF

PSRR

Power-supply rejection ratio

Output noise voltage

dB

100 kHz

BW = 10 Hz to 100 kHz,

V_N

20.33

185

µV_RMS

°C

I_OUT= 3 A, V_IN= 2 V, V_OUT= 1.8 V

Thermal shutdown

temperature

TSD

(1) The output voltage accuracy of condition at I_OUT= 2 A and I_OUT= 3 A is specified by characterization, but not production tested.

(2) Line and load regulations done under pulse condition for t < 10 ms.

(3) The parameter is specified to the limit in characterization, but not production tested.

(4) The maximum limit of the I_CLparameter is specified to the limit in characterization, but not production tested.

(5) To insure foldback is enabled, V_CSmust be > 0.9 · V_FB

.

(6) This maximum limit applies to SMD 5962R13202 post 100-krad(Si) test at 25°C.

(7) Any external pullup voltage should not exceed 1.188 V.

Submit Document Feedback

9

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

6.6 Typical Characteristics

0.608

0.607

0.606

0.605

10

9

8

V_IN= 7 V

7

V_IN= 1.5 V

0.604

V_IN= 1.5 V

6

0.603

V_IN= 7 V

5

0.602

-55

-35

-15

5

25

45

65

85

105 125

5

25

45

65

85

105 125

œ55 œ35 œ15

Junction Temperature (°C)

C014

Figure 6-1. Feedback Voltage vs Temperature

Figure 6-2. Quiescent Current vs Temperature

320

280

240

200

160

120

13

12

11

10

9

Load = 2 A

No Load

8

7

6

5

25

45

65

85

105 125

œ55 œ35 œ15

-55

-35

-15

5

25

45

65

85

105 125

Junction Temperature (°C)

C015

V_OUT= 1.8 V

Load = 3 A

Figure 6-4. Dropout Voltage vs Temperature

Figure 6-3. Ground Current vs Temperature

100

80

60

40

20

0

100

95

V_IN= 7 V

90

V_IN= 1.5 V

85

80

5

25

45

65

85

105 125

5

25

45

65

85

105 125

-55

-35

-15

-55

-35

-15

Junction Temperature (°C)

C017

C018

Figure 6-5. Shutdown Current vs Temperature

Figure 6-6. PG Threshold vs Temperature

10

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

6.6 Typical Characteristics (continued)

100

No load

1A

2A

3A

80

60

40

20

0

10

100

1000

10000

100000

Frequency (Hz)

V_IN= 2.5 V

V_OUT= 1.8 V

Figure 6-7. Power Supply Ripple Rejection vs Frequency

Submit Document Feedback

11

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

7 Detailed Description

7.1 Overview

The TPS7H1101A-SP is 3-A, 1.5-V to 7-V LDO linear regulator that uses PMOS pass element configuration.

It uses TI’s proprietary process to achieve low noise, high PSRR combined with high-thermal performance in a

16-pin ceramic flatpack package (HKR).

A number of features are incorporated in the design to provide high reliability and system flexibility. Current

foldback, current limit, and thermal protection are incorporated in the design to make it viable for space

environments.

The device also has a current sense monitoring feature. A resistor connected from the current sense (CS)

terminal to VIN indicates voltage proportional to the output current. Section 8.2.1.3 provides a detailed

description of this feature. When CS is pulled high to voltage greater than 90% Vref (0.544 V), foldback current

limit is enabled. Pulling CS below 0.544 V disables the foldback current limit.

A resistor connected from the programmable current limit (PCL) terminal to ground sets the overcurrent limit

activation point. When overcurrent limit activation point is reached, it results in the LDO going into current

foldback mode. Output current is reduced to approximately 50% of the current limit set point. Section 8.2.1.2

provides a detailed description of this feature.

TPS7H1101A-SP incorporates thermal protection, which disables the output when the junction temperature rises

to approximately 185°C, allowing the device to cool. Cycling limits the dissipation of the regulator, protecting it

from catastrophic damage as a result of overheating.

To provide system flexibility for demanding current needs, the LDO can be configured in parallel operation as

indicated in Figure 8-12. Section 8.2.1.6 provides detailed parallel operation information.

An enable feature is incorporated in the design allowing the user to enable or disable the LDO. Power

Good (PG), is an open-drain connection, indicating status of the output voltage regulation. These provide the

customers system flexibility in monitoring and controlling the LDO operation.

7.2 Functional Block Diagram

CS

V_IN

1.2 V

2 mA

R_TOP

EN

I_SS

OCP

PCL

R_BOT

Thermal

Protection

V_REF

1.1*V_REF

PG

0.9*V_REF

12

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

7.3 Feature Description

7.3.1 Soft Start

Connecting a capacitor (C_SS) from the SS terminal to GND slows down the output voltage ramp rate. The

soft-start capacitor charges up to 1.2 V, with a threshold of V_FB.

t_SS· I_SS

C_SS=

V_FB

(1)

where

•

t_ss= soft-start time

I_ss= 2.5 µA

V_FB= V_REF= 0.605 V

7.3.2 Power Good (PG)

Power Good terminal (9) is an open-drain connection and can be used to sequence multiple LDOs. Figure

7-1 shows typical connection. The PG terminal will be pulled low until the output voltage reaches 90% of its

maximum level. At that point, the PG pin will be pulled up. Since the PG pin is open drain, it can be pulled up to

any voltage as long as it does not exceed the absolute max of 7.5 V listed in Section 6.5.

TPS7H1101A-SP

PG

EN

SS

VIN

Figure 7-1. Sequencing LDOs With Power Good

Note

For PSpice models, WEBENCH, and reference design, see the Design & development tab of the

product folder.

1. PSpice transient model (switching, transient, and stability simulations)

2. PSpice Worst Case Analysis (WCA) model (radiation and aging stability – Bode plot)

7.4 Device Functional Modes

7.4.1 Enable/Disable

For V_INfrom 1.5 V to 7 V, TPS7H1101A-SP can be disabled by pulling the enable terminal to logic low at a

minimum of 0.7 V. Enable cannot exceed V_INby more than 0.3 V, and in most cases, the enable terminal is

connected to V_IN.

Submit Document Feedback

13

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TPS7H1101A-SP LDO linear regulator is targeted space environment applications. This regulator has

various features such as low dropout, soft start, output current foldback, high-side current sensing (where

sensing voltage at CS pin provides voltage proportional to output current), and current sharing.

8.1.1 Stability

Bode plots are a standard approach in assessing stability. This approach requires a single feedback path

where an AC signal is injected across a resistor (typically 50 Ω) and measurements are taken on either side

of the resistor as shown in Figure 8-1. From this measurement, loop gain and phase plots can be generated.

Crossover frequency, ƒ_C, is defined as the frequency where the magnitude of the loop gain is unity and phase

margin is evaluated at the crossover frequency ƒ_C.

Signal

injection

TPS7H1101A-SP

IN

OUT

50Ω

+

R_ESR

VIN

R_ESR

C_COMP

œ

R_LOAD

COMP

FB

R_T

gm

C_OUT

C_IN

R_B

0.6V V_REF

Figure 8-1. Conventional Bode Plot With Simplified Feedback Loops

However, it is important the AC signal is injected as shown in Figure 8-1. This injection point ensures that the

feedback signal goes through both the outer loop (consisting of the top feedback resistor, R_T) and the inner loop

(consisting of the compensation capacitor, C_COMP). If the only the outer loop is measured, the resulting crossover

frequency will be lower which would indicate a poorer transient response than reality. Therefore, it is best to

inject the measurement signal at a point where it goes through both loops. If this is not possible, the two loops

may be measured independently and added using the superposition principle.

Furthermore, the stability of the device can be qualitatively validated by applying a step load to the output and

observing the response. The SPICE models for the device can be found on the TPS7H1101A-SP product page.

To simulate impedance measurements, the transient model should be used.

14

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

8.2 Typical Application

TPS7H1101A-SP

Power

5 V

V

IN

Good

C

IN

R

CS

COMP

EN

3.3 V

V

OUT

CS

R

PCL

C

T

OUT

Soft

Start

Feed

Back

R

PCL

GND

R

B

C

SS

Figure 8-2. Typical Application Circuit

Submit Document Feedback

15

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

8.2.1 Detailed Design Procedure

8.2.1.1 Adjustable Output Voltage (Feedback Circuit)

The output voltage of the TPS7H1101A-SP can be set to a user-programmable level between 0.8 V and 6.65

V. Achieve this by using a resistor divider connected between V_OUT, FB, and GND terminals. R_TOPconnected

between V_OUTand V_FB, and R_BOTTOMconnected between V_FBand GND.

Use Equation 2 to determine V_OUT

.

(R_TOP+ R_BOTTOM) · V_FB

R_BOTTOM

V_OUT

=

(2)

where

V_FB= 0.605 V

•

Table 8-1. Example Resistor Values for Typical

Voltages

Standard 1% Resistors

Standard 0.1% Resistors

V_OUT

R_TOP

R_BOTTOM

33.2 kΩ

21 kΩ

R_TOP

R_BOTTOM

33.2 kΩ

19.3 kΩ

12 kΩ

0.8 V

1 V

10.7 kΩ

13.7 kΩ

11.3 kΩ

15.8 kΩ

23.2 kΩ

10.7 kΩ

51.1 kΩ

13.3 kΩ

11.5 kΩ

17.4 kΩ

90.9 kΩ

26.7 kΩ

11.3 kΩ

39.2 kΩ

10.7 kΩ

12.6 kΩ

11.8 kΩ

18.2 kΩ

32 kΩ

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

4 V

11.5 kΩ

10.7 kΩ

11.8 kΩ

3.4 kΩ

12.3 kΩ

16.2 kΩ

12.1 kΩ

2.29 kΩ

5.56 kΩ

2.23 kΩ

11.1 kΩ

1.2 kΩ

37.9 kΩ

10.2 kΩ

31.2 kΩ

16.2 kΩ

89.8 kΩ

10.7 kΩ

15.2 kΩ

22.1 kΩ

13.8 kΩ

11.5 kΩ

2.37 kΩ

1.58 kΩ

2.15 kΩ

10.2 kΩ

2.74 kΩ

1.15 kΩ

3.92 kΩ

5 V

5.5 V

6 V

6.5 V

6.6 V

6.7 V

1.56 kΩ

2.23 kΩ

1.37 kΩ

8.2.1.2 PCL

PCL resistor, R_PCL, sets the overcurrent limit activation point and can be calculated per Equation 3.

R_PCL= (CSR × V_REF) / (I_CL– 0.0403)

where

(3)

•

V_REF= 0.605 V

I_CL= Programmable current limit (A)

Current sense ratio (CSR) is the ratio of output load current to I_CS; typical value of the CSR is 52000

Offset value 0.0403 is a fixed offset derived from internal keep-alive biasing

Figure 8-3 shows the output load current (I_LOAD) versus PCL terminal current (I_PCL) varied with minimum and

maximum range of CSR values by temperature. The R_PCLresistor should be chosen to set the worst case I_LOAD

across system normal operating load and temperature range without reaching overcurrent activation point of I_PCL

· R_PCL≥ V_REF

.

Additionally, a suitable resistor R_CSmust be chosen to ensure the CS terminal is within its operating range of 0.3

V to V_INand V_CSneeds to be greater than 0.9 · V_REF(0.544 V) to insure foldback remains enabled when current

activation point is triggered.

16

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

The maximum PCL is 3.5 A. The range of resistor that can be used on the PCL terminal to GND is 8.2 kΩ to 160

kΩ. It is not recommended to use overcurrent limit activation thresholds of less than 500 mA due to internal bias

offset currents representing a larger percentage of total I_PCLcurrent and therefore additional error.

I_LOADVs I_PCLacross CSR range

6

Min CSR: I_LOAD= 45000 * I_PCL+0.0403

25c Nom CSR: I_LOAD= 52000 * I_PCL+0.0403

125c Max CSR: I_LOAD= 56000 * I_PCL+0.0403

5

-55c Max CSR: I_LOAD= 65000 * I_PCL+0.0403

4

3

2

1

0

0x10⁰

10x10^-620x10^-630x10^-640x10^-650x10^-660x10^-670x10^-680x10^-6

I_PCL(A)

CSR_

Figure 8-3. I_LOAD(A) vs I_PCL(A)

8.2.1.3 High-Side Current Sense

Figure 8-4 shows the cascode NMOS current mirror. V_CSmust be ≥ 0.3 V for proper biasing. Additionally V_CS

must be greater than 0.9 · V_REF(0.544 V) if foldback current limiting is intended to be enabled. The following

example shows the typical calculation of R_CS

.

I_LOAD+ I_offset

I_CS

=

CSR

(4)

(5)

V_IN- V_CS

¾¾

I_CS

R_CS=

where

•

I_LOADis the output load current

CSR is the current sense ratio

I_offsetis internal keep-alive bias current times CSR

I_offset= 5 µA · CSR

When V_IN= 2.3 V, select V_CS= 2.05 V, I_LOAD= 3 A, CSR = 52000, and I_offset= 0.26 A, then I_CS= 62.69 µA and

R_CS= 3.99 kΩ.

Submit Document Feedback

17

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

Vin

Rcs

Iout

Ics

Vcs

Figure 8-4. Cascode NMOS Current Mirror

For TPS7H1101A-SP, Figure 8-5 shows a typical curve V_CSvs I_OUTfor V_IN= 2.28 V and R_CS= 3.65 kΩ. A

resistor connected from the CS terminal to V_INindicates voltage proportional to the output current.

Monitoring current in the CS terminal (I_CSvs I_LOAD) indicates the current sense ratio between the main

PMOSFET and the current sense MOSFET as shown in Figure 8-6. Additionally Figure 8-6 shows the linearity

of the CSR ratio across V_CSpin voltage range of 0.3 V to V_IN. V_CSmust be ≥ 0.3-V minimum to keep circuit

properly biased.

Figure 8-7 shows I_LOADvs I_CSacross the full range of CSR values.

3.5

2.35

I_CS(uA) vs I_LOADat VCS = 0.3V

I_CS(uA) vs I_LOADat VCS = 2.3V

I_CS(uA) vs I_LOADat VCS = 5V

3

2.30

2.25

2.5

2.20

2

2.15

1.5

2.10

1

2.05

0.5

2.00

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0

10

20

30

40

50

60

70

80

I_CS(uA)

Load Current (A)

VCS_

C003

V_IN= 2.3 V

V_OUT= 1.8 V

y = –0.078x + 2.2853

V_IN= 2.3 V

V_OUT= 1.8 V

Figure 8-5. V_CS(V) vs I _LOAD(A)

Figure 8-6. I_OUT(A) vs I_CS(A)

18

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

I_LOADVs I_CSacross CSR range

6

5

4

3

2

1

Min CSR: I_LOAD= 45000(I_CS- 5uA)

25c Nom CSR: I_LOAD= 52000(I_CS- 5uA)

-55c Max CSR: I_LOAD= 65000(I_CS- 5uA)

125c Max CSR: I_LOAD= 56000(I_CS- 5uA)

0

0x10⁰

10x10^-620x10^-630x10^-640x10^-650x10^-660x10^-670x10^-680x10^-6

I_CS(A)

CSR_

Figure 8-7. I_OUT(A) vs I_CS(A)

8.2.1.4 Current Foldback

1. The TPS7H1101A-SP has a current foldback feature which can be enabled when the CS terminal is greater

than 0.9 · V_REF(0.544 V). Pulling CS below this threshold disables the foldback current limit. If the foldback

current limit is disabled, then the LDO will begin regulating again as soon as the current falls below the

clamp threshold.

2. With foldback current limit enabled, when current limit trip point is activated,

a. Output voltage drops low, and

b. Output current folds back to approximately 50% of the current limit trip point.

This results in minimizing the power loss under fault conditions. Monitoring the voltage at the CS terminal

indicates voltage proportional to the output current. It is important to note that the current sense voltage

range on CS pin must be designed to stay above the 0.9 · V_REFthreshold to insure foldback is not

inadvertently disabled at high currents.

Submit Document Feedback

19

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

8.2.1.5 Transient Response

Figure 8-8, Figure 8-9, and Figure 8-10 indicate the transient response behavior of the LDO for 50% step load

change.

Channel 1: Input voltage

Channel 3: Step load in current

Channel 4: Output voltage overshoot/undershoot

Figure 8-9. Expanded View Overshoot

Figure 8-8. Load Transient Response: Step Load

0.1 to 1.6 A, V_IN= 2.3 V, V_OUT= 1.8 V

Figure 8-10. Expanded View Undershoot

20

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

8.2.1.6 Current Sharing

For demanding load requirements, multiple LDOs can be paralleled as indicated in Figure 8-12. In parallel mode,

the CS terminal of LDO1 must be connected to the PCL terminal of LDO2 via a series resistor, R_CL, and CS

terminal of LDO2 must be connected to PCL terminal of LDO1 via series resistor, R_CL. The typical value of R_CL

in parallel operation is 3.75 kΩ for current limit > 6 A. In parallel configuration, R_CL(resistor from PCL to GND)

and R_CS(resistor from CS terminal to V_IN) must be left open (unpopulated). The R_CLvalue must be selected so

that the operating condition of the CS terminal is maintained, as specified in Section 6.5. V_CSmust be greater

than 0.3 V to insure proper current sense operation. The current from PCL through RCL of LDO1 is determined

by the output load current of LDO2 divided by the CSR. Hence, the voltage at CS terminal of the LDO1 is 0.605

V – ((output load current of LDO2 + 0.2458) / CSR × R_CL).

Alternately, it can also provide twice the output current to meet system needs. When using two LDOs in parallel

operation for higher output load current, use POL TPS50601-SP as an input source.

65.00

LDO1

LDO2

60.00

55.00

50.00

45.00

40.00

35.00

0

1

2

3

4

5

6

Output Current

Figure 8-11. LDO Current Share

Submit Document Feedback

21

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

R_PG

Supply

Ccomp

PG

V_IN

Comp

V_OUT

LDO1

SS

FB

PCL

CS

R_TOP

R_LOAD

C_OUT

C_X

R_BOT

R_CL

Optional

R_CL

Supply

Ccomp

CS

PCL

V_IN

SS

FB

Comp

V_OUT

LDO1

PG

R_PG

C_SS

Figure 8-12. Block Diagram (Parallel Operation)

22

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

8.2.1.7 Compensation

Figure 8-13 shows a generic block diagram for TPS7H1101A-SP LDO with external compensation components.

LDO incorporates nested loops, thus providing the high gain necessary to meet design performance.

Q1

C_COMP

C_FF

R_TOP

R_ESR

+

Buffer

-

R_INESR

+

V_OUT

-

R_L

E/A

V_IN

+

C_O

R_BOT

C_IN

V_REF= 0.605 V

C_X

-

Figure 8-13. TPS7H1101A-SP Compensation

Resistor divider composed of R_topand R_bottomdetermine the output voltage set points as indicated by Equation

2.

Output capacitor C_OUTintroduces a pole and a zero as shown in the following.

1

F_{p_co}

=

2·p·C_o·R_L

(6)

(7)

1

F_{z_co}

=

2·p·C_o·C_esr

The TPS7H1101A-SP was designed so that the ESR of the output capacitor will not have a strong influence on

the response of the LDO. However, an optional capacitor, C_x, can be added in parallel with the bottom feedback

resistor to introduce a pole to cancel F_{z_co}. Equation 8 shows how to calculate the location of the pole introduced

by C_x. To cancel the zero directly, F_pshould be equal to F_{z_co}

.

1

F_p=

2·p·C_x·R_bottom

(8)

C_xis calculated to be 1000 pF for C_o= 220 µF, C_esr= 45 mΩ, and R_bottom= 10 kΩ.

Figure 8-13 also includes a place holder for a feed forward capacitance C_ff. Use of feed forward compensation

can be more advantageous than use of C_x. Please reference application note Pros and Cons of Using a

Feedforward Capacitor with a Low-Dropout Regulator for additional information on usage of C_FF.

Internal compensation in the LDO cancels the output capacitor pole introduced by C_OUTand R_L.

C_compintroduces a dominant pole at low frequency. TI recommends that a C_compvalue of 10 nF.

8.2.1.8 Output Noise

Output noise is measured using an HP3495A. Figure 8-14 and Figure 8-15 show noise of the TPS7H1101A-SP

in µV/√ Hz vs frequency.

Submit Document Feedback

23

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

10

1

0.1

0.01

10

0.01

10

100

1,000

10,000

100,000

100

1000

10000

100000

Frequency

(Hz)

Frequency (Hz)

V_IN= 2 V

C_IN= 220 µF

V_OUT= 1.8 V at 3 A

C_LOAD= 220 µF

V_IN= 7 V

C_IN= 220 µF

V_OUT= 6.7 V at I_LOAD= 3 A

C_LOAD= 220 µF

Figure 8-14. RMS Noise (10 Hz to 100 kHz) = 20.33 Figure 8-15. RMS Noise (10 Hz to 100 kHz) = 31.68

µVrms

8.2.1.9 Capacitors

TPS7H1101A-SP requires the use of a combination of tantalum and ceramic capacitors to achieve good volume

to capacitance ratio. Table 8-2 highlights some of the capacitors used in the device. TI recommends to follow

proper derating guidelines as recommended by the capacitor manufacturer based upon output voltage and

operating temperature.

Note that polymer-based tantalum capacitors must be derated to at least 60% of rated voltage, whereas

manganese oxide (MnO₂) based tantalum capacitors should be derated to 33% of rated voltage depending

upon the operating temperature.

TI recommends to use a tantalum capacitor along with a 0.1-µF ceramic capacitor. The device is stable for input

and output tantalum capacitor values of 10 µF to 220 µF with the ESR range of 10 mΩ to 2 Ω. However, the

dynamic performance of the device varies based on load conditions and the capacitor values used.

TI recommends a minimum output capacitor of 22 µF with ESR of 1 Ω or less to prevent oscillations. X7R

dielectrics are preferred. See Table 8-2 for various capacitor recommendations.

24

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

Table 8-2. TPS7H1101A-SP Capacitors

CAPACITOR DETAILS

(CAPACITOR, VOLTAGE, ESR)

CAPACITOR PART NUMBER

TYPE

Tantalum - MnO2

VENDOR

T493X107K016CH612A⁽¹⁾

T493X226M025AH6x20⁽¹⁾

T525D476M016ATE035⁽¹⁾

T540D476M016AH6520⁽¹⁾

T525D107M010ATE025⁽¹⁾

T541X337M010AH6720⁽¹⁾

T525D227M010ATE025⁽¹⁾

T495X107K016ATE100⁽¹⁾

CWR29FK227JTHC⁽¹⁾

100 µF, 16 V, 100 mΩ

22 µF, 25 V, 35 mΩ

47 µF, 10 V, 35 mΩ

47 µF, 16 V, 20 mΩ

100 µF, 10 V, 25 mΩ

330 µF, 10 V, 6 mΩ

220 µF, 10 V, 25 mΩ

100 µF, 16 V, 100 mΩ

220 µF, 10 V, 180 mΩ

100 µF, 16 V, 58 mΩ

220 µF, 10 V, 40 mΩ

33 µF, 25 V

Kemet

Tantalum - MnO2

Tantalum - Polymer

Tantalum - MnO2

Tantalum

Kemet

AVX

THJE107K016AJH

AVX

THJE227K010AJH

Tantalum

AVX

SMX33C336KAN360

Stacked ceramic

Ceramic

SR2225X7R335K1P5#M123

3.3 µF, 25 V, 10 mΩ

Presidio Components Inc

(1) Operating temperature is –55°C to 125°C.

8.2.2 Application Curves

350

300

250

200

150

100

50

125 °C

25 °C

-55 °C

0

0.5

1

1.5

I_OUT(A)

2

2.5

3

Figure 8-16. VDO vs I_OUT

Submit Document Feedback

25

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

9 Power Supply Recommendations

This device is designed to operate with an input voltage supply up to 7 V. The minimum input voltage should

provide adequate headroom greater than the dropout voltage for the device to have a regulated output. If the

input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance.

10 Layout

10.1 Layout Guidelines

•

For best performance, all traces should be as short as possible, and no longer than 5 cm.

Use wide traces for IN, OUT and GND to minimize the parasitic electrical effects.

Place the output capacitors (COUT) as close as possible to the OUT pin of the device.

10.2 Layout Example

C

1

2

3

4

5

6

7

8

SS

FB 16

COMP 15

VOUT 14

VOUT 13

VOUT 12

VOUT 11

CS 10

EN

Cap

C

VIN

PCL

GND

VIN

plane

Vout plane

Cap

To CS sense

PG/OC

9

To PG/OC sense

Vias from top layer

thermal pad GND to

main GND plane(s)

Via to GND

Main GND layer(s) plane

Figure 10-1. PCB Layout Example

26

Submit Document Feedback

Product Folder Links: TPS7H1101A-SP

TPS7H1101A-SP

SLVSDW6C – APRIL 2017 – REVISED APRIL 2021

www.ti.com

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Device Nomenclature

KGD

Known good die

RHA

Radiation hardness assurance for space systems

Same device as TPS50601-SP, shown with standard microcircuit drawing (SMD)

5962R13202

TPS7H1101A-SP Same device as 5962R10221, shown with TI package drawing

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator

application note (SBVA042)

Texas Instruments, TPS7H1101‐SP TID and SEE radiation report (SNAA257)

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

27

Product Folder Links: TPS7H1101A-SP

PACKAGE OUTLINE

HKR0016A

CFP - 2.416 mm max height

S

C

A

L

E

0

.

7

0

CERAMIC DUAL FLATPACK

9.88

9.38

B

METAL LID

A

PIN 1 ID

14X 1.27

16

1

11.26

10.76

(10.41)

2X 8.89

8

9

0.482

16X

0.382

(9.14)

0.2

C A B

METAL LID

C

2.416

1.850

0.177

0.097

(6.59)

1.19

0.69

25.142

24.642

HEATSINK

8

9

8.95

8.65

16

1

6.74

6.44

PIN 1 ID

4226020/B 12/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermetically sealed with a metal lid. Lid is connected to Heatsink and pin 8 (GND).

4. The terminals are gold plated.

5. Falls within MIL-STD-1835 CDFP-F11A.

www.ti.com

EXAMPLE BOARD LAYOUT

HKR0016A

CFP - 2.416 mm max height

CERAMIC DUAL FLATPACK

(6.59)

(1.2) TYP

(0.6)

(1.2) TYP

(0.6)

(8.8)

PKG

(

0.2) TYP

PKG

HEATSINK LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

4226020/B 12/2020

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	5962R1320202VXC
厂家：	TEXAS INSTRUMENTS
描述：	耐辐射 QMLV、1.5V 至 7V 输入、3A 低噪声可调低压降 (LDO) 稳压器 \| HKR \| 16 \| -55 to 125 输出元件稳压器调节器
文件：	总32页 (文件大小：2100K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5962R1320202VXC [TI]

相关型号：

5962R1320801VXC

5962R1322001V9A

5962R1322001VXC

5962R1420302V9A

5962R1420302VYC

5962R1420801V9A

5962R1420801VXC

5962R1420802V9A

5962R1420802VXC

5962R1420803V9A

5962R1420803VXC

5962R1420804V9A