5962R8670412VYC [TI]

Radiation-hardened QMLV, 30-V input, 1-A single-output 500-kHz PWM controller, 100% duty cycle | HKU | 10 | -55 to 125;


型号：	5962R8670412VYC
厂家：	TEXAS INSTRUMENTS
描述：	Radiation-hardened QMLV, 30-V input, 1-A single-output 500-kHz PWM controller, 100% duty cycle \| HKU \| 10 \| -55 to 125
文件：	总29页 (文件大小：3773K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

UC1843B-SP QML V 类耐辐射电流模式 PWM 控制器

1 特性

2 应用

•

符合 QML V 类 (QMLV) 标准，SMD 5962-86704

5962R8670412VYC：

•

直流/直流转换器

支持多种拓扑结构：

–

耐辐射加固保障 (RHA) 能力高达

100krad(Si) 总电离剂量 (TID)

–

反激、正激降压、升压

推挽、半桥、全桥（采用外部接口电路时）

•

经过优化适用于离线和直流/直流转换器

低启动电流 (< 0.5mA)

修整的振荡器放电电流

自动前馈补偿

•

可用于军用温度范围，即 -55°C 至 125°C

3 说明

UC1843B-SP 控制 IC 是与 UC1843A-SP 引脚兼容的

耐辐射加固版。该器件提供了控制电流模式开关电源所

必需的特性，并改进了多种特性。额定启动电流低于

0.5mA，振荡器放电电流调整为 8.3mA。UVLO 期

间，输出级在低于 1.2V 的电压下至少具有 10mA 的灌

电流能力（V_CC高于 5V）。

逐脉冲电流限制

增强型负载响应特性

带滞后的欠压闭锁 (UVLO) 保护

双脉冲抑制

高电流图腾柱输出

内部调整的带隙参考

500kHz 工作频率

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

低 R_O误差放大器

UC1843B-SP

CFP/HKU (10)

6.48mm x 7.02mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

V_CC

UVLO

34 V

5-V

REF

S/R

V_REF

5.0 V

50 mA

Gnd

2.5 V

Internal

Bias

V_REF

V_C

Good

Logic

R_T/C_T

Osc

Output

Error

Amplifier

Pwr

Ground

PWM

Latch

V_FB

Comp

C/S

1 V

Current

Sense

Comparator

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDD4

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

7.4 Device Functional Modes........................................ 13

Application and Implementation ........................ 14

8.1 Application Information............................................ 14

8.2 Typical Application .................................................. 14

Power Supply Recommendations...................... 21

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

Detailed Description .............................................. 7

7.1 Overview ................................................................... 7

7.2 Functional Block Diagram ......................................... 7

7.3 Feature Description................................................... 7

10 Layout................................................................... 21

10.1 Layout Guidelines ................................................. 21

10.2 Layout Example .................................................... 22

11 器件和文档支持 ..................................................... 23

11.1 接收文档更新通知 ................................................. 23

11.2 社区资源................................................................ 23

11.3 商标....................................................................... 23

11.4 静电放电警告......................................................... 23

11.5 Glossary................................................................ 23

12 机械、封装和可订购信息....................................... 23

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (April 2019) to Revision A

Page

•

Changed the package image in the Pin Configuration and Functions ................................................................................... 3

Changed <10 mA To: <17 mA in Figure 6 .......................................................................................................................... 10

UC1843B-SP

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ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

5 Pin Configuration and Functions

HKU Package

10-Pin CFP

Top View

Comp

V_FB

V_REF

V_CC

Output

Gnd

I_SENSE

R_T/C_T

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

Comp

V_FB

NO.

Error amplifier output.

Voltage feedback input to error amplifier.

Current sense comparator input pin.

RC time constant input to oscillator.

No connect.

I_SENSE

R_T/C_T

5, 6

—

Gnd

Ground.

Output

V_CC

Regulated output.

Unregulated supply voltage.

5-V internally generated reference.

V_REF

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

over operating free-air temperature (unless otherwise noted)

MIN

MAX

UNIT

V_CC

V_I

Supply voltage, low-impedance source⁽³⁾

Input voltage (V_FB, I_SENSE

)

–0.3

6.3

Supply current

Self limiting

I_O

Output current

±1

μJ

Error amplifier output sink current

Output energy (capacitive load)

Power dissipation (T_A= 25°C)

Lead temperature (soldering, 10 s)

Storage temperature

P_D

T_lead

T_stg

300

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to ground. Currents are positive in, negative out of the specified terminal.

(3) Current limiting this input will allow for higher supply voltages.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101 or

ANSI/ESDA/JEDEC JS-002⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (T_A= T_J= –55°C to 125°C), unless otherwise noted

MIN

MAX

UNIT

V_CC

Supply voltage

Sink/source output current (continuous or time average)

Reference load current

200

6.4 Thermal Information

UC1843B-SP

HKU (CFP)

10 PINS

51.9

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC(bot)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (bottom) thermal resistance

Junction-to-board thermal resistance

°C/W

6.6

31.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

5.42

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

UC1843B-SP

www.ti.com.cn

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

6.5 Electrical Characteristics

V_CC= 15 V⁽¹⁾, R_T= 10 kΩ, C_T= 3.3 nF, T_A= T_J= –55°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

REFERENCE

Output voltage

Line regulation

Load regulation

T_J= 25°C, I_O= 1 mA

4.85

5.1

V_IN= 12 to 25 V

I_O= 1 to 20 mA

Temperature stability⁽²⁾⁽³⁾

Total output variation⁽²⁾

Output noise voltage

Long-term stability

0.2

0.4 mV/°C

Over line, load, and temperature

10 Hz ≤ ƒ ≤ 10 kHz, T_J= 25°C

1000 hours, T_A= 125°C⁽²⁾

4.85

5.1

μV

Short-circuit output current

OSCILLATOR

–30

–100

–180

Initial accuracy

T_J= 25°C⁽⁴⁾

0.2%

kHz

Voltage stability

V_CC= 12 to 25 V

T_J= –55°C to 125°C⁽²⁾

V pin 4⁽²⁾

Temperature stability

Amplitude peak-to-peak

1.7

T_J= 25°C

T_J= Full range

7.8

7.5

8.3

8.8

Discharge current

V pin 4 = 2 V⁽⁵⁾

ERROR AMPLIFIER

Input voltage

V_Comp= 2.5 V

2.45

2.50

–0.3

2.55

–1

μA

MHz

Input bias current

Open-loop voltage gain

Unity-gain bandwidth

PSRR

V_O= 2 to 4 V

T_J= 25°C⁽²⁾

0.7

V_CC= 12 to 25 V

Output sink current

Output source current

High-level output voltage

Low-level output voltage

CURRENT SENSE

Gain⁽⁶⁾⁽⁷⁾

V_FB= 2.7 V, V_Comp= 1.1 V

V_FB= 2.3 V, V_Comp= 5 V

–0.5

–0.8

V_FB= 2.3 V, R_L= 15 kΩ to ground

V_FB= 2.7 V, R_L= 15 kΩ to V_REF

0.7

1.1

2.85

0.9

3.15

1.1

V/V

Maximum input signal

PSRR

V_Comp= 5 V⁽⁶⁾

V_CC= 12 to 25 V⁽⁶⁾

–2

μA

Input bias current

Delay to output

–10

300

V_ISENSE= 0 to 2 V⁽²⁾

150

(1) Adjust V_CCabove the start threshold before setting at 15 V.

(2) Parameters ensured by design and/or characterization, if not production tested.

(3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:

Temperature Stability = V_REF(max) – V_REF(min) / T_J(max) – T_J(min). V_REF(max) and V_REF(min) are the maximum and minimum

reference voltage measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the

extremes in temperature.

(4) Output frequency equals oscillator frequency.

(5) This parameter is measured with R_T= 10 kΩ to V_REF. This contributes approximately 300 μA of current to the measurement. The total

current flowing into the R_Tor C_Tpin will be approximately 300 μA higher than the measured value.

(6) Parameter measured at trip point of latch with V_FB= 0 V.

(7) Gain defined as: G = ΔV_Comp/ ΔV_ISENSE; V_ISENSE= 0 to 0.8 V.

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

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MAX UNIT

Electrical Characteristics (continued)

V_CC= 15 V⁽¹⁾, R_T= 10 kΩ, C_T= 3.3 nF, T_A= T_J= –55°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

OUTPUT

I_SINK= 20 mA

I_SINK= 200 mA

0.1

1.5

0.4

Output low-level voltage

Output high-level voltage

2.2

I_SOURCE= –20 mA

13.5

I_SOURCE= –200 mA

Rise time

C_L= 1 nF, T_J= 25°C⁽²⁾

V_CC= 5 V, I_SINK= 10 mA

150

1.2

Fall time

UVLO saturation

0.7

UNDERVOLTAGE LOCKOUT

Start threshold

7.8

8.4

7.6

Minimum operation voltage after turnon

PWM

8.2

Maximum duty cycle

Minimum duty cycle

TOTAL STANDBY CURRENT

Start-up current

94%

96% 100%

0.3

0.5

Operating supply current

V_CCZener voltage

V_FB= V_ISENSE= 0 V

I_CC= 25 mA

6.6 Typical Characteristics

.01 .02 .03 .04 .05 .07 .1

.2 .3 .4 .5 .7 1.0

Output Current, Source or Sink (A)

Figure 1. Output Saturation Characteristics

UC1843B-SP

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ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

7 Detailed Description

7.1 Overview

The UC1843B-SP control IC is a pin-for-pin compatible improved version of the UC1843A-SP. Providing the

necessary characteristics to control current-mode switched-mode power supplies, this device has improved

features. Start-up current is specified to be less than 0.5 mA and oscillator discharge is trimmed to 8.3 mA.

During UVLO, the output stage can sink at least 10 mA at less than 1.2 V for V_CCover 5 V.

7.2 Functional Block Diagram

V_CC

UVLO

34 V

5-V

REF

S/R

V_REF

5.0 V

50 mA

Gnd

2.5 V

Internal

Bias

V_REF

V_C

Good

Logic

R_T/C_T

Osc

Output

Error

Amplifier

Pwr

Ground

PWM

Latch

V_FB

Comp

C/S

1 V

Current

Sense

Comparator

7.3 Feature Description

UC1843B-SP is a current mode controller, used to support various topologies such as forward, flyback, buck,

and boost. Using an external interface circuit will also support half-bridge, full-bridge, and push-pull

configurations.

Figure 2 shows the two-loop current-mode control system. A clock signal initiates power pulses at a fixed

frequency. The termination of each pulse occurs when an analog of the inductor current reaches a threshold

established by the error signal. In this way, the error signal actually controls peak inductor current. This contrasts

with voltage control in which the error signal directly controls pulse width without regard to inductor current.

Several performance advantages result from the use of current-mode control. First, an input voltage feed-forward

characteristic is achieved; that is, the control circuit instantaneously corrects for input voltage variations without

using up any of the error amplifier’s dynamic range. Therefore, line regulation is excellent and the error amplifier

can be dedicated to correcting for load variations exclusively.

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Feature Description (continued)

Figure 2. Two-Loop Current-Mode Control System

For converters in which inductor current is continuous, controlling peak current is nearly equivalent to controlling

average current. Therefore, when such converters employ current-mode control, the purposes of small signal

analysis (see Figure 3). The two pole control to output frequency response of these converters is reduced to a

single-pole (filter capacitor in parallel with load) response. One result is that the error amplifier compensation can

be designed to yield a stable closed-loop converter response with greater gain bandwidth than would be possible

with pulse-width control, giving the supply improved small signal dynamic response to changing loads. A second

result is that the error amplifier compensation circuit becomes simpler, as shown in Figure 4.

Capacitor C_iand resistor R_i, in Figure 4(A), add a low frequency zero, which cancels one of the two control to

output poles of non-current mode converters. For large signal load changes, in which converter response is

limited by inductor slew rate, the error amplifier saturates while the inductor is catching up with the load. During

this time, C_icharges to an abnormal level. When the inductor current reaches its required level, the voltage on C_i

causes a corresponding error in supply output voltage. The recovery time is R_izC_i, which may be long. However,

the compensation network of Figure 4(B) can be used where current-mode control has eliminated the inductor

pole. Large-signal dynamic response is then greatly improved due to the absence of C_i.

Current limiting is greatly simplified with current mode control. Pulse-by-pulse limiting is, of course, inherent in

the control scheme. Furthermore, an upper limit on the peak current can be established by simply clamping the

error voltage. Accurate current limiting allows optimization of magnetic and power semiconductor elements while

ensuring reliable supply operation.

Finally, current-mode controlled power stages can be operated in parallel with equal current sharing. This opens

the possibility of a modular approach to power supply design.

UC1843B-SP

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ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

Feature Description (continued)

Figure 3. Inductor Looks Like a Current Source to Small Signals

A. Direct duty cycle control

B. Current mode control

Figure 4. Required Error Amplifier Compensation for Continuous Inductor Current Designs

7.3.1 UVLO

The UVLO circuit ensures that V_CCis adequate to make the UC1843B-SP fully operational before enabling the

output stage. Figure 5 shows that the UVLO turnon and turnoff thresholds are fixed internally at 8.4 V and 7.6 V,

respectively. The 0.6-V hysteresis prevents V_CCoscillations during power sequencing.

Figure 6 shows supply current requirements. Start-up current is < 1 mA for efficient bootstrapping from the

rectified input of an off-line converter, as shown in Figure 7. During normal circuit operation, V_CCis developed

from auxiliary winding, W_Aux, with D₁and C_IN. However, at start-up, C_INmust be charged to 8.4 V through R_IN.

With a start-up current of 1 mA, R_INcan be as large as 100 kΩ and still charge C_INwhen V_AC= 90-V RMS (low

line). Power dissipation in R_INwould then be less than 350 mW even under high line (V_AC= 130-V RMS)

conditions.

During UVLO, the output driver is in a low state. While it does not exhibit the same saturation characteristics as

normal operation, it can easily sink 1 mA, enough to ensure the MOSFET is held off. For efficient operations, an

LDO can take the place of R_INand be disabled during the operation of the device.

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Feature Description (continued)

Figure 5. UVLO Turnon and Turnoff Threshold

I_CC

<17 mA

<1 mA

V_CC

V_OFF

V_ON

NOTE: During UVLO, the output driver is biased to sink minor amounts of current.

Figure 6. Supply Current Requirements

Figure 7. Providing Power to the UC1843B-SP

UC1843B-SP

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ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

Feature Description (continued)

7.3.2 Reference

As highlighted in the Functional Block Diagram, UC1843B-SP incorporates a 5-V internal reference regulator with

±2% set point variation over temperature.

7.3.3 Totem-Pole Output

The UC1843B-SP PWM has a single totem-pole output which can be operated to ±1-A peak for driving MOSFET

gates, and a 200-mA average current for bipolar power U-100A transistors. Cross conduction between the output

transistors is minimal, the average added power with V_IN= 30 V is only 80 mW at 200 kHz.

Limiting the peak current through the IC is accomplished by placing a resistor between the totem-pole output and

the gate of the MOSFET. The value is determined by dividing the totem-pole collector voltage V_Cby the peak

current rating of the IC’s totem-pole. Without this resistor, the peak current is limited only by the dV/dT rate of the

totem-pole switching and the FET gate capacitance. Adding resistance will increase the switching losses of the

converter, but will often reducing ringing and switching noise.

The use of a Schottky diode from the PWM output to ground prevents the output voltage from going excessively

below ground, causing instabilities within the IC. To be effective, the diode selected should have a forward drop

of less than 0.3 V at 200 mA. Most 1- to 3-A Schottky diodes exhibit these traits above room temperature.

Placing the diode as physically close to the PWM as possible enhances circuit performance. Implementation of

the complete drive scheme is shown in Figure 8 through Figure 10. Transformer-driven circuits also require the

use of the Schottky diodes to prevent a similar set of circumstances from occurring on the PWM output. The

ringing below ground is greatly enhanced by the transformer leakage inductance and parasitic capacitance, in

addition to the magnetizing inductance and FET gate capacitance. Circuit implementation is similar to the

previous example.

Figure 8 through Figure 10 show suggested circuits for driving MOSFETs and bipolar transistors with the

UC1843B-SP output. The simple circuit of Figure 8 can be used when the control IC is not electrically isolated

from the MOSFET turnon and turnoff to ±1 A. It also provides damping for a parasitic tank circuit formed by the

FET input capacitance and series wiring inductance. Schottky diode, D₁, prevents the output of the IC from going

far below ground during turnoff.

Figure 9 shows an isolated MOSFET drive circuit which is appropriate when the drive signal must be level shifted

or transmitted across an isolation boundary. Bipolar transistors can be driven efficiently with the circuit of

Figure 10. Resistors R₁and R₂fix the on-state base current while capacitor C_lprovides a negative base current

pulse to remove stored charge at turnoff.

Because the UC1843B-SP series has only a single output, an interface circuit is needed to control push-pull,

half-bridge, or full-bridge topologies. The UC1706 dual output driver with internal toggle flip-flop performs this

function. The Typical Application section shows a typical application for these two ICs. Increased drive capability

for driving numerous FETs in parallel, or other loads can be accomplished using one of the UC1705/7-SP driver

ICs.

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ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Feature Description (continued)

Figure 8. Direct MOSFET Drive

Figure 9. Isolated MOSFET Drive

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ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

Feature Description (continued)

Figure 10. Bipolar Drive With Negative Turnoff Bias

7.4 Device Functional Modes

The UC1843B-SP uses fixed frequency, peak current mode control. An internal oscillator initiates the turnon of

the driver to high-side power switch. The external power switch current is sensed through an external resistor

and is compared via internal comparator. The voltage generated at the COMP pin is stepped down via internal

resistors (as shown in the Functional Block Diagram). When the sensed current reaches the stepped down

COMP voltage, the high-side power switch is turned off.

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

UC1843B-SP can be used as a controller to design various topologies such as buck, boost, flyback, and forward.

Using an external interphase circuit can also support push-pull, half-bridge, and full-bridge topologies.

8.2 Typical Application

Figure 11. Typical Application Schematic

8.2.1 Design Requirements

See Table 1 for parameter values.

Table 1. Design Parameters

PARAMETER

Input Power Supply

Output Voltage

SPECIFICATIONS

20 to 40 VDC

5 VDC

Output Current

0 to 10 A

100 mA

Output Current Pre-load

Operating Temperature

Switching Frequency of UC1843B-SP

Peak Input Current Limit

Bandwidth

25°C

200 kHz

12 A

~4 kHz

Phase Margin

~80°

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8.2.2 Detailed Design Procedure

8.2.2.1 Switching Frequency

Choosing a switching frequency has a trade off between efficiency and bandwidth. Higher switching frequencies

will have larger bandwidth, but a lower efficiency than lower switching frequencies. A switching frequency of 200

kHz was chosen as a trade off between bandwidth and efficiency. Using Equation 1, R_Tand C_Twere chosen to

be 7.15 kΩ and 1200 pF, respectively.

(1)

(2)

8.2.2.2 Transformer

The transformer of the design consists of two major values, turns ratio and primary side inductance. There is no

minimum limit to the turns ratio of the transformer, just a maximum limit. The equation below will give the turns

ratio as a function of duty cycle, which if you put in the maximum duty cycle of the converter will give you a

maximum turns ratio. The UC1843B-SP design targeted a duty cycle of 50%, which is somewhat low for this

controller. The suggested value would be around 70% duty cycle to take advantage of the fact the UC1843B-SP

has full duty cycle range. The equation of the turns ratio of the transformer is Equation 3.

(3)

(4)

Often the turns ratio will slightly change in design due to how the transformer is manufactured. For the UC1843B-

SP design a turns ratio of 3.33 was used. Another turns ratio that is important is the turns ratio of the auxiliary

winding. The auxiliary winding is found by figuring out what positive voltage is needed from the auxiliary winding.

Picking what voltage the auxiliary winding should have lets one pick the turns ratio from the secondary to the

auxiliary winding, which in turn allows for the turns ratio from primary to auxiliary to be found. The equation for

the turns ratio for the auxiliary winding is Equation 5.

(5)

(6)

An auxiliary winding of 1.43 was used for the UC1843B-SP design due to manufacturing constraints. The primary

inductance of the transformer is found from picking an appropriate ripple current. A higher inductance will often

mean reduced current ripple, thus lower EMI and noise, but a higher inductance will also increase physical size

and limit the bandwidth of the design. A lower inductance will do the opposite, increasing current ripple, lowering

EMI, lowering noise, decreasing physical size, and increasing the limited bandwidth of the design. The percent

ripple current can be anywhere from 20% to 80% depending on the design. The equation for finding the primary

inductance from the percentage ripple current is Equation 7.

(7)

(8)

There are quite a few physical limitations when making transformers, so often this inductance will change slightly.

For the UC1843B-SP design a primary inductance of 21 µH. This corresponds to a percent ripple of around

0.475. The peak and primary currents of the transformer are also generally useful for figuring out the physical

structure of the transformer. See the following equations for proper calculations.

(9)

(10)

(11)

(12)

(13)

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

(14)

(15)

(16)

8.2.2.3 RCD Diode Clamp

For the UC1843B-SP design a resistor and capacitor are used. The resistor and capacitor is generally a value

that is found through testing, but starting values can be obtained. To figure out the resistor and capacitor needed

for the RCD clamp, one must first pick how much the node is allowed to overshoot. The equation for finding the

voltage of the clamp is Equation 17.

(17)

Note that K_clampis recommended to be 1.5 as this will allow for only around 50% overshoot. Knowing the

parasitic inductance of the transformer and how much the snubber voltage is allowed to change over the

switching cycle, can allow one to figuring out starting values for the resistor and capacitor using Equation 18 and

Equation 19.

(18)

(19)

A starting value of 10% is generally used for ΔV_clamp

8.2.2.4 Output Diode

The voltage stress by the converter on the diode can be found with Equation 20.

(20)

(21)

Note that any diode picked should have a voltage rating of well above this value as it does not include parasitic

spikes in the equation. The UC1843B-SP diode was picked to have a voltage rating of 60 V.

8.2.2.5 Output Filter and Capacitor

The output capacitance value is picked such that there is enough capacitance for the required voltage ripple and

output current load step. The UC1843B-SP design uses equations Equation 22 and Equation 24 to find a

minimum capacitance.

(22)

(23)

(24)

(25)

A value of around 1145 µF was chosen to keep output voltage ripple low. Note that the output voltage ripple in

the design was further decreased by adding an output filter and by adding an inductor after a small portion of the

output capacitance. Six ceramic capacitors were picked to be placed before the output filter and then the large

tantalum capacitors with some small ceramics were added to be part of the output filter. The initial ceramics will

help with the initial current ripple, but have a very large output voltage ripple. This voltage ripple will be

attenuated by the inductor and capacitor combination placed between the ceramic capacitors and the output. The

equations below allow for finding the amount of attenuation that will come from a specific output filter inductance.

An inductance of 500 nH was chosen to attenuate the output voltage ripple and the attenuation was sufficient for

the design.

(26)

UC1843B-SP

www.ti.com.cn

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

(27)

(28)

(29)

(30)

(31)

Sometimes the output filter can cause peaking at high frequencies, this can be damped by adding a resistor in

parallel with the inductor. For the UC1843B-SP design, 0.5 Ω was used as a very conservative value. The

resistance needed to damp the peaking can be calculated using the following equations:

(32)

(33)

(34)

(35)

8.2.2.6 Compensation

The poles and zeros of a flyback converter can be found with the following equations:

(36)

(37)

(38)

(39)

(40)

(41)

(42)

(43)

Type IIB compensation was selected to compensate the poles and zeros of the flyback converter for the design.

Since the right half plane zero (RHPZ) of the flyback converter is unable to be compensated, the crossover

frequency of the converter should be between one fourth to a whole decade below the RHPZ of the converter.

Type IIB compensation has 1 pole and 1 zero to help compensate the converter. The pole from the

compensation is suggested to be placed by the RHPZ of the converter and the zero from compensation is

suggested to be placed a decade before the expected crossover frequency. Using these guidelines the

compensation values for the converter were picked for the converter. For the non-isolated portion of the board

this means choosing the value of the compensation resistors and capacitors along these guidelines. Increasing

or decreasing the gain of the design can be compensated for by dividing the resistor from compensation down

and increasing the values of the capacitors by the same amount. This allows for the gain to be controlled in the

system without changing the poles and zeros of the system. Optimization is needed for compensation values,

and those values can be validated through testing.

8.2.2.7 Sense Resistor and Slope Compensation

The sense resistor is used to sense the ripple current from the transformer as well as shutdown the switching

cycle if the peak current of the converter is allowed to get too high. The voltage threshold of the CS pin is around

1 V, thus the equation to find the sense resistor from the peak current is shown in Equation 44.

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

(44)

(45)

Note that I_limitshould be greater than I_PriPeak, and that the voltage offset from the slope compensation will be

dependant on the amount of slope compensation in the design. The value of 0.075 Ω for the sense resistance

was found to be the optimum value adding some headroom for slope compensation offset of 0.1 V. Slope

compensation was implemented with a BJT being turned off and on by the RC pin of the device. The BJT was

placed between the REF pin and a resistor divider to the CS pin. The optimum slope compensation value can be

found from the following equations after picking a value for the top of the divider:

(46)

(47)

(48)

(49)

(50)

(51)

The UC1843B-SP design uses a much higher resistor of 1.47 kΩ, but this is an attempt to be very conservative.

Note that the bottom resistor can be used as part of a filter to the CS pin as well, which is implemented in the

design using a capacitor near the CS pin. Care was taken such that the RC filter would not filter the switching

frequency by having the RC time constant be a decade less than the switching frequency.

8.2.3 Application Curves

Figure 12. Switch Node of Flyback Converter

For the test in Figure 12, 40 V was applied to the input and 10 A was drawn from the output. Ringing can be

present on the switching node if the converter is run in discontinuous conduction mode rather than the

continuous conduction mode the design was run with.

UC1843B-SP

www.ti.com.cn

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

Figure 13. Load Step Down With 40 V_IN

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Figure 14. Load Step Up With 40 V_IN

For tests shown in and , 40 V was applied to the input and a load step was applied to the output. The load step

applied was from 0 A to 10 A and 10 A to 0 A. Note that those currents do not include the 0.1-A pre-load. The

curves show that the stability of the design due to the lack of ringing during the load step.

UC1843B-SP

www.ti.com.cn

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

9 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 8 V and 32 V. This input

supply should be well regulated. If the input supply is located more than a few inches from the UC1843B-SP

converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. A tantalum

capacitor with a value of 100 µF is a typical choice; however, this varies heavily on the start up circuitry of the

device. This is because the input voltage to the device will decrease during start up and the input capacitance

will have to provide enough charge to allow the UC1843B-SP to initially switch.

Figure 15. Flyback Regulator

10 Layout

10.1 Layout Guidelines

Always try to use a low EMI inductor with a ferrite closed core. Some examples would be toroid and encased E

core inductors. Open core can be used if they have low EMI characteristics and are located a farther away from

the low-power traces and components. Make the poles perpendicular to the PCB as well if using an open core.

Stick cores usually emit the most unwanted noise.

10.1.1 Feedback Traces

Try to run the feedback trace as far as possible from the inductor and noisy power traces. The designer should

also make the feedback trace as direct as possible and somewhat thick. These two guidelines sometimes involve

a trade-off, but keeping the trace away from inductor EMI and other noise sources is the more critical guideline.

Run the feedback trace on the side of the PCB opposite of the inductor with a ground plane separating the two.

10.1.2 Input/Output Capacitors

When using a low-value ceramic input filter capacitor, locate it as close as possible to the V_INpin of the IC. This

eliminates as much trace inductance effects as possible and gives the internal IC rail a cleaner voltage supply.

Some designs require the use of a feed-forward capacitor connected from the output to the feedback pin as well,

usually for stability reasons. In this case, it should also be positioned as close as possible to the IC.

10.1.3 Compensation Components

External compensation components for stability should also be placed close to the IC. TI recommends to also

use surface mount components for the same reasons discussed for the filter capacitors. These should not be

located very close to the inductor either.

UC1843B-SP

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Layout Guidelines (continued)

10.1.4 Traces and Ground Planes

Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a

standard PCB to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. The inductor, output

capacitors, and output diode should be as close as possible to each other. This helps reduce the EMI radiated by

the power traces due to the high-switching currents through them. This also reduces lead inductance and

resistance, which in turn reduces noise spikes, ringing, and resistive losses that produce voltage errors. The

grounds of the IC, input capacitors, output capacitors, and output diode (if applicable) should be connected close

together directly to a ground plane. It would also be a good idea to have a ground plane on both sides of the

PCB. This reduces noise by reducing ground loop errors and absorbing more of the EMI radiated by the inductor.

For multi-layer boards with more than two layers, a ground plane can be used to separate the power plane

(where the power traces and components are located) and the signal plane (where the feedback and

compensation and components are located) for improved performance. On multi-layer boards, vias are required

to connect traces and different planes. Arrange the components so that the switching current loops curl in the

same direction. Due to the way switching regulators operate, there are two power states: one state when the

switch is on and one when the switch is off. During each state there is a current loop made by the power

components that are currently conducting. Place the power components so that during each of the two states the

current loop is conducting in the same direction. This prevents magnetic field reversal caused by the traces

between the two half-cycles and reduces radiated EMI.

10.2 Layout Example

NOTE: High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass

capacitors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used

to sample the oscillator waveform and apply an adjustable ramp to pin 3.

Figure 16. Open-Loop Laboratory Test Fixture

UC1843B-SP

www.ti.com.cn

ZHCSJK0A –APRIL 2019–REVISED SEPTEMBER 2019

11 器件和文档支持

11.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.2 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

5962R8670412V9A

5962R8670412VYC

ACTIVE

XCEPT

CFP

KGD

HKU

RoHS & Green

Call TI

N / A for Pkg Type

-55 to 125

Samples

RoHS-Exempt

& Green

R8670412VYC

UC1843B-SP

UC1843BHKU/EM

ACTIVE

CFP

HKU

RoHS-Exempt

& Green

N / A for Pkg Type

25 to 25

UC1843BHKUM

EVAL ONLY

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

5962R8670412VYC

UC1843BHKU/EM

HKU

CFP

506.98

26.16

6220

Pack Materials-Page 1

PACKAGE OUTLINE

HKU0010A

CFP - 2.63mm max height

CERAMIC DUAL FLATPACK

7.06

6.66

METAL LID

PIN 1 ID

8X 1.27

7.27

(6.248)

6.77

2X 5.08

0.48

10X

0.38

(6.248)

0.2

C A

0.16

0.10

2.62 MAX

(4.7)

0.85

0.67

22.7 MAX

(4.3)

(6.62) (7.02)

PIN 1 ID

BACK SIDE PAD

METALIZATION

(THERMAL PAD)

4226200/A 09/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermetically sealed with a metal lid.

4. The terminals are gold plated.

5. This drawing does not comply with MIL STD 1835. Do not use this package for compliant product.

6. Metal lid is connected to back side pad metalization.

www.ti.com

EXAMPLE BOARD LAYOUT

HKU0010A

CFP - 2.63mm max height

CERAMIC DUAL FLATPACK

(4.3)

(1.2) TYP

(0.6)

PKG

(6.62)

(0.6)

(1.2) TYP

(

0.2) TYP

PKG

HEATSINK LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SCALE

SIZE

REV

PAGE

4226200

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

5962R8670412VYC [TI]

相关型号：

5962R8752501B2A

5962R8752501B2A

5962R8752501BCA

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5962R8752501SCA

5962R8752501SDA

5962R8754903V9A

5962R8754903VCA

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