65056 [TI]
6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS AND 4 LOW-INPUT VOLTAGE LDOs; 6通道电源管理IC具有两个降压型转换器和4低输入电压LDO
| 型号： | 65056 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS AND 4 LOW-INPUT VOLTAGE LDOs |
| 文件： | 总41页 (文件大小：1222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65050, TPS65051, TPS65052
TPS65054, TPS65056
www.ti.com
SLVS710–JANUARY 2007
6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS
AND 4 LOW-INPUT VOLTAGE LDOs
FEATURES
APPLICATIONS
•
•
•
•
Cell Phones, Smart-Phones
WLAN
PDAs, Pocket PCs
OMAP™ and Low-Power TMS320™ DSP
Supply
•
Up To 95% Efficiency
•
Output Current for DC/DC Converters:
–
–
–
–
–
TPS65050: 2 x 0.6 A
TPS65051: DCDC1 = 1 A; DCDC2 = 0.6 A
TPS65052: DCDC1 = 1 A; DCDC2 = 0.6 A
TPS65054: 2 x 0.6 A
•
•
Samsung S3C24xx application processor
Supply
Portable Media Players
TPS65056: DCDC1 = 1 A; DCDC2 = 0.6 A
•
Output Voltages for DC/DC Converters
DESCRIPTION
–
–
–
TPS65050: Externally Adjustable
TPS65051: Externally Adjustable
The TPS6505x are integrated Power Management
ICs for applications powered by one Li-Ion or
Li-Polymer cell, which require multiple power rails.
The TPS6505x provides two efficient, 2.25-MHz
step-down converters targeted at providing the core
voltage and I/O voltage in a processor based
system. Both step-down converters enter a low
power mode at light load for maximum efficiency
across the widest possible range of load currents.
TPS65052: DCDC1 = Fixed at 3.3 V;
DCDC2 = 1 V / 1.3 V for Samsung
Application Processors
–
–
TPS65054: DCDC1 = Externally Adjustable;
DCDC2 = 1.3 V / 1.05 V for OMAP™1710
Processor
TPS65056: DCDC1 = Fixed at 3.3 V;
DCDC2 = 1 V / 1.3 V for Samsung
Application Processors
For low noise applications, the devices can be forced
into fixed frequency PWM mode by pulling the
MODE pin high. In the shutdown mode, the current
consumption is reduced to less than 1 µA. The
devices allow the use of small inductors and
•
VI Range for DC/DC Converters
From 2.5 V to 6 V
•
•
•
•
•
•
2.25-MHz Fixed Frequency Operation
Power Save Mode at Light Load Current
180° Out-of-Phase Operation
capacitors to achieve
a
small solution size.
TPS6505x provides an output current of up to 1 A on
each DC/DC converter. The TPS6505x also integrate
two 400-mA LDO and two 200-mA LDO voltage
regulators, which can be turned on/off using separate
enable pins on each LDO. Each LDO operates with
an input voltage range between 1.5 V and 6.5 V
allowing them to be supplied from one of the
step-down converters or directly from the main
battery.
Output Voltage Accuracy in PWM mode ±1%
Low Ripple PFM Mode
Total Typical 32-µA Quiescent Current for
Both DC/DC Converters
•
•
100% Duty Cycle for Lowest Dropout
Two General-Purpose 400-mA, High PSRR
LDOs
Four digital input pins are used to set the output
voltage of the LDOs from a set of 16 different
combinations for LDO1 to LDO4 on TPS65050 and
TPS65052. In TPS65051, TPS65054 and TPS65056,
the LDO voltages are adjustable using external
resistor dividers.
•
Two General-Purpose 200-mA, High PSRR
LDOs
•
•
•
VI range for LDOs from 1.5 V to 6.5 V
Digital Voltage Selection for the LDOs
The TPS6505x come in a small 32-pin leadless
package (4 mm x 4 mm QFN) with a 0.4 mm pitch.
Available in a 4 mm x 4 mm 32-Pin QFN
Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OMAP, TMS320, PowerPAD are trademarks of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS65050, TPS65051, TPS65052
TPS65054, TPS65056
www.ti.com
SLVS710–JANUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART
NUMBER
OUTPUT CURRENT
for DC/DC CONVERTERS
QFN(1)
PACKAGE(2)
PACKAGE
MARKING
TA
OPTION
LDO voltages according to Table 1
DC/DC converters externally adjustable
TPS65050
TPS65051
TPS65052
2 x 600 mA
65050
65051
65052
LDO voltages externally adjustable
DC/DC converters externally adjustable
DCDC1 = 1 A
DCDC2 = 600 mA
LDO voltages according to Table 1
DCDC1 = 3.3 V; DCDC2 = 1 V / 1.3 V
DCDC1 = 1 A
DCDC2 = 600 mA
-40°C to 85°C
RSM
LDO voltages externally adjustable
DCDC1 = externally adjustable
DCDC2 = 1.3 V / 1.05 V
TPS65054
TPS65056
2 x 600 mA
65054
65056
LDO voltages externally adjustable
DCDC1 = 3.3 V
DCDC1 = 1A
DCDC2 = 600 mA
DCDC2 = 1.0 V / 1.3 V
(1) The RSM package is available in tape and reel. Add the R suffix (TPS65050RSMR) to order quantities per reel. Add the T suffix
(TPS65050RSMT) to order quantities of 250 parts per reel.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNITS
Input voltage range on all pins except AGND, PGND, and EN_LDO1 pins with
-0.3 V to 7 V
respect to AGND
VI
II
Input voltage range on EN_LDO1 pins with respect to AGND
Current at VINDCDC1/2, L1, PGND1, L2, PGND2
Current at all other pins
-0.3 V to VCC + 0.5 V
1800 mA
1000 mA
Continuous total power dissipation
Operating free-air temperature
See the dissipation rating table
–40°C to 85°C
125°C
TA
TJ
Maximum junction temperature
Tstg
Storage temperature range
–65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
POWER RATING DERATING FACTOR
POWER RATING
POWER RATING
(1)
PACKAGE
RθJA
58 K/W
TA ≤ 25°C
ABOVE TA = 25°C
TA = 70°C
TA = 85°C
RSM
1.7 W
17 mW/K
0.95 W
0.68 W
(1) The thermal resistance junction to case of the RSM package is 4 K/W measured on a high K board
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
6
UNIT
VI
Input voltage range for step-down converters, VINDCDC1/2
Output voltage range for step-down converter, VDCDC1
Output voltage range for step-down converter, VDCDC2
Input voltage range for LDOs, VINLDO1, VINLDO2, VINLDO3/4
2.5
0.6
0.6
1.5
V
V
V
V
VINDCDC1/2
VINDCDC1/2
6.5
VO
VI
2
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SLVS710–JANUARY 2007
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
1
NOM
MAX
UNIT
VINLDO1,
VINLDO2
Output voltage range for LDO1 and LDO2
VO
V
Output voltage range for LDO3 and LDO4
1
VINLDO3/4
1000
600
V
Output current at L1 (DCDC1) for TPS65051, TPS65052
Output current at L1 (DCDC1) for TPS65050, TPS65054
mA
mA
mA
mA
mA
µH
µF
µF
µF
µF
µF
°C
IO
Output current at L1 (DCDC2)
600
Output current at VLDO1, VLDO2
Output current at VLDO3, VLDO4
Inductor at L1, L2(1)
Output capacitor at VDCDC1, VDCDC2(2)
Output capacitor at VLDO1, VLDO2, VLDO3, VLDO4(2)
Input capacitor at VCC(2)
400
200
1.5
10
2.2
22
CO
CI
2.2
1
Input capacitor at VINLDO1/2(2)
Input capacitor at VINLDO3/4(2)
2.2
2.2
-40
-40
TA
TJ
Operating ambient temperature range
Operating junction temperature range
Resistor from battery voltage to VCC used for filtering(3)
85
125
10
°C
1
Ω
(1) See the Application Information section of this data sheet for more details.
(2) See the Application Information section of this data sheet for more details.
(3) Up to 2 mA can flow into VCC when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted
accordingly.
ELECTRICAL CHARACTERISTICS
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 µH, CO = 10 µF. TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted).
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range at VINDCDC1/2
2.5
6
V
One converter, IO = 0 mA.
PFM mode enabled (Mode = GND) device not
switching, EN_DCDC1 = VI OR EN_DCDC2 = VI;
EN_LDO1= EN_LDO2 = EN_LDO3/4 = GND
20
32
30
µA
Two converters, IO = 0 mA
Operating quiescent current
PFM mode enabled (Mode = 0) device not
switching, EN_DCDC1 = VI AND EN_DCDC2 = VI;
EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND
40
µA
µA
IQ
Total current into VCC, VINDCDC1/2,
VINLDO1, VINLDO2, VINLDO3/4
One converter, IO = 0 mA.
PFM mode enabled (Mode = GND) device not
switching, EN_DCDC1 = VI OR EN_DCDC2 = VI;
EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 =
VI
180
250
One converter, IO = 0 mA.
Switching with no load (Mode = VI), PWM operation
EN_DCDC1 = VI OR EN_DCDC2 = VI; EN_LDO1 =
EN_LDO2 = EN_LDO3/4 = GND
0.85
1.25
mA
mA
IQ
Operating quiescent current into VCC
Two converters, IO = 0 mA
Switching with no load (Mode = VI), PWM operation
EN_DCDC1 = VI AND EN_DCDC2 = VI; EN_LDO1
= EN_LDO2 = EN_LDO3/4 = GND
EN_DCDC1 = EN_DCDC2 = GND EN_LDO1 =
EN_LDO2 = EN_LDO3 = EN_LDO4 = GND
I(SD)
Shutdown current
9
12
2
µA
Undervoltage lockout threshold for
DCDC converters and LDOs
V(UVLO)
Voltage at VCC
1.8
V
3
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SLVS710–JANUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 µH, CO = 10 µF. TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4
MODE/DATA, EN_DCDC1, EN_DCDC2,
DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3,
DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3,
EN_LDO4
VIH
High-level input voltage
Low-level input voltage
1.2
0
VCC
0.4
V
V
MODE/DATA, EN_DCDC1, EN_DCDC2, DEFLDO1,
DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1,
EN_LDO2, EN_LDO3, EN_LDO4, DEFDCDC2
VIL
MODE/DATA = GND or VI
MODE/DATA, EN_DCDC1, EN_DCDC2,
DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3,
DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3,
EN_LDO4
0.01
1
µA
IlB
Input bias current
TPS65051 and TPS65052 only
V_FB_LDOx = 1 V
100
nA
FB_LDO1, FB_LDO2, FB_LDO3, FB_LDO4
POWER SWITCH
VINDCDC1/2 = 3.6 V
280
400
280
400
630
630
DCDC1
VINDCDC1/2 = 2.5 V
rDS(on)
P-channel MOSFET on resistance
mΩ
µA
VINDCDC1/2 = 3.6 V
DCDC2
VINDCDC1/2 = 2.5 V
Ilkg
P-channel leakage current
VDCDCx = V(DS) = 6 V
1
VINDCDC1/2 = 3.6 V
220
320
220
320
7
450
DCDC1
VINDCDC1/2 = 2.5 V
rDS(on)
N-channel MOSFET on resistance
N-channel leakage current
mΩ
VINDCDC1/2 = 3.6 V
450
DCDC2
VINDCDC1/2 = 2.5 V
Ilkg
VDCDCx = V(DS) = 6 V
TPS65050
10
µA
0.85
1.19
0.85
1
1.4
1
1.15
TPS65054
2.5 V ≤ VINDCDC1/2 ≤ 6
V
Forward Current Limit
PMOS (High-Side)
and NMOS (Low
side)
DCDC1:
DCDC2:
A
TPS65051, TPS65052,
TPS65056
I(LIMF)
1.65
1.15
2.5 V ≤ VINDCDC1/2 ≤ 6
TPS65050 - TPS65056
V
A
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
150
20
°C
°C
Thermal shutdown hysteresis
OSCILLATOR
fSW Oscillator frequency
2.025
2.25
2.475
MHz
4
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SLVS710–JANUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 µH, CO = 10 µF. TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Output voltage range for DCDC1,
DCDC2
externally adjustable
versions
VINDCDC
1/2
VO
0.6
V
externally adjustable
versions
Vref
Reference voltage
600
0
mV
VINDCDC1/2 = 2.5 V to 6 V
0 mA < IO = < IO(max)
Mode = GND, PFM operation
-2%
-1%
2%
1%
DC output voltage
accuracy
DCDC1,
DCDC2(1)
VO
VINDCDC1/2 = 2.5 V to 6 V
0 mA < IO = < IO(max)
0
Mode = VI, PWM operation
IO = 1 mA, Mode = GND, VO = 1.3 V,
Bandwith = 20 MHz
∆VO
Power save mode ripple voltage(2)
25
mVPP
tStart
Start-up time
time from active EN to Start switching
time to ramp from 5% to 95% of VO
Input voltage at threshold pin rising
170
750
100
32
µs
µs
tRamp
VOUT Ramp up Time
RESET delay time
80
26
120
38
ms
ms
V
PB-ONOFF debounce time
RESET, PB_OUT output low voltage
RESET, PB_OUT sink current
VOL
IOL
IOL = 1 mA, Vhysteresis < 1 V, Vthreshold < 1 V
0.2
1
10
1
mA
RESET, PB_OUT output leakage
current
After PB_IN has been pulled high once; Vthreshold
> 1 V and Vhysteresis > 1 V, VOH = 6 V
nA
V
Vth
Vthreshold, Vhysteresis threshold
0.98
1.5
1.02
6.5
VLDO1, VLDO2, VLDO3 and VLDO4 Low Dropout Regulators
Input voltage range for LDO1, LDO2,
LDO3, LDO4
VI
V
VO
LDO1 output voltage range
LDO2 output voltage range
LDO3 output voltage range
LDO4 output voltage range
TPS65050, TPS65052 only
TPS65050, TPS65052 only
TPS65050, TPS65052 only
TPS65050, TPS65052 only
1.2
1.8
1.1
1.2
3.3
3.3
V
V
V
V
3.3
2.85
Feedback voltage for FB_LDO1,
FB_LDO2, FB_LDO3, and FB_LDO4
V(FB)
IO
TPS65051, TPS65054 and TPS65056 only
1
V
Maximum output current for LDO1,
LDO2
400
200
mA
mA
Maximum output current for LDO3,
LDO4
I(SC)
LDO1 short-circuit current limit
LDO2 short-circuit current limit
VLDO1 = GND
VLDO2 = GND
750
850
mA
mA
LDO3 and LDO4 short-circuit current
limit
VLDO3 = GND, VLDO4 = GND
420
mA
Dropout voltage at LDO1
Dropout voltage at LDO2
Dropout voltage at LDO3, LDO4
IO = 400 mA, VINLDO = 3.4 V
IO = 400 mA, VINLDO = 1.8 V
IO = 200 mA, VINLDO = 1.8 V
400
280
280
mV
mV
mV
Leakage current from VinLDOx to
VLDOx
LDO enabled, VINLDO = 6.5 V, VO = 1 V,
at TA = 140°C
Ilkg
VO
3
µA
Output voltage accuracy for LDO1,
LDO2, LDO3, LDO4
IO = 10 mA
-2%
-1%
-1%
1%
1%
1%
VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5V,
VINLDO3,4 = VLDO3,4 + 0.5 V (min. 2.5 V) to 6.5V,
IO = 10 mA
Line regulation for LDO1, LDO2,
LDO3, LDO4
Load regulation for LDO1, LDO2,
LDO3, LDO4
IO = 0 mA to 400 mA for LDO1, LDO2
IO = 0 mA to 200 mA for LDO3, LDO4
Regulation time for LDO1, LDO2,
LDO3, LDO4
Load change from 10% to 90%
10
70
µs
PSRR
Power supply rejection ratio
f = 10 kHz; IO = 50 mA; VI = VO + 1 V
dB
(1) Output voltage specification does not include tolerance of external voltage programming resistors.
(2) In Power Save Mode, operation is typically entered at IPSM = VI / 32 Ω.
5
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ELECTRICAL CHARACTERISTICS (continued)
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 µH, CO = 10 µF. TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal discharge resistor at VLDO1,
VLDO2, VLDO3, VLDO4
R(DIS)
active when LDO is disabled
350
R
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
140
20
°C
°C
Thermal shutdown hysteresis
6
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SLVS710–JANUARY 2007
PIN ASSIGNMENTS
RSM PACKAGE
(TOP VIEW)
EN_DCDC1
EN_DCDC2
EN_LDO1
EN_LDO2
VINLDO1
EN_LDO4
EN_LDO3
EN_DCDC1
EN_DCDC2
EN_LDO1
EN_LDO2
VINLDO1
EN_LDO4
EN_LDO3
PB_OUT
DEFLDO4
VLDO4
TPS65051
TPS65054
TPS65056
TPS65050
RESET
FB4
VLDO4
VLDO1
FB1
VINLDO3/4
VLDO3
FB3
VLDO1
DEFLDO1
MODE
VINLDO3/4
VLDO3
MODE
DEFLDO3
EN_DCDC1
EN_LDO4
EN_LDO3
RESET
EN_DCDC2
EN_LDO1
EN_LDO2
VINLDO1
TPS65052
DEFLDO4
VLDO4
VLDO1
DEFLDO1
MODE
VINLDO3/4
VLDO3
DEFLDO3
TERMINAL FUNCTIONS
TERMINAL
TPS65050 TPS65051 TPS65052 TPS65054 TPS65056
I/O
DESCRIPTION
NAME
Power supply for digital and analog circuitry of DCDC1, DCDC2
and LDOs. This pin must be connected to the same voltage supply
as VINDCDC1/2.
VCC
3
3
3
3
3
I
I
Input to adjust output voltage of converter 1 between 0.6 V and VI.
Connect external resistor divider between VOUT1, this pin, and
GND.
FB_DCDC1
24
24
24
24
24
Select between Power Safe Mode and forced PWM Mode for
DCDC1 and DCDC2. In Power Safe Mode, PFM is used at light
loads, PWM for higher loads. If PIN is set to high level, forced
PWM Mode is selected. If Pin has low level, then the device
operates in Power Safe Mode.
MODE
32
32
32
32
32
I
Input voltage for VDCDC1 and VDCDC2 step-down converter.
VINDCDC1/2
VDCDC2
21
18
21
18
21
18
21
18
21
18
I
I
This must be connected to the same voltage supply as VCC
.
Feedback voltage sense input, connect directly to the output of
converter 2.
TPS65050 and TPS65051: Feedback pin for converter 2. Connect
DEFDCDC2 to the center of the external resistor divider.
TPS65052 and TPS65056: Select pin of converter 2 output
voltage.
High = 1.3 V, Low = 1 V
TPS65054: Select pin of converter 2 output voltage.
High = 1.05 V, Low = 1.3 V
DEFDCDC2
L1
17
22
17
22
17
22
17
22
17
22
I
O
Switch pin of converter 1. Connected to Inductor .
7
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SLVS710–JANUARY 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
TPS65050 TPS65051 TPS65052 TPS65054 TPS65056
I/O
DESCRIPTION
NAME
PGND1
PGND2
AGND
23
19
2
23
19
2
23
19
2
23
19
2
23
19
2
I
I
GND for converter 1
GND for converter 2
I
Analog GND, connect to PGND and PowerPad™
Switch Pin of converter 2. Connected to Inductor.
Enable Input for converter 1, active high
Enable Input for converter 2, active high
Input voltage for LDO1
L2
20
25
26
29
4
20
25
26
29
4
20
25
26
29
4
20
25
26
29
4
20
25
26
29
4
O
I
EN_DCDC1
EN_DCDC2
VINLDO1
VINLDO2
VINLDO3/4
VLDO1
I
I
I
Input voltage for LDO2
11
30
5
11
30
5
11
30
5
11
30
5
11
30
5
I
Input voltage for LDO3 and LDO4
Output voltage of LDO1
O
O
O
O
VLDO2
Output voltage of LDO2
VLDO3
10
12
10
12
10
12
10
12
10
12
Output voltage of LDO3
VLDO4
Output voltage of LDO4
Digital input, used to set the default output voltage of LDO1 to
LDO4; LSB
DEFLDO1
FB1
31
--
--
31
--
31
--
--
31
--
--
31
--
I
I
I
I
I
I
I
I
I
Feedback input for the external voltage divider.
Digital input, used to set the default output voltage of LDO1 to
LDO4.
DEFLDO2
FB2
6
6
--
6
--
6
6
Feedback input for the external voltage divider.
Digital input, used to set the default output voltage of LDO1 to
LDO4.
DEFLDO3
FB3
9
--
9
--
--
--
9
--
9
9
Feedback input for the external voltage divider.
Digital input, used to set the default output voltage of LDO1 to
LDO4; MSB
DEFLDO4
FB4
13
--
--
13
--
--
--
13
27
13
27
13
27
Feedback input for the external voltage divider.
Enable input for LDO1. Logic high enables the LDO, logic low
disables the LDO.
EN_LDO1
27
27
Enable input for LDO2. Logic high enables the LDO, logic low
disables the LDO.
EN_LDO2
EN_LDO3
EN_LDO4
28
15
16
28
15
16
28
15
16
28
15
16
28
15
16
I
I
I
Enable input for LDO3. Logic high enables the LDO, logic low
disables the LDO.
Enable input for LDO4. Logic high enables the LDO, logic low
disables the LDO.
THRESHOLD
PB_IN
--
7
7
--
7
--
7
--
7
--
I
I
Reset input
Input for the pushbutton ON-OFF function
Input for hysteresis on reset threshold
Connect to GND
HYSTERESIS
GND
--
8
8
8
8
8
I
--
--
--
--
-
RESET
--
14
14
14
14
O
Open drain active low reset output, 100 ms reset delay time.
Open drain output. Active low after the supply voltage (VCC
)
PB_OUT
14
--
--
--
--
O
I
exceeded the undervoltage lockout threshold. The pin can be
toggled pulling PB_IN high.
BP
1
1
1
1
1
Input for bypass capacitor for internal reference.
Connect to GND
PowerPAD™
--
--
--
--
--
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FUNCTIONAL BLOCK DIAGRAM
TPS65050
VINDCDC1/2
1 W
Vbat
VCC
10 mF
1 mF
2.2 mH
L1
DCDC1 (I/O)
Cff
R1
EN_DCDC1
ENABLE
MODE
FB_DCDC1
STEP-DOWN
CONVERTER
600 mA
10 mF
PGND1
R2
DEFLDO1
DEFLDO2
DEFLDO3
DEFLDO4
Interface
L2
2.2 mH
DCDC2 (core)
R3
R4
VDCDC2
DEFDCDC2
PGND2
10 mF
STEP-DOWN
CONVERTER
600 mA
EN_DCDC2
ENABLE
VLDO1
VIN_LDO1
EN_LDO1
VLDO1
VIN
4.7 mF
4.7 mF
2.2 mF
2.2 mF
400-mA LDO
ENABLE
VIN_LDO2
EN_LDO2
VLDO2
VIN
VLDO2
ENABLE
400-mA LDO
VIN_LDO3/4
EN_LDO3
VIN
VLDO3
VLDO3
BP
200-mA LDO
ENABLE
0.1 mF
EN_LDO4
VLDO4
VLDO4
ENABLE
Vbat
200-mA LDO
I/Ovoltage
R19
PB_OUT
default
turned on
Flipflop with
32-ms debounce
PB_IN
AGND
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TPS65051
VINDCDC1/2
1 W
Vbat
VCC
22 mF
1 mF
2.2 mH
L1
DCDC1 (I/O)
Cff
EN_DCDC1
R1
R2
ENABLE
FB_DCDC1
PGND1
STEP-DOWN
CONVERTER
1 A
10 mF
MODE
L2
2.2 mH
DCDC2 (core)
VDCDC2
R3
R4
10 mF
STEP-DOWN
CONVERTER
600 mA
EN_DCDC2
DEFDCDC2
PGND2
ENABLE
VLDO1
FB1
VIN_LDO1
EN_LDO1
VLDO1
VIN
4.7 mF
R5
R6
400-mA LDO
ENABLE
VIN_LDO2
EN_LDO2
VLDO2
FB2
VIN
VLDO2
ENABLE
R7
R8
4.7 mF
400-mA LDO
VIN_LDO3/4
EN_LDO3
VIN
VLDO3
FB3
VLDO3
R9
2.2 mF
200-mA LDO
ENABLE
BP
R10
0.1 mF
EN_LDO4
VLDO4
ENABLE
VLDO4
FB4
200-mA LDO
2.2 mF
R11
R12
I/Ovoltage
R19
THRESHOLD
HYSTERESIS
RESET
RESET
AGND
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TPS65052
VINDCDC1/2
1 W
Vbat
VCC
10 mF
1 mF
3.3 mH
L1
DCDC1 (I/O)
EN_DCDC1
FB_DCDC1
ENABLE
STEP-DOWN
CONVERTER
1 A
10 mF
PGND1
MODE
DEFLDO1
DEFLDO2
DEFLDO3
DEFLDO4
Interface
L2
DCDC2 (core)
2.2 mH
VDCDC2
10 mF
STEP-DOWN
CONVERTER
600 mA
EN_DCDC2
DEFDCDC2
ENABLE
1 V/1.3 V
PGND2
VLDO1
VIN_LDO1
EN_LDO1
VLDO1
VIN
4.7 mF
400-mA LDO
ENABLE
VIN_LDO2
EN_LDO2
VLDO2
VIN
VLDO2
ENABLE
4.7 mF
400-mA LDO
VIN_LDO3/4
EN_LDO3
VIN
VLDO3
VLDO3
BP
2.2 mF
200-mA LDO
ENABLE
0.1 mF
EN_LDO4
VLDO4
RESET
VLDO4
ENABLE
2.2 mF
200-mA LDO
I/Ovoltage
R19
THRESHOLD
HYSTERESIS
RESET
AGND
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TPS65054
VINDCDC1/2
1 W
Vbat
VCC
22 mF
1 mF
2.2 mH
L1
DCDC1 (I/O)
Cff
EN_DCDC1
R1
R2
ENABLE
FB_DCDC1
PGND1
STEP-DOWN
CONVERTER
600 mA
10 mF
MODE
L2
DCDC2 (core)
2.2 mH
VDCDC2
PGND2
10 mF
STEP-DOWN
CONVERTER
600 mA
EN_DCDC2
DEFDCDC2
ENABLE
1.3 V/1.05 V
VLDO1
FB1
VIN_LDO1
EN_LDO1
VLDO1
VIN
4.7 mF
R5
R6
400-mA LDO
ENABLE
VIN_LDO2
EN_LDO2
VLDO2
FB2
VIN
VLDO2
ENABLE
R7
R8
4.7 mF
400-mA LDO
VIN_LDO3/4
EN_LDO3
VIN
VLDO3
VLDO3
R9
2.2 mF
FB3
BP
200-mA LDO
ENABLE
R10
0.1 mF
EN_LDO4
VLDO4
ENABLE
VLDO4
FB4
200-mA LDO
2.2 mF
R11
R12
I/Ovoltage
R19
THRESHOLD
HYSTERESIS
RESET
RESET
AGND
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TPS65056
VINDCDC1/2
1 W
Vbat
VCC
22 mF
1 mF
3.3 mH
L1
DCDC1 (I/O)
EN_DCDC1
ENABLE
FB_DCDC1
STEP-DOWN
CONVERTER
1 A
10 mF
PGND1
MODE
L2
2.2 mH
DCDC2 (core)
VDCDC2
10 mF
STEP-DOWN
CONVERTER
600 mA
EN_DCDC2
DEFDCDC2
ENABLE
PGND2
VLDO1
1 V / 1.3 V
VIN_LDO1
EN_LDO1
VLDO1
VIN
4.7 mF
4.7 mF
2.2 mF
R5
R6
FB1
400-mA LDO
ENABLE
VIN_LDO2
EN_LDO2
VLDO2
FB2
VIN
VLDO2
ENABLE
R7
R8
400-mA LDO
VIN_LDO3/4
EN_LDO3
VIN
VLDO3
VLDO3
R9
FB3
BP
200-mA LDO
ENABLE
R10
0.1 mF
EN_LDO4
VLDO4
ENABLE
VLDO4
FB4
200-mA LDO
2.2 mF
R11
R12
I/Ovoltage
R19
THRESHOLD
HYSTERESIS
RESET
RESET
AGND
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency converter 1
vs Output current
vs Output current
vs Output current
vs Output current
PWM/PFM mode = low
PWM mode = high
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Efficiency converter 2
Efficiency converter 1
Efficiency converter 2
Output voltage ripple
Output voltage ripple
DCDC1 startup timing
LDO1 to LDO4 startup timing
DCDC1 load transient response
DCDC1 load transient response
DCDC2 load transient response
DCDC2 load transient response
DCDC1 line transient response
DCDC2 line transient response
LDO1 load transient response
LDO4 load transient response
LDO1 line transient response
Power supply rejection ratio
PWM mode = high
PFM mode = low
PWM mode = high
PFM mode = low
vs Frequency
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
90
80
80
70
3.8 V
5 V
4.2 V
70
3.8 V
5 V
60
50
40
30
20
60
50
40
30
20
3.4 V
3.4 V
4.2 V
V
T
= 3.3 V
= 25oC
V
T
= 3.3 V
= 25oC
O
O
A
A
10
10
PWM Mode
PWM/PFM Mode
0
0.0001
0
0.0001
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
I
− Output Current − A
I
− Output Current − A
O
O
Figure 1.
Figure 2.
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
90
3.3 V
V
T
= 1.3 V
= 25oC
O
A
PWM Mode
80
70
60
50
40
30
20
80
70
60
50
40
30
20
3.8 V
3.8 V
4.2 V
5 V
3.3 V
5 V
4.2 V
V
O
= 1.3 V
= 25oC
T
A
PFM Mode
10
10
0
0
0.0001
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
I
− Output Current − A
I
− Output Current − A
O
O
Figure 3.
Figure 4.
OUTPUT VOLTAGE RIPPLE
PWM/PFM MODE = LOW
OUTPUT VOLTAGE RIPPLE
PWM MODE = HIGH
V
= 4.2 V,
T
= 25oC
A
CH1 (VDCDC1 = 3.3 V)
= 25oC
A
I
V
= 4.2 V,
T
CH1 (VDCDC1 = 3.3 V)
I
CH1 (VDCDC2 = 1.5 V)
CH2 (VDCDC2 = 1.5 V)
CH3 (I DCDC2 = 600 mA)
L
CH3 (I DCDC2 = 80 mA)
L
CH4 (I DCDC1 = 600 mA)
L
CH4 (I DCDC1 = 80 mA)
L
t − Time = 500 ns/div
Figure 6.
t − Time = 2 ms/div
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
DCDC1 STARTUP TIMING
LDO1 TO LDO4 STARTUP TIMING
CH1 (EN)
CH4 (VLDO1)
EN
CH1 (VLDO1)
CH2 (VLDO2)
V
T
= 3.6 V
= 25oC
I
A
Mode = Low
CH3 (VLDO3)
CH4 (VLDO4)
CH3
(VDCDC2 = 1.5 V)
V
T
= 3.6 V
= 25oC
I
A
CH2
(VDCDC1 = 3.3 V)
Load DCDC1 = 600 mA
Load DCDC2 = 600 mA
ILDO1/2/3/4 = 100 mA
Mode = Low
t − Time = 200 ms/div
Figure 7.
DCDC1 LOAD TRANSIENT RESPONSE
t − Time = 20 ms/div
Figure 8.
DCDC1 LOAD TRANSIENT RESPONSE
CH1 (VDCDC1)
CH1 (VDCDC1)
V
T
= 4.2 V
= 25oC
I
V
T
= 4.2 V
= 25oC
I
A
A
Mode = Low
Mode = High
CH2
I(DCDC1)
CH2
I(DCDC1)
VDCDC1 = 3.3 V
ENDCDC1 = High
ENDCDC2 = Low
VDCDC1 = 3.3 V
ENDCDC1 = High
ENDCDC2 = Low
Load Current = 60 mA to 540 mA
t − Time = 100 ms/div
Figure 9.
Load Current = 60 mA to 540 mA
t − Time = 100 ms/div
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
DCDC2 LOAD TRANSIENT RESPONSE
DCDC2 LOAD TRANSIENT RESPONSE
CH1 (VDCDC2)
CH1 (VDCDC2)
V
T
= 3.6 V
= 25oC
I
V
T
= 3.6 V
= 25oC
I
A
A
Mode = High
Mode = Low
CH2
I(DCDC2)
CH2
I(DCDC2)
VDCDC2 = 1.5 V
ENDCDC1 = Low
ENDCDC2 = High
VDCDC2 = 1.5 V
ENDCDC1 = Low
ENDCDC2 = High
Load Current = 60 mA to 540 mA
t − Time = 100 ms/div
Figure 12.
Load Current = 60 mA to 540 mA
t − Time = 100 ms/div
Figure 11.
DCDC1 LINE TRANSIENT RESPONSE
DCDC2 LINE TRANSIENT RESPONSE
CH1
VIN (VDCDC1)
CH1
VIN (VDCDC2)
V
T
= 3.6 V to 4.5 V to 3.6 V
= 25oC
I
A
Mode = High
VDCDC1 = 3.3 V
ENDCDC1 = High
ENDCDC2 = Low
Load Current = 600 mA
CH2 (VDCDC2)
CH2 (VDCDC1)
VDCDC2 = 1.5 V
V
T
= 3.4 V to 4.4 V to 3.4 V
= 25oC
I
ENDCDC1 = Low
ENDCDC2 = High
Load Current = 600 mA
A
Mode = High
t − Time = 100 ms/div
Figure 14.
t − Time = 100 ms/div
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
LDO1 LOAD TRANSIENT RESPONSE
LDO4 LOAD TRANSIENT RESPONSE
CH1 (VLDO4)
CH1 (VLDO1)
V
= 3.6 V
I
V
T
= 3.6 V
= 25oC
I
VLDO4 = 1.3 V
VLDO4 = 20 mA to 180 mA
= 25oC
A
VLDO1 = 3.3 V
VLDO1 = 40 mA to 360 mA
T
A
CH2
I(LDO4)
CH2
I(LDO1)
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 15.
Figure 16.
POWER SUPPLY REJECTION RATIO
vs
LDO1 LINE TRANSIENT RESPONSE
FREQUENCY
100
90
CH1
VIN (LDO1)
80
70
60
50
40
30
20
CH2 (VLDO1)
V
T
= 3.6 V to 4.2 V to 3.6 V
= 25oC
I
A
VLDO1 = 3.3 V
VLDO1 = 100 mA
Mode = High
10
0
t − Time = 100 ms/div
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 17.
Figure 18.
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DETAILED DESCRIPTION
Operation
The TPS6505x include each two synchronous step-down converters. The converters operate with 2.25-MHz
(typical) fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load
currents, the converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency
Modulation).
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on, and the inductor current ramps up until the current comparator trips, and the control logic turns off the
switch. The current limit comparator turns off the switch if the current limit of the P-channel switch is exceeded.
After the adaptive dead time, which prevents shoot through current, the N-channel MOSFET rectifier is turned
on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the N-channel
rectifier, and turning on the on the P-channel switch.
The two DC/DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase
shift between converter 1 and converter 2 decreases the input RMS current. Therefore, smaller input capacitors
can be used.
DCDC1 Converter
The converter 1 output voltage is set by an external resistor divider connected to FB_DCDC1 pin for TPS65050,
TPS65051 and TPS65054. For TPS65052, the output voltage is fixed to 3.3 V and this pin needs to be directly
connected to the output. See the Application Information section for more details. The maximum output current
on DCDC1 is 600 mA for TPS65050 and TPS65054. For TPS65051, TPS65052 and TPS65056, the maximum
output current is 1 A.
DCDC2 Converter
The VDCDC2 pin must be directly connected to the DCDC2 converter output voltage. The DCDC2 converter
output voltage is selected via the DEFDCDC2 pin.
TPS65050 and TPS65051: The output voltage is set with an external resistor divider. Connect the DEFDCDC2
pin to the external resistor divider.
TPS65052, TPS65054 and TPS65056: The DEFDCDC2 pin can either be connected to GND, or to VCC. The
converter 2 output voltage defaults to:
Device
TPS65052 , TPS65056
TPS65054
DEFDCDC2 = low
DEFDCDC2 = high
1.3 V
1 V
1.3 V
1.05 V
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Power-Save Mode
The Power Save Mode is enabled with the Mode pin set to 0. If the load current decreases, the converters
enters Power Save Mode operation automatically. During Power Save Mode, the converters operate with
reduced switching frequency in PFM mode, and with a minimum quiescent current to maintain high efficiency.
The converter positions the output voltage 1% above the nominal output voltage. This voltage positioning feature
minimizes voltage drops caused by a sudden load step.
To optimize the converter efficiency at light load, the average current is monitored. If in PWM mode, the inductor
current remains below a certain threshold, then Power Save Mode is entered. The typical threshold is calculated
according to Equation 1:
VINDCDC
I(PFM_enter)
=
32 W
(1)
(2)
A. Average output current threshold to enter PFM mode.
VINDCDC
I(PSMDCDC_leave)
=
24 W
A. Average output current threshold to leave PFM mode.
During the Power Save Mode, the output voltage is monitored with a comparator. As the output voltage falls
below the skip comparator threshold (skip comp), the P-channel switch turns on, and the converter effectively
delivers a constant current. If the load is below the delivered current, the output voltage rises until the skip comp
threshold is crossed again, then all switching activity ceases, reducing the quiescent current to a minimum until
the output voltage has dropped below the threshold. If the load current is greater than the delivered current, the
output voltage falls until it crosses the skip comparator low (Skip Comp Low) threshold set to 1% below nominal
VO, then Power Save Mode is exited, and the converter returns to PWM mode
These control methods reduce the quiescent current to 12 µA per converter, and the switching frequency to a
minimum achieving the highest converter efficiency. The PFM mode operates with low output voltage ripple. The
ripple depends on the comparator delay, and the size of the output capacitor; increasing capacitor values
decreases the output ripple voltage.
The Power Save Mode can be disabled by driving the MODE pin high. In forced PWM mode, both converters
operate with fixed frequency PWM mode regardless of the load.
Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is
activated in Power Save Mode operation when the converter runs in PFM Mode. It provides more headroom for
both, the voltage drop at a load step and the voltage increase at a load throw-off. This improves load transient
behavior.
At light loads, in which the converter operate in PFM Mode, the output voltage is regulated typically 1% higher
than the nominal value. In the event of a load transient from light load to heavy load, the output voltage drops
until it reaches the skip comparator low threshold set to -1% below the nominal value and enters PWM mode.
During a release from heavy load to light load, the voltage overshoot is also minimized due to active regulation
turning on the N-channel switch.
Smooth
Increased Load
Fast Load Transient
+1%
OUT_NOM
-1%
PFM Mode
Light Load
PFM Mode
Light Load
V
PFM Mode
Medium/Heavy Load
PFM Mode
Medium/Heavy Load
COMP_LOW Threshold
Figure 19. Dynamic Voltage Positioning
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Soft Start
The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft
start, the output voltage ramp up is controlled as shown in Figure 20.
EN
95%
5%
V
OUT
t
t
RAMP
Start
Figure 20. Soft Start
100% Duty Cycle Low Dropout Operation
The converters offer a low input to output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range. (i.e. The minimum input voltage to maintain regulation depends on the load current and output
voltage) and can be calculated as:
VI (min) = VO (max) + IO (max) x (rDS(on) (max) + RL)
(3)
with:
•
•
•
•
IO max = maximum output current plus inductor ripple current
rDS(on) max = maximum P-channel switch rDS(on)
.
RL = DC resistance of the inductor
VO (max) = nominal output voltage plus maximum output voltage tolerance
Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery and disables all internal circuitry. The undervoltage lockout threshold, sensed
at the VCC pin is typically 1.8 V, max 2 V.
Mode Selection
The MODE pin allows mode selection between forced PWM Mode and power Safe Mode for both converters.
Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters
operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
maintaining high efficiency over a wide load current range.
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Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load
currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the
switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power
save mode during light loads. For additional flexibility, it is possible to switch from power save mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the
converter to the specific system requirements.
Enable
To start up each converter independently, the device has a separate enable pin for each DC/DC converter and
for each LDO. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4 are set to high, the
corresponding converter starts up with soft start as previously described.
Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the
electrical characteristics. In this mode, the P and N-Channel MOSFETs are turned-off, the and the entire internal
control circuitry is switched-off. If disabled, the outputs of the LDOs are pulled low by internal 350Ω resistors,
actively discharging the output capacitor. For proper operation, the enable pins must be terminated and must not
be left unconnected.
RESET
The TPS65051, TPS65052, TPS65054 and TPS65056 contain circuitry that can generate a reset pulse for a
processor with a 100 ms delay time. The input voltage at a comparator is sensed at an input called threshold.
When the voltage exceeds the threshold, the output goes high with a 100-ms delay time. A hysteresis can be
defined with an external resistor connected to the hysteresis input. This circuitry is functional as soon as the
supply voltage at VCC exceeds the undervoltage lockout threshold. Therefore, the TPS6505x has a shutdown
current (all DCDC converters and LDOs are off) of 9 µA in order to supply bandgap and comparator.
Vbat
HYSTERESIS
RESET
THRESHOLD
+
100 ms
Delay
-
V
= 1 V
ref
Vbat
THRESHOLD
THRESHOLD - HYSTERESIS
Comparator
Output (Internal)
t
NRESET
RESET
Figure 21. RESET Pulse Circuit
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Push-Button ON-OFF (PB-ON-OFF)
The TPS65050 provides a PB-ON-OFF functionality instead of supervising a voltage with the threshold and
hysteresis inputs. The output at PB_OUT is held low after voltage is applied at VCC. Only after the input at PB-IN
is pulled high once, the output driver at PB_OUT goes to its inactive state, driven high with its external pullup
resistor. Further low-high pulses at PB-IN toggles the status of the PB_OUT output, and can be used to
shutdown and start the converter with a single push on a button by connecting the PB_OUT output to the enable
input of the converters.
Vbat
PB_OUT
JK-
PB_IN
Debounce
32 ms
Flipflop
Default
Low
Min Pulse
Width 32 ms
PB_IN
RESPWRON
32 ms
Figure 22. Push-Button Circuit
Short-Circuit Protection
All outputs are short-circuit protected with a maximum output current as defined in the Electrical Characteristics.
Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typically) for the DC/DC converters, the device goes
into thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues its
operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown
for one of the DC/DC converters disables both converters simultaneously.
The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore, a LDO which may be
used to power an external voltage never heats up the chip high enough to turn off the DC/DC converters. If one
LDO exceeds the thermal shutdown temperature, all LDOs turns off simultaneously.
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Low Dropout Voltage Regulators
The low dropout voltage regulators are designed to operate well with small ceramic input and output capacitors.
They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 280 mV at rated
output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, ENLDO2,
EN_LDO3 and EN_LDO4 pin. In TPS65050 and TPS65052, the output voltage of the LDOs is set using 4 pins.
The DEFLDO1 to DEFLDO4 pins can either be connected to GND or Vbat (VCC) to define a set of output
voltages for LDO1 to LDO4 according to table 1. Connecting the DEFLDOx pins to a voltage different from GND
or VCC causes increased leakage current into VCC. In TPS65051 and TPS65054, the output voltage of the LDOs
is set using external resistor dividers.
TPS65050 and TPS65052 default voltage options adjustable with DEFLDO4…DEFLDO1 according to Table 1.
Table 1. Default Options
DEFLDO1
DEFLDO2
DEFLDO3
DEFLDO4
VLDO1
VLDO2
VLDO3
VLDO4
400 mA LDO
400 mA LDO
200 mA LDO
200 mA LDO
1.8 V - 5.5 V
Input
1.8 V - 5.5 V
Input
1.5 V - 5.5 V
Input
1.5 V - 5.5 V
Input
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.85 V
2.7 V
2.5 V
2.5 V
1.85 V
1.8 V
1.2 V
3.3 V
3.3 V
1.85 V
1.5 V
1.85 V
1.5 V
2.7 V
2.5 V
1.85 V
1.85 V
1.5 V
1.3 V
1.3 V
1.85 V
1.2 V
1.5 V
1.3 V
1.35 V
2.85 V
1.3 V
2.85 V
2.85 V
2.85 V
2.85 V
2.85 V
2.85 V
2.85 V
2.85 V
3.3 V
2.85 V
2.85 V
2.85 V
1.85 V
1.5 V
1.5 V
1.1 V
1.85 V
1.2 V
3.3 V
1.5 V
3.3 V
1.5 V
1.85 V
2.5 V
1.35 V
3.3 V
1.8 V
1.1 V
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APPLICATION INFORMATION
Output Voltage Setting
Converter 1 (DCDC1)
The output voltage of converter 1 can be set by an external resistor network. The output voltage can be
calculated using Equation 4.
R1
VO = Vref
x
1 +
(
)
R2
(4)
with an internal reference voltage Vref, 0.6 V .
Setting the total resistance of R1 + R2 to less than 1 MΩ is recommended. The resistor network connects to the
input of the feedback amplifier, therefore, requiring a small feedforward capacitor in parallel to R1. A typical
value of 47 pF is sufficient.
Converter 2 (DCDC2)
The output voltage of converter 2 can be selected as following:
•
Adjustable output voltage defined with external resistor network on pin DEFDCDC2. This option is available
for TPS65050 and TPS65051.
•
Two default fixed output voltages selectable by pin DEFDCDC2, see Table 2. This option is available for
TPS65052 and TPS65054.
Table 2. Default Fixed Output Voltages
Converter 2
TPS65050
TPS65051
TPS65052
TPS65054
TPS65056
DEFDCDC2 = low
DEFDCDC2 = high
--
--
--
--
1 V
1.3 V
1 V
1.3 V
1.05 V
1.3 V
The adjustable output voltage can be calculated similar to the DCDC1 converter. Setting the total resistance of
R3 + R4 to less than 1 MΩ is recommended. Route the DEFDCDC2 line separate from noise sources, such as
the inductor or the L2 line. The VDCDC2 line needs to be directly connected to the output capacitor. As the
VDCDC2 line is the feedback to the internal amplifier, no feedforward capacitor at R3 is needed.
Using an external resistor divider at DEFDCDC2:
1 W
V
Vbat
CC
1 mF
VDCDC2
L2
V
O
VINDCDC1/2
ENDCDC2
L
C
I
C
O
R3
R4
DEFDCDC2
AGND PGND
Figure 23. External Resistor Divider
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V(DEFDCDC2) = 0.6 V
R3 + R4
VO
VO = V(DEFDCDC2)
x
R3 = R4 x
- R4
V(DEFDCDC2)
R4
(5)
See Table 3 for typical resistor values:
Table 3. Typical Resistor Values
OUTPUT VOLTAGE
R1
R2
NOMINAL VOLTAGE
Typical CFF
3.3 V
3 V
680 kΩ
510 kΩ
560 kΩ
510 kΩ
300 kΩ
200 kΩ
300 kΩ
330 kΩ
150 kΩ
130 kΩ
150 kΩ
160 kΩ
150 kΩ
120 kΩ
200 kΩ
330 kΩ
3.32 V
2.95 V
2.84 V
2.51 V
1.8 v
47 pF
47 pF
47 pF
47 pF
47 pF
47 pF
47 pF
47 pF
2.85 V
2.5 V
1.8 V
1.6 V
1.5 V
1.2 V
1.6 V
1.5 V
1.2 V
Output Filter Design (Inductor and Output Capacitor)
Inductor Selection
The two converters operate with 2.2-µH output inductor. Larger or smaller inductor values can be used to
optimize the performance of the device for specific operation conditions. The selected inductor has to be rated
for its dc resistance and saturation current. The dc resistance of the inductance directly influences the efficiency
of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest efficiency. The
minimum inductor value is 1.5 µH, but an output capacitor of 22 µF minimum is needed in this case. For an
output voltage above 2.8 V, an inductor value of 3.3 µH minimum is recommended. Lower values result in an
increased output voltage ripple in PFM mode.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 6. This is
recommended because during heavy load transient the inductor current rises above the calculated value.
VO
1 -
VI
DIL
DIL = VO
x
IL(max) = IO (max) +
2
L x ¦
(6)
with:
•
•
•
•
f = Switching Frequency (2.25-MHz typical)
L = Inductor Value
∆ IL= Peak-to-peak inductor ripple current
ILmax = Maximum Inductor current
The highest inductor current occurs at maximum VI. Open core inductors have a soft saturation characteristic,
and they can normally handle higher inductor currents versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Consideration must be given to the difference in the core material from inductor to
inductor which has an impact on the efficiency especially at high switching frequencies. See Table 4 and the
typical applications for possible inductors.
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Table 4. Tested Inductors
Inductor Type
LPS3010
Inductor Value
2.2 µH
Supplier
Coilcraft
Coilcraft
Coilcraft
TDK
LPS3015
3.3 µH
LPS4012
2.2 µH
VLF4012
2.2 µH
Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the two converters allow the use of small
ceramic capacitors with a value of 22-µF (typical), without having large output voltage undershoots and
overshoots during heavy load transients. Ceramic capacitors having low ESR values result in lowest output
voltage ripple, and are recommended.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. For completeness, the RMS ripple current is calculated as:
VO
1 -
VI
1
x
I(RMSCout) = VO
x
2 x Ö3
L x ¦
(7)
At nominal load current, the inductive converters operate in PWM mode, and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
VO
1 -
VI
1
8 x CO x ¦
x
+ ESR
DVO = VO
x
L x ¦
(8)
Where the highest output voltage ripple occurs at the highest input voltage VI.
At light load currents, the converters operate in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The converters need a ceramic input capacitor of 10 µF. The input capacitor can be increased
without any limit for better input voltage filtering.
Table 5. Possible Capacitors
Capacitor Value
2.2 µF
Size
0805
0805
0805
0805
0603
Supplier
Type
TDK C2012X5R0J226MT
Taiyo Yuden JMK212BJ226MG
Taiyo Yuden JMK212BJ106M
TDK C2012X5R0J106M
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
2.2 µF
10 µF
10 µF
10 µF
Taiyo Yuden JMK107BJ106MA
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Low Drop Out Voltage Regulators (LDOs)
The output voltage of all 4 LDOs in TPS65051, TPS65054 and TPS65056 are set by an external resistor
network. The output voltage is calculated using Equation 9:
R5
VO = Vref
x
1 +
(
)
R6
(9)
with an internal reference voltage, Vref, 1 V (typical)
Setting the total resistance of R5 + R6 to less than 1 MΩ is recommended. Typically, there is no feedforward
capacitor needed at the voltage dividers for the LDOs.
VO
R5 + R6
VO = V(FB_LDOs)
x
R5 = R6 x
- R6
V(FB_LDOs)
R6
(10)
Typical resistor values:
Table 6. Typical Resistor Values
OUTPUT VOLTAGE
R5
R6
NOMINAL VOLTAGE
3.3 V
3 V
300 kΩ
300 kΩ
240 kΩ
260 kΩ
300 kΩ
240 kΩ
150 kΩ
36 kΩ
130 kΩ
150 kΩ
130 kΩ
200 kΩ
200 kΩ
300 kΩ
300 kΩ
120 kΩ
510 kΩ
330 kΩ
3.31 V
3 V
2.85 V
2.8 V
2.5 V
1.8 V
1.5 V
1.3 V
1.2 V
1.1 V
2.85 V
2.8 V
2.5 V
1.8 v
1.5 V
1.3 V
1.19 V
1.1 V
100 kΩ
33 kΩ
LAYOUT CONSIDERATIONS
Application Circuits
PB-ONOFF and Sequencing
The PB-ONOFF output can be used to enable one or several converters. After power up, the PB_OUT pin is
low, and pulls down the enable pins connected to PB_OUT; EN_DCDC1, and EN_LDO1 in Figure 24. When
PB_IN is pulled to VCC for longer than 32 ms, the PB_OUT pin is turned off, hence the enable pins pulled high
using a pull-up resistor to VCC. This enables the DCDC1 converter and LDO1. The output voltage of DCDC1
(VOUT1) is used as the enable signal for DCDC2 and LDO2 to LDO4. LDO1 with its output voltage of 3.3 V and
LDO2 for an output voltage of 2.5 V are powered from the battery (V(bat)) directly. To save power, the input
voltage for the lower voltage rails at LDO3 and LDO4 are derived from the output of the step-down converters,
keeping the voltage drop at the LDOs low to increase efficiency. As LDO3 and LDO4 are powered from the
output of DCDC1, the total output current on VOUT1, LDO3 and LDO4 must not exceed the maximum rating of
DCDC1.
Figure 25 shows the power up timing for this application.
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LAYOUT CONSIDERATIONS (continued)
1 W
VINDCDC1/2
Vbat
V
Vbat
CC
10 mF
1 mF
2.2 mH
L1
Vout1 = 2.85 V
Cff
FB_DCDC1
MODE
R1
R2
GND
10 mF
DEFLDO1
DEFLDO2
DEFLDO3
DEFLDO4
GND
GND
Vbat
Vbat
PGND1
2.2 mH
L2
Vbat Vbat
TPS65050
Vout2 = 1.575 V
VDCDC2
DEFDCDC2
PGND2
PB_IN
R3
R4
10 mF
PB_OUT
VLDO1
VLDO1 = 3.3 V
4.7 mF
EN_DCDC1
EN_LDO1
VLDO2
VLDO3
VLDO4
VLDO2 = 2.5 V
4.7 mF
VDCDC1
EN_DCDC2
EN_LDO2
EN_LDO3
EN_LDO4
VLDO3 = 1.5 V
2.2 mF
VIN_LDO1
VIN_LDO2
Vbat
Vbat
VLDO4 = 1.3 V
2.2 mF
VIN_LDO3/4
Vout1
BP
AGND
0.1 mF
Figure 24. PB_ON/OFF Circuit
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LAYOUT CONSIDERATIONS (continued)
Vbat
PB_IN
32 ms
EN_DCDC1
EN_LDO1
32 ms
Vout1
1.2V
170 ms
VLDO1
EN_DCDC2
EN_LDO3
EN_LDO4
EN_LDO2
Vout2
VLDO2
VLDO3
170 ms
VLDO4
Figure 25. Power Up Timing
RESET
TPS65051, TPS65052, TPS65054 and TPS65056 contain a comparator that are used to supervise a voltage
connected to an external voltage divider, and generate a reset signal if the voltage is lower than the threshold.
The rising edge is delayed by 100 ms at the open drain RESET output. The values for the external resistors R3
to R5 are calculated as follows:
VL = lower voltage threshold
VH = higher voltage threshold
VREF = reference voltage (1 V)
Example:
•
•
VL = 3.3 V
VH = 3.4 V
Set R5 = 100 kΩ
→ R3 + R4 = 240 kΩ
→ R4 = 3.03 kΩ
→ R3 = 237 kΩ
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LAYOUT CONSIDERATIONS (continued)
VH
R3 + R4 = R5
x
- 1
(
)
Vref
VH - VL
VL
R4 = R5
x
(11)
VINDCDC1/2
1 W
V
CC
Vbat
2.2 mH
2.2 mH
1 mF
L1
Cff
Vout1 = 2.85 V
R1
FB_DCDC1
10 mF
R2
PGND1
TPS65051
L2
2.2 mH
Vout2 = 1.575 V
R3
VDCDC2
Vbat
Vout1
R3
DEFDCDC2
PGND2
10 mF
HYSTERESIS
R4
R4
R5
THRESHOLD
VLDO1
FB1
VLDO1 = 3.3 V
R5
R6
1 MW
4.7 mF
RESET
Vbat
VLDO2
FB2
EN_DCDC1
EN_DCDC2
VLDO2 = 1.8 V
R7
R8
4.7 mF
EN_LDO1
EN_LDO2
EN_LDO3
EN_LDO4
VLDO3
VLDO3 = 1.2 V
R9
FB3
BP
2.2 mF
R10
VIN_LDO1
VIN_LDO2
Vbat
0.1 mF
Vbat
VIN_LDO3/4
Vout1
VLDO4
FB4
VLDO4 = 1.3 V
MODE
R11
R12
Vbat
2.2 mF
AGND
Figure 26. RESET Circuit
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
TPS65050RSMR
TPS65050RSMRG4
TPS65050RSMT
TPS65050RSMTG4
TPS65051RSMR
TPS65051RSMRG4
TPS65051RSMT
TPS65051RSMTG4
TPS65052RSMR
TPS65052RSMRG4
TPS65052RSMT
TPS65052RSMTG4
TPS65054RSMR
TPS65054RSMRG4
TPS65054RSMT
TPS65054RSMTG4
TPS65056RSMR
TPS65056RSMRG4
TPS65056RSMT
TPS65056RSMTG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RSM
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
FRB
FRB
FRB
FRB
FRB
FRB
FRB
FRB
FRB
FRB
Reel
Diameter Width
(mm)
Reel
A0 (mm)
4.3
B0 (mm)
4.3
K0 (mm)
1.5
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
TPS65050RSMR
TPS65050RSMT
TPS65051RSMR
TPS65051RSMT
TPS65052RSMR
TPS65052RSMT
TPS65054RSMR
TPS65054RSMT
TPS65056RSMR
TPS65056RSMT
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
32
32
32
32
32
32
32
32
32
32
330
12
12
12
12
12
12
12
12
12
12
12
12 PKGORN
T2TR-MS
P
330
330
330
330
330
330
330
330
330
12
12
12
12
12
12
12
12
12
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS65050RSMR
TPS65050RSMT
TPS65051RSMR
TPS65051RSMT
TPS65052RSMR
TPS65052RSMT
TPS65054RSMR
TPS65054RSMT
TPS65056RSMR
TPS65056RSMT
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
RSM
32
32
32
32
32
32
32
32
32
32
FRB
FRB
FRB
FRB
FRB
FRB
FRB
FRB
FRB
FRB
342.9
342.9
342.9
342.9
342.9
342.9
342.9
342.9
342.9
342.9
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
20.6
20.6
20.6
20.6
20.6
20.6
20.6
20.6
20.6
20.6
Pack Materials-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
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Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
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