6PAIC3109TWRHMRQ1 [TI]
汽车类低功耗 96kHz 单声道音频编解码器 | RHM | 32 | -40 to 105;
| 型号： | 6PAIC3109TWRHMRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类低功耗 96kHz 单声道音频编解码器 | RHM | 32 | -40 to 105 PC 电信 电信集成电路 编解码器 |
| 文件： | 总122页 (文件大小：2396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV320AIC3109-Q1
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
TLV320AIC3109-Q1 汽车低功耗 96kHz 单声道音频编解码器
1 特性
2 应用
1
•
•
符合汽车应用 要求
具有符合 AEC-Q100 标准的下列特性：
•
•
•
紧急呼叫 (eCall) 系统
远程信息处理控制单元 (TCU)
汽车音响主机
–
–
温度等级 2：-40°C 至 +105°C
人体放电模型 (HBM) 静电放电 (ESD) 分类等级
3 说明
2
TLV320AIC3109-Q1 器件是一款低功耗单声道编解码
器，配备单声道耳机放大器和多个输入输出通道，且在
单端或全差动配置下可编程。该器件包括全面的基于寄
存器的电源控制，可实现 48kHz 数模转换器 (DAC) 回
放，功耗低至
–
组件充电模型 (CDM) ESD 分类等级 C4B
•
•
单声道音频 DAC：
–
–
–
102dBA 信噪比
支持 8kHz 至 96kHz 的采样率
3D、低音、高音、EQ 或去加重效果
14mW，因此非常适合低功耗 应用。
单声道音频 ADC：
–
–
–
92dBA 信噪比
TLV320AIC3109-Q1 的录音路径包含集成式麦克风偏
置、数控麦克风前置放大器、自动增益控制 (AGC)、
灵活的前端多路复用器 (MUX) 和前端模拟混频器
(MIX)。录音过程中，可编程滤波器能够移除可闻噪
声。回放路径包括 MIX 和 MUX 功能（从单声道 DAC
和所选输入，经可编程音量控制至各种输出）。
支持 8kHz 至 96kHz 的采样率
数字信号处理和噪声过滤
•
•
•
四个音频输入引脚：
–
–
多达 2 个差动输入
多达 2 个单端输入
六个音频输出驱动器：
器件信息(1)
–
–
一个全差动或两个单端耳机驱动器
单声道全差动线路输出对
器件型号
封装
封装尺寸（标称值）
TLV320AIC3109-Q1
VQFN (32)
5.00mm x 5.00mm
低功耗：3.3V 模拟电源电压、14mW 单声道、
48kHz 回放
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
•
•
•
•
•
具有无源模拟旁路的超低功耗模式
前端可编程增益放大器 (PGA)
用于 DAC 回放的可编程数字增益：
用于录音的自动增益控制 (AGC)
可编程麦克风偏置
空白
简化图表
DIN WCLK BCLK DOUT
Digital Audio Interface
用于灵活时钟生成的可编程锁相环路 (PLL)
I2C 控制总线
音频数据格式：I2S、左平衡和右平衡、DSP 和
HPCOM
Audio
ADC
Audio
DAC
Digital
Filters
PGA
MIC1P/LINE1P
MIC1M/LINE1M
HPOUT
MIX,
MUX
MIX,
MUX
LEFT_LOM
LEFT_LOP
TDM
MIC2P/LINE2P
MIC2M/LINE2M
RIGHT_LOM
RIGHT_LOP
PGA_AUX
•
电源：
–
–
–
模拟 (AVDD, DRVDD)：2.7V 至 3.6V
数字内核 (DVDD)：1.525V 至 1.95V
数字 I/O (IOVDD)：1.1V 至 3.6V
•
可提供两个 VQFN-32 封装选项：
–
–
非湿润性侧面 (6PAIC3109TRHBRQ1)
可湿侧面 (6PAIC3109TWRHMRQ1)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASE93
TLV320AIC3109-Q1
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
www.ti.com.cn
目录
7.5 Programming........................................................... 38
7.6 Register Maps......................................................... 40
Application and Implementation ...................... 104
8.1 Application Information.......................................... 104
8.2 Typical Application ................................................ 104
Power Supply Recommendations.................... 107
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Audio Data Serial Interface Timing Requirements.. 10
6.7 Typical Characteristics............................................ 14
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 35
8
9
10 Layout................................................................. 107
10.1 Layout Guidelines ............................................... 107
10.2 Layout Example .................................................. 108
11 器件和文档支持 ................................................... 109
11.1 文档支持.............................................................. 109
11.2 接收文档更新通知 ............................................... 109
11.3 社区资源.............................................................. 109
11.4 商标..................................................................... 109
11.5 静电放电警告....................................................... 109
11.6 Glossary.............................................................. 109
12 机械、封装和可订购信息..................................... 109
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (August 2017) to Revision A
Page
•
•
已将 6PAIC3109TWRHMRQ1（可湿侧面封装选项）的状态更新为生产 ............................................................................... 1
已添加 已将 TI 设计添加至文档 .............................................................................................................................................. 1
2
Copyright © 2017, Texas Instruments Incorporated
TLV320AIC3109-Q1
www.ti.com.cn
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
5 Pin Configuration and Functions
RHB, RHM Packages
32-Pin VQFN
Top View
MCLK
BCLK
WCLK
DIN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DRVDD
HPOUT
HPCOM
DRVSS
NC
Thermal
Pad
DOUT
DVSS
IOVDD
SCL
NC
DRVDD
AVSS
Not to scale
NOTE: Connect the device thermal pad to DRVSS.
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Analog DAC voltage supply; connect 1-µF and 0.1-µF decoupling capacitors in parallel
to AVSS
AVDD
25
—
AVSS
BCLK
DIN
17, 26
—
Analog ground
2
4
5
Digital I/O
Digital input
Digital output
Audio serial data bus bit clock input/output
Audio serial data bus data input
Audio serial data bus data output
DOUT
Analog ADC and output driver voltage supply; connect 1-µF and 0.1-µF decoupling
capacitors in parallel to DRVSS
DRVDD
DRVSS
DVDD
18, 24
21
—
—
—
—
Analog output driver ground supply
Digital core voltage supply; connect 1-µF and 0.1-µF decoupling capacitors in parallel
to DVSS
32
DVSS
6
Digital core and I/O ground supply
HPCOM
HPOUT
22
23
7
Analog output High-power output driver (single-ended output, differential output (–), or VCM output)
Analog output High-power output driver, single-ended output or differential output (+)
IOVDD
—
Digital I/O voltage supply
LEFT_LOM
LEFT_LOP
28
27
Analog output Left line output (–); leave floating when not used
Analog output Left line output (+); leave floating when not used
Copyright © 2017, Texas Instruments Incorporated
3
TLV320AIC3109-Q1
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
MCLK
1
Digital input
Analog input
Master clock input
Microphone or line input, differential only (–); connect a 0.47-µF capacitor to AVSS
when not used
MIC1M/LINE1M
MIC1P/LINE1P
MIC2M/LINE2M
MIC2P/LINE2P
11
10
13
12
Microphone or line input, differential (+) or single-ended; connect a 0.47-µF capacitor to
AVSS when not used
Analog input
Analog input
Analog input
Microphone or line input, differential only (–); connect a 0.47-µF capacitor to AVSS
when not used
Microphone or line input, differential (+) or single-ended; connect a 0.47-µF capacitor to
AVSS when not used
MICDET
NC
14
Analog input
—
Microphone detection input; leave floating when not used
Not connected; always leave floating
16, 19, 20
MICBIAS
RESET
RIGHT_LOM
RIGHT_LOP
SCL
15
31
30
29
8
Analog output Microphone bias voltage output; leave floating when not used
Digital input Reset
Analog output Right line output (–); leave floating when not used
Analog output Right line output (+); leave floating when not used
Digital I/O
Digital I/O
Digital I/O
I2C serial clock input
I2C serial data input/output
SDA
9
WCLK
3
Audio serial data bus word clock input/output
6 Specifications
6.1 Absolute Maximum Ratings
MIN
MAX
UNIT
AVDD to AVSS, DRVDD to DRVSS
–0.3
–0.3
–0.3
–0.3
–0.1
–0.3
–0.3
–40
3.9
3.9
AVDD to DRVSS
Power-supply voltage
IOVDD to DVSS
3.9
V
DVDD to DVSS
2.5
AVDD to DRVDD
0.1
Analog input voltage
Digital input voltage
Analog input voltage to AVSS
Digital input voltage to DVSS
Operating ambient, TA
Junction, TJ
AVDD + 0.3
IOVDD + 0.3
105
V
V
Temperature
–40
125
°C
Storage, Tstg
–40
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) ESD compliance tested to EIA/JESD22-A114-B and passed.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
±2000
Corner pins
(1, 8, 9, 16,17, 24, 25, 32)
V(ESD)
Electrostatic discharge
±750
±500
V
Charged-device model (CDM),
per AEC Q100-011
All other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
4
Copyright © 2017, Texas Instruments Incorporated
TLV320AIC3109-Q1
www.ti.com.cn
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER SUPPLY
Analog supply voltage (AVDD to AVSS, DRVDD to DRVSS)
Digital core supply voltage (DVDD to DVSS)
Digital I/O supply voltage (IOVDD to DVSS)
ANALOG INPUTS
2.7
1.525
1.1
3.3
1.8
1.8
3.6
1.95
3.6
V
V
V
VI
Analog full-scale, 0-dB input voltage (DRVDD = 3.3 V)
0.707
VRMS
DIGITAL INPUTS
VDIG
Digital input voltage
DVSS
–40
IOVDD
105
V
TEMPERATURE
TA
Operating free-air temperature
°C
OTHERS
Mono line output load resistance
Mono headphone output load resistance
Digital output load capacitance
10
16
kΩ
Ω
10
pF
6.4 Thermal Information
TLV320AIC3109-Q1
THERMAL METRIC(1)
RHB (VQFN)
RHM (VQFN)
32 PINS
31.3
UNIT
32 PINS
31.1
19.5
10.6
0.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
18.9
11.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
10.6
0.9
11.1
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
5
TLV320AIC3109-Q1
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
www.ti.com.cn
6.5 Electrical Characteristics
at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, and 16-bit audio data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO ADC
Input signal level
Single-ended configurations
0.707
92
VRMS
dB
A-weighted, fS = 48 kSPS, 0-dB PGA gain,
inputs ac-shorted to ground
SNR
DR
Signal-to-noise ratio(1)(2)
80
fS = 48 kSPS; 0-dB PGA gain; 1-kHz, –60-dB,
full-scale input signal
Dynamic range(1)(2)
93
dB
fS = 48 kSPS; 0-dB PGA gain; 1-kHz, –2-dB,
full-scale input signal
THD
Total harmonic distortion
–89
–75
dB
dB
217-Hz signal applied to DRVDD
55
44
PSRR
Power-supply rejection ratio
1-kHz signal applied to DRVDD
Input channel separation
Gain error
1-kHz, –2-dB, full-scale signal, MIC1 to MIC2
–71
dB
dB
fS = 48 kSPS; 0-dB PGA gain; 1-kHz, –2-dB,
full-scale input signal
0.82
59.5
0.5
20
ADC programmable-gain
amplifier maximum gain
1-kHz input tone
dB
dB
ADC programmable-gain
amplifier step size
MIC1/MIC2 inputs routed to single ADC
input MIX attenuation = 0 dB
Input resistance
kΩ
MIC1/MIC2 inputs routed to single ADC
input MIX attenuation = 12 dB
80
Input resistance
80
10
kΩ
Input capacitance
MIC1/LINE1 inputs
pF
Input level control minimum
attenuation setting
0
12
dB
dB
dB
Input level control maximum
attenuation setting
Input level control attenuation
step size
1.5
ANALOG PASSTHROUGH MODE
RDS(on)
Input-to-output switch resistance MIC1/LINE1 to LINEOUT
330
Ω
INPUT SIGNAL LEVEL, DIFFERENTIAL
A-weighted, fS = 48 kSPS, 0-dB PGA gain,
inputs ac-shorted to ground
SNR
THD
Signal-to-noise ratio
92
dB
dB
fS = 48 kHz; 0-dB PGA gain, 1-kHz, –2-dB,
full-scale input signal
Total harmonic distortion
–94
ADC DIGITAL DECIMATION FILTER (fS = 48 kHz)
From 0 fS to 0.39 fS
±0.1
–0.25
–3
At 0.4125 fS
At 0.45 fS
Filter gain
dB
s
At 0.5 fS
–17.5
–75
From 0.55 fS to 64 fS
Filter group delay
17/fS
(1) Ratio of output level with 1-kHz, full-scale, sine-wave input to the output level with the inputs short-circuited, measured A-weighted over
a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz, low-pass filter and an A-weighted filter, where noted. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
6
Copyright © 2017, Texas Instruments Incorporated
TLV320AIC3109-Q1
www.ti.com.cn
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
Electrical Characteristics (continued)
at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, and 16-bit audio data (unless otherwise noted)
PARAMETER
MICROPHONE BIAS
TEST CONDITIONS
MIN
TYP
MAX UNIT
Programmable setting = 2 V
2
2.455
AVDD
4
Bias voltage
Programmable setting = 2.5 V
Programmable setting = AVDD
Programmable setting = 2.5 V
2.3
2.7
V
Current sourcing
mA
AUDIO DAC, DIFFERENTIAL LINE OUTPUT (RLOAD = 10 kΩ)
1.414
4
VRMS
VPP
0-dB input full-scale signal, output common-mode
setting = 1.35 V, output volume control = 0 dB
Full-scale output voltage
Signal-to-noise ratio(3)
A-weighted, fS = 48 kHz, output volume control =
0 dB, no input signal, referenced to full-scale input
level
SNR
DR
88
102
97
dB
dB
A-weighted, fS = 48 kHz, –60-dB input full-scale
signal, output volume control = 0 dB, output
common-mode setting = 1.35 V
Dynamic range
fS = 48 kHz; 0-dB, 1-kHz input full-scale signal;
output volume control = 0 dB; output common-
mode setting = 1.35 V
THD
Total harmonic distortion
Power-supply rejection ratio
DAC gain error
–95
–75
dB
dB
dB
217-Hz signal applied to DRVDD, AVDD
1-kHz signal applied to DRVDD, AVDD
78
80
PSRR
0-dB, 1-kHz input full-scale signal; output volume
control = 0 dB; output common-mode setting =
1.35 V; fS = 48 kHz
–0.2
AUDIO DAC, SINGLE-ENDED LINE OUTPUT (RLOAD = 10 kΩ)
0-dB input full-scale signal, output common-mode
setting = 1.35 V, output volume control = 0 dB
Full-scale output voltage
Signal-to-noise ratio
0.707
96
VRMS
A-weighted, fS = 48 kHz, output volume control =
0 dB, no input signal, referenced to full-scale input
level
SNR
DR
dB
A-weighted, fS = 48 kHz, output volume control =
0 dB, no input signal, referenced to full-scale input
level, 50% DAC current-boost mode
97
91
A-weighted, fS = 48 kHz, –60-dB input full-scale
signal, output volume control = 0 dB, output
common-mode setting = 1.35 V
Dynamic range
DAC gain error
dB
dB
0-dB, 1-kHz input full-scale signal; output volume
control = 0 dB; output common-mode setting =
1.35 V; fS = 48 kHz
–0.85
(3) Unless otherwise noted, all measurements use an output common-mode voltage setting of 1.35 V, a 0-dB output level control gain, and
a 16-Ω single-ended load.
Copyright © 2017, Texas Instruments Incorporated
7
TLV320AIC3109-Q1
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, and 16-bit audio data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO DAC, SINGLE-ENDED HEADPHONE OUTPUT (RLOAD = 16 Ω)
0-dB input full-scale signal, output common-mode
setting = 1.35 V, output volume control = 0 dB
Full-scale output voltage
Signal-to-noise ratio
0.707
96
VRMS
A-weighted, fS = 48 kHz, output volume control =
0 dB, no input signal, referenced to full-scale input
level
SNR
DR
dB
dB
A-weighted, fS = 48 kHz, output volume control =
0 dB, no input signal, referenced to full-scale input
level, 50% DAC current-boost mode
97
91
A-weighted, fS = 48 kHz, –60-dB input full-scale
signal, output volume control = 0 dB, output
common-mode setting = 1.35 V
Dynamic range
fS = 48 kHz, 0-dB input full-scale signal, output
volume control = 0 dB, output common-mode
setting = 1.35 V
THD
Total harmonic distortion
Power-supply rejection ratio
DAC gain error
–71
–65
dB
dB
dB
217-Hz signal applied to DRVDD, AVDD
1-kHz signal applied to DRVDD, AVDD
43
41
PSRR
0-dB, 1-kHz input full-scale signal; output volume
control = 0 dB; output common-mode setting =
1.35 V; fS = 48 kHz
–0.85
DAC DIGITAL INTERPOLATION FILTER (fS = 48 kHz)
Pass band
0
0.45 fS
Hz
dB
Hz
Hz
dB
s
Pass-band ripple
±0.06
Transition band
0.45 fS
0.55 fS
0.55 fS
7.5 fS
Stop band
Stop-band attenuation
65
Group delay
21 / fS
MONO HEADPHONE DRIVER (AC-Coupled Output Configuration(3)
)
0-dB gain to high-power outputs, output common-
mode voltage setting = 1.35 V
0-dB full-scale output voltage
0.707
VRMS
First option
1.35
1.5
Programmable output common-
mode voltage (applicable to line
outputs also)
Second option
Third option
Fourth option
V
1.65
1.8
Maximum programmable output
level control gain
9
1
dB
dB
Programmable output level
control gain step size
RL = 32 Ω
RL = 16 Ω
A-weighted
15
30
94
PO
Maximum output power
Signal-to-noise ratio(4)
mW
dB
SNR
(4) Ratio of output level with a 1-kHz, full-scale input to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to
20-kHz bandwidth.
8
Copyright © 2017, Texas Instruments Incorporated
TLV320AIC3109-Q1
www.ti.com.cn
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
Electrical Characteristics (continued)
at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, and 16-bit audio data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
MONO HEADPHONE DRIVER (AC-Coupled Output Configuration, continued)
–77
0.014%
–76
dB
dB
dB
dB
1-kHz output, PO = 5 mW, RL = 32 Ω
1-kHz output, PO = 10 mW, RL = 32 Ω
0.016%
–73
THD
Total harmonic distortion
1-kHz output, PO = 10 mW, RL = 16 Ω
1-kHz output, PO = 20 mW, RL = 16 Ω
0.022%
–71
0.028%
90
Channel separation
Power-supply rejection ratio
Mute attenuation
1-kHz, 0-dB input
dB
dB
dB
PSRR
217 Hz, 100 mVPP on AVDD, DRVDD
1-kHz output
48
107
DIGITAL I/O
VIL
Input low level
–0.3
0.7 IOVDD
1.1
0.3 IOVDD
V
V
IOVDD > 1.6 V
VIH
Input high level(5)
IOVDD ≤ 1.6 V
VOL
VOH
Output low level
Output high level
0.1 IOVDD
V
V
0.8 IOVDD
CURRENT CONSUMPTION (DRVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V)
IDRVDD + IAVDD
RESET held low
IDVDD
0.1
0.2
µA
mA
µA
Mono ADC record, fS = 8 kSPS, I2S slave,
IDRVDD + IAVDD
2.15
0.48
4.31(6)
2.45(6)
3.5
AGC off, no signal
IDVDD
Mono ADC record, fS = 48 kSPS, I2S slave,
AGC off, no signal
IDRVDD + IAVDD
IDVDD
IDRVDD + IAVDD
IDVDD
IDRVDD + IAVDD
IDVDD
IDRVDD + IAVDD
IDVDD
IDRVDD + IAVDD
IDVDD
IDRVDD + IAVDD
IDVDD
IDRVDD + IAVDD
IDVDD
Mono DAC playback to lineout, analog mixer
bypassed, fS = 48 kSPS, I2S slave
2.3
4.9
Mono DAC playback to lineout, fS = 48 kSPS,
I2S slave, no signal
IIN
2.3
6.7
Mono DAC playback to mono single-ended
headphone, fS = 48 kSPS, I2S slave, no signal
2.3
3.11
0
Mono line in to mono line out, no signal
Extra power when PLL enabled
1.4
0.9
28
All blocks powered down, headset detection
enabled, headset not inserted
2
(5) When IOVDD < 1.6 V, minimum VIH is 1.1 V.
(6) Additional power is consumed when the PLL is powered.
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6.6 Audio Data Serial Interface Timing Requirements(1)(2)
IOVDD = 1.1 V
IOVDD = 3.3 V
UNIT
MIN
MAX
MIN
MAX
I2S, LEFT-JUSTIFIED AND RIGHT-JUSTIFIED TIMING IN MASTER MODE (See 图 1)
td(WS)
ADWS, WCLK delay time
ADWS, WCLK to DOUT delay time
BCLK to DOUT delay time
DIN setup time
50
50
50
15
20
15
ns
ns
ns
ns
ns
ns
ns
td(DO-WS)
td(DO-BCLK)
ts(DI)
th(DI)
tr
10
10
6
6
DIN hold time
Rise time
30
30
10
10
tf
Fall time
DSP TIMING IN MASTER MODE (See 图 2)
td(WS)
ADWS, WCLK delay time
BCLK to DOUT delay time
DIN setup time
DIN hold time
50
50
15
15
ns
ns
ns
ns
ns
ns
td(DO-BCLK)
ts(DI)
th(DI)
tr
10
10
6
6
Rise time
30
30
10
10
tf
Fall time
I2S, LEFT-JUSTIFIED AND RIGHT-JUSTIFIED TIMING IN SLAVE MODE (See 图 3)
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
td(DO-WS)
td(DO-BCLK)
ts(DI)
BCLK high period
70
70
10
10
35
35
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BCLK low period
ADWS, WCLK setup time
ADWS, WCLK hold time
6
ADWS, WCLK to DOUT delay time (for left-justified mode only)
50
50
35
20
BCLK to DOUT delay time
DIN setup time
DIN hold time
Rise time
10
10
6
6
th(DI)
tr
8
8
4
4
tf
Fall time
DSP TIMING IN SLAVE MODE (See 图 4)
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
td(DO-BCLK)
ts(DI)
BCLK high period
BCLK low period
ADWS, WCLK setup time
ADWS, WCLK hold time
BCLK to DOUT delay time
DIN setup time
70
70
10
10
35
35
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
50
20
10
10
6
6
th(DI)
DIN hold time
tr
Rise time
8
8
4
4
tf
Fall time
(1) All timing specifications are measured at characterization but not tested at final test.
(2) All specifications at 25°C, DVDD = 1.8 V.
10
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WCLK
td(WS)
BCLK
td(DO-WS)
td(DO-BCLK)
SDOUT
tS(DI)
th(DI)
SDIN
WCLK
BCLK
T0145-01
图 1. I2S, Left-Justified and Right-Justified Format Timing in Master Mode
td(WS)
td(WS)
td(DO-BCLK)
SDOUT
tS(DI)
th(DI)
SDIN
T0146-01
图 2. DSP Timing in Master Mode
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WCLK
tS(WS)
th(WS)
tH(BCLK)
BCLK
tL(BCLK)
td(DO-WS)
td(DO-BCLK)
SDOUT
tS(DI)
th(DI)
SDIN
T0145-02
图 3. I2S, Left-Justified and Right-Justified Format Timing in Slave Mode
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WCLK
tS(WS)
th(WS)
tS(WS)
th(WS)
tL(BCLK)
BCLK
tH(BCLK)
td(DO-BCLK)
SDOUT
tS(DI)
th(DI)
SDIN
T0146-02
图 4. DSP Timing in Slave Mode
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6.7 Typical Characteristics
at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, and 16-bit audio data (unless otherwise noted)
0
-10
-20
-30
-40
-50
-60
-70
-80
0
−20
−40
−60
HPOUT DRVDD = 2.7 V
HPOUT DRVDD = 3.3 V
HPOUT DRVDD = 3.6 V
−80
−100
−120
−140
−160
0
2
4
6
8
10
12 14
16 18
20
0
10
20
30
40
50
60
70
80
90 100
Headphone Power (mW)
f − Frequency − kHz
G003
Load = 16 Ω, ac-coupled
图 5. THD vs Headphone Power, 16-Ω Load
图 6. DAC to Line Output FFT Plot
0
−20
−40
−60
42
40
38
36
34
32
30
28
26
24
−80
−100
−120
−140
−160
0
2
4
6
8
10
12 14
16 18
20
0
10
20
30
40
50
60
f − Frequency − kHz
PGA Gain Setting − dB
G006
G004
Input = –65 dBFS
图 7. Line Input to ADC FFT Plot
图 8. ADC SNR vs PGA Gain Setting, –65-dBFS Input
0.85
0.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
MICBIAS = AVDD
0.75
0.7
MICBIAS = 2.5 V
0.65
0.6
MICBIAS = 2 V
0.55
0.5
ADC
70
2.7
2.8
2.9
3.0 3.1
3.2
3.3
3.4
3.5
3.6
0
10
20
30
40
50
60
AVDD - Supply Voltage - V
G007
PGA Setting (dB)
图 10. MICBIAS Output Voltage vs AVDD
图 9. ADC Gain Error vs PGA Gain Setting
14
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Typical Characteristics (接下页)
at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, and 16-bit audio data (unless otherwise noted)
3.2
3.0
MICBIAS = AVDD
2.8
2.6
2.4
MICBIAS = 2.5 V
2.2
2.0
MICBIAS = 2 V
1.8
-45 -35 -25 -15 -5
5
15 25 35 45 55 65 75 85
T
A
- Ambient Temperature - °C
G008
图 11. MICBIAS Output Voltage vs Ambient Temperature
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7 Detailed Description
7.1 Overview
The TLV320AIC3109-Q1 is a highly flexible, low-power, mono audio codec with extensive feature integration
intended for automotive applications. Available in a 5-mm × 5-mm, 32-lead VQFN, the device integrates a host of
features to reduce cost, board space, and power consumption in space-constrained, battery-powered, portable
applications.
The TLV320AIC3109-Q1 consists of the following blocks:
•
•
•
•
•
•
•
•
•
Mono audio multi-bit, delta-sigma digital-to-analog converter (DAC): 8 kHz–96 kHz
Mono audio multi-bit, delta-sigma analog-to-digital converter (ADC): 8 kHz–96 kHz
Programmable gain amplifier (PGA): 0-dB to 59.5-dB gain
Programmable digital audio effects processing (bass, treble, midrange, EQ, notch filter, de-emphasis)
Two differential or two single-ended microphone or line inputs
One differential or two single-ended headphone drivers
Two fully differential line output drivers
Fully programmable PLL
Headphone, headset jack detection available as a register status bit
7.2 Functional Block Diagram
Audio Serial Bus Interface
VCM
HPCOM
HPOUT
AGC
SW-D2
LINE1P
PGA
0 dB-59.5 dB
MIC1P/LINE1P
Volume
Control
Digital
Filters
DAC
ADC
in
SW-D1
MIC1M/LINE1M
0.5-dB Steps
LINE1M
LINE1P
LINE1M
SW-L1
LINE2P
LEFT_LOP
LEFT_LOM
PGA
0 dB-59.5 dB
SW-L0
SW-L3
MIC2P/LINE2P
in
MIC2M/LINE2M
0.5-dB Steps
SW-L4
LINE2M
LINE2P
LINE2M
SW-R1
RIGHT_LOP
RIGHT_LOM
SW-R0
SW-R3
I2C Serial
Control Bus
Bias ,
Reference
Audio Clock
Generation
Voltage Supplies
SW-R4
16
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7.3 Feature Description
7.3.1 Hardware Reset
The TLV320AIC3109-Q1 requires a hardware reset after power-up for proper operation. After all power supplies
are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the TLV320AIC3109-Q1 may not respond properly to register reads or writes.
This device also offers a software reset (page 0, register 1) that can be used by the host to reset all registers on
page 0 and page 1 to their reset values. In cases where changes are needed only for routing or volume-control
registers, these changes can be accomplished by writing directly to the appropriate registers rather than using
the software or hardware reset.
In cases where the ESD events generate a device reset, a minimum 1-nF capacitor is recommended to be
connected between the RESET pin and DVSS. This capacitor avoids ESD events that can place the codec in
default state.
7.3.2 Digital Audio Data Serial Interface
Audio data are transferred between the host processor and the TLV320AIC3109-Q1 via the digital audio data
serial interface. The audio bus of the TLV320AIC3109-Q1 can be configured for left- or right-justified, I2S, DSP,
or TDM modes of operation, where communication with standard PCM interfaces is supported within TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word
clock (WCLK) and bit clock (BCLK) can be independently configured in either master or slave mode for flexible
connectivity to a wide variety of processors.
The word clock (WCLK) is used to define the beginning of a frame, and can be programmed as either a pulse or
a square-wave signal. The frequency of this clock corresponds to the selected ADC and DAC sampling
frequency.
The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in master
mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In
continuous transfer mode, only the minimal number of bit clocks required to transfer the audio data are
generated, so in general the number of bit clocks per frame is two times the data width. For example, if the data
width is chosen as 16 bits, then 32-bit clocks are generated per frame. If the bit clock signal in master mode is to
be used by a PLL in another device, then the 16-bit or 32-bit data-width selections are recommended be used.
These cases result in a low-jitter bit clock signal being generated, with frequencies of 32 fS or 64 fS. For a 20-bit
and 24-bit data width in master mode, the bit clocks generated in each frame are not all of equal period because
the device does not have a clean 40-fS or 48-fS clock signal readily available. The average frequency of the bit
clock signal is still accurate in these cases (40 fS or 48 fS), but the resulting clock signal has higher jitter than in
the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC3109-Q1 further includes programmability to place the DOUT line in the high-impedance state
during all bit clocks when valid data are not being sent. By combining this capability with the ability to program at
what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting
in multiple codecs able to use a single audio serial data bus.
When the digital audio data serial interface is powered down when configured in master mode, the pins
associated with the interface are put into a high-impedance state.
The following subsections describe the supported data interface protocols. These protocols can be used for left-
and right-channel applications. Only one of the two possible channels can be selected because the
TLV320AIC3109-Q1 is a mono audio codec. Only the left channel is valid for DOUT (output data). For DIN (input
data), valid data can be selected with bits 4 and 3 of register 7, page 0.
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Feature Description (接下页)
7.3.2.1 Right-Justified Mode
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock
preceding the rising edge of the word clock. 图 12 shows a timing diagram of this operation.
1/fs
WCLK
BCLK
Right Channel
Left Channel
SDIN/SDOUT
0
n–1 n–2 n–3
MSB
2
1
0
n–1 n–2 n–3
2
1
0
LSB
T0149-01
图 12. Right-Justified Serial Data Bus Mode Operation
7.3.2.2 Left-Justified Mode
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock. 图 13 shows a timing diagram of this operation.
1/fs
WCLK
BCLK
Right Channel
Left Channel
SDIN/SDOUT
0
n–1 n–2 n–3
MSB
2
1
0
n–1 n–2 n–3
2
1
0
n–1 n–2
LSB
T0150-01
图 13. Left-Justified Serial Data Bus Mode Operation
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Feature Description (接下页)
7.3.2.3 I2S Mode
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock. 图 14 shows a timing diagram of this operation.
1/fs
WCLK
BCLK
1 Clock Before MSB
Right Channel
Left Channel
SDIN/SDOUT
n–1 n–2 n–3
MSB
2
1
0
n–1 n–2 n–3
2
1
0
n–1
LSB
T0151-01
图 14. I2S Serial Data Bus Mode Operation
7.3.2.4 DSP Mode
In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first,
immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock. 图 15
shows a timing diagram of this operation.
1/fs
WCLK
BCLK
Right Channel
Left Channel
SDIN/SDOUT
n–1 n–2 n–3 n–4
LSB MSB
2
1
0
n–1 n–2 n–3
2
1
0
n–1
LSB MSB
LSB
T0152-01
图 15. DSP Serial Data Bus Mode Operation
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Feature Description (接下页)
7.3.2.5 TDM Data Transfer
Time-division multiplexed data transfer can be realized in any of the left-justified transfer modes if the 256-clock
bit-clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By
changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the
serial data output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks
except when valid data is being put onto the bus. This format allows other codecs to be programmed with
different offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the
codec simply ignores data on the bus except when expected based on the programmed offset.
The location of the data when an offset is programmed is different depending on what transfer mode is selected.
In DSP mode, both the left and right channels of data are transferred immediately adjacent to each other in the
frame. This configuration differs from left-justified mode, where the left- and right-channel data are always a half-
frame apart in each frame. In this case, when the offset is programmed from zero to some higher value, both the
left- and right-channel data move across the frame, but still stay a full half-frame apart from each other. 图 16
shows the TDM transfer for DSP mode and left-justified mode.
DSP Mode
Word Clock
Bit Clock
• • • •
• • • • • •
Data In/Out
N–1 N–2
1
0
N–1 N–2
1
0
Offset
Right-Channel Data
Left-Channel Data
Left-Justified Mode
Word Clock
Bit Clock
• • • •
• • • •
N–1 N–2
1
0
Data In/Out
N–1 N–2
1
0
Offset
Offset
Right-Channel Data
Left-Channel Data
T0153-01
图 16. DSP Mode and Left-Justified Mode, Showing the
Effect of a Programmed Data-Word Offset
7.3.3 Audio Data Converters
The TLV320AIC3109-Q1 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz,
16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters also can operate at
different sampling rates in various combinations, as described in this section.
The data converters are based on the concept of an fS(ref) rate that is used internal to the device, and is related to
the actual sampling rates of the converters through a series of ratios. For typical sampling rates, fS(ref) is either
44.1 kHz or 48 kHz, although fS(ref) can realistically be set over a wider range of rates up to 53 kHz, with
additional restrictions if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and
also to enable high-quality playback of low-sampling-rate data without high-frequency audible noise being
generated.
20
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Feature Description (接下页)
The sampling rate of the ADC and DAC is determined by the clock divider (NCODEC). The sampling rate can be
set to fS(ref) / NCODEC or 2 × fS(ref) / NCODEC, with NCODEC being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for
both the NDAC and NADC settings. In the TLV320AIC3109-Q1, NDAC and NADC must be set to the same value
because the device only supports a common sampling rate for the ADC and DAC channels. Therefore, NCODEC
= NDAC = NADC and this value is programmed by setting the value of bits 7–4 equal to the value of bits 3–0 in
register 2, page 0.
7.3.3.1 Audio Clock Generation
The audio converters in the TLV320AIC3109-Q1 need an internal audio master clock at a frequency of 256 fS(ref)
,
which can be obtained in a variety of manners from an external clock signal applied to the device. 图 17 shows a
detailed diagram of the audio clock section of the TLV320AIC3109-Q1.
MCLK BCLK
PLL_CLKIN
CLKDIV_CLKIN
CLKDIV_IN
PLL_IN
K = J.D
J = 1, 2, 3, ...., 62, 63
K*R/P
D = 0000, 0001, ...., 9998, 9999
R = 1, 2, 3, 4, ...., 15, 16
P = 1, 2, ...., 7, 8
Q = 2, 3,….., 16, 17
2/Q
CLKDIV_OUT
PLL_OUT
1/8
PLLDIV_OUT
CODEC_CLKIN
CODEC_CLK = 256 ´ fS(ref)
CODEC
DAC fS
ADC fS
WCLK = fS(ref)/NCODEC
CODEC fS = DAC fS = ADC fS
Set NCODEC = NADC = NDAC = 1, 1.5, 2, ...., 5.5, 6
DAC DRA => NDAC = 0.5
ADC DRA => NADC = 0.5
B0153-01
图 17. Audio Clock Generation Processing
The device can accept an MCLK input from 512 kHz to 50 MHz that can then be passed through either a
programmable divider or a PLL to get the proper internal audio master clock required by the device. The BCLK
input can also be used to generate the internal audio master clock.
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Feature Description (接下页)
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations easily.
The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus
paid to the standard MCLK rates already widely used.
When the PLL is disabled,
fS(ref) = CLKDIV_IN / (128 × Q)
where
•
Q = 2, 3…17; Q is register-programmable and can be set by bits 6–3 in register 3, page 0
(1)
CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits 7–6.
注
When NCODEC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode,
MCLK can be as high as 50 MHz, and fS(ref) must fall within 39 kHz to 53 kHz, inclusively.
When the PLL is enabled,
fS(ref) = (PLLCLK_IN × K × R) / (2048 × P)
where
•
•
•
•
•
•
P = 1, 2, 3…8
R = 1, 2…16
K = J.D
J = 1, 2, 3…63
D = 0000, 0001, 0002, 0003…9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by bits 5–4 in register 102, page 0
(2)
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), whereas D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits
of precision). P can be set by bits 2–0 in register 3, page 0. R can be set by bits 3–0 in register 11, page 0. J can
be set by bits 7–2 in register 4, page 0. The most-significant bits of D can be set by bits 7–0 in register 5, page 0,
and the least-significant bits of D can be set by bits 7–2 in register 6, page 0.
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz ≤ (PLLCLK_IN / P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz
4 ≤ J ≤ 55
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified
performance:
10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1
Example:
MCLK = 12 MHz and fS(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
22
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Feature Description (接下页)
Example:
MCLK = 12 MHz and fS(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
表 1 lists several example cases of typical MCLK rates and how to program the PLL to achieve fS(ref) = 44.1 kHz
or 48 kHz.
表 1. Typical MCLK Rates
MCLK (MHz)
P
R
J
D
ACHIEVED fS(ref)
% ERROR
fS(ref) = 44.1 kHz
2.8224
5.6448
12
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
32
16
7
0
44,100
44,100
0
0
0
5264
9474
6448
7040
5893
5264
44,100
0
13
6
44,099.71
44,100
–0.0007
16
5
0
19.2
4
44,100
0
19.68
48
4
44,100.3
44,100
0.0007
0
7
fS(ref) = 48 kHz
2.048
3.072
4.096
6.144
8.192
12
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
1
1
48
32
24
16
12
8
0
48,000
48,000
0
0
0
0
48,000
0
0
48,000
0
0
48,000
0
1920
5618
1440
1200
9951
1920
48,000
0
13
7
47,999.71
48,000
–0.0006
16
6
0
19.2
5
48,000
0
–0.0004
0
19.68
48
4
47,999.79
48,000
8
7.3.3.2 Mono Audio ADC
The TLV320AIC3109-Q1 includes a mono audio ADC that uses a delta-sigma modulator with 128-times
oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from
8 kHz to 96 kHz. Whenever the ADC or DAC is in operation, the device requires that an audio master clock be
provided and appropriate audio clock generation be set up within the device.
The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an
initial sampling rate of 128 fS to the final output sampling rate of fS. The decimation filter provides a linear phase
output response with a group delay of 17 / fS. The –3-dB bandwidth of the decimation filter extends to 0.45 fS and
scales with the sample rate (fS). The filter has minimum 75-dB attenuation over the stop band from 0.55 fS to 64
fS. The device also provide options to select the corner frequency of the digital high-pass filter.
Requirements for analog antialiasing filtering are very relaxed because of the oversampling nature of the audio
ADC and the integrated digital decimation filtering. The TLV320AIC3109-Q1 integrates a second-order analog
antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter, provides
sufficient antialiasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA) that allows analog gain control from 0 dB to
59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that
only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on
the register programming (see registers 19 and 22, page 0). This soft-stepping ensures that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on
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power-down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled
by programming a register bit. When soft-stepping is enabled, the audio master clock must be applied to the
device after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When
the ADC power-down flag is no longer set, the audio master clock can be shut down.
An additional auxiliary PGA is provided to allow the mixing of the DAC output signals with an input not routed
through the ADC. This PGA has the same specifications as the ADC PGA.
7.3.3.2.1 Mono Audio ADC High-Pass Filter
Often in audio applications, the dc offset needs to be removed from the converted audio data stream. The
TLV320AIC3109-Q1 has a programmable first-order, high-pass filter that can be used for this purpose. The
digital filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients,
N0, N1, and D1. 公式 3 shows the form of the digital high-pass filter transfer function:
*1
N0 ) N1 z
H(z) +
*1
32, 768 * D1 z
(3)
Programming the channel is done by writing to registers 65–70, page 1. After the coefficients are loaded, these
ADC high-pass filter coefficients can be selected by writing to bit 7 in register 107, page 0, and the high-pass
filter can be enabled by writing to bit 7 in register 12, page 0.
7.3.3.2.2 Automatic Gain Control (AGC)
An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant
output signal amplitude when recording speech signals (the AGC can be fully disabled if not needed). This
circuitry automatically adjusts the PGA gain when the input signal becomes overly loud or very weak, such as
when a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has
several programmable settings, including target level, attack and decay time constants, noise threshold, and
maximum PGA gain applicable that allow the algorithm to be fine-tuned for any particular application. These AGC
features are explained in this section, and 图 18 illustrates their operation. The algorithm uses the absolute
average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal
amplitude of the output signal.
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Input
Signal
Output
Signal
Target
Level
AGC
Gain
Attack
Time
Decay Time
W0002-01
图 18. Typical Operation of the AGC Algorithm During Speech Recording
7.3.3.2.2.1 Target Level
Target value represents the nominal output level at which the AGC attempts to hold the ADC output signal level.
The TLV320AIC3109-Q1 allows programming of eight different target levels, which can be programmed from
–5.5 dB to –24 dB relative to a full-scale signal. The target level is recommended to be set with enough margin to
avoid clipping at the occurrence of loud sounds because the device reacts to the signal absolute average and not
to peak levels.
7.3.3.2.2.2 Attack Time
Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It
Attack time can be varied from 7 ms to 1,408 ms. The attack time can be programmed by writing to register 105,
page 0.
7.3.3.2.2.3 Decay Time
Decay time determines how quickly the PGA gain is increased when the input signal is too low. It Decay time can
be varied in the range from 0.05 s to 22.4 s. Decay time is programmed by writing to register 106, page 0.
The actual maximum AGC decay time is based on a counter length, so the maximum decay time scales with the
clock setup that is used. 表 2 lists the relationship of the NCODEC ratio to the maximum time available for the
AGC decay. In practice, these maximum times are extremely long for audio applications and must not limit any
practical AGC decay time that is needed by the system.
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表 2. AGC Decay Time Restriction
NCODEC RATIO
MAXIMUM DECAY TIME
(SECONDS)
1
1.5
2
4
5.6
8
2.5
3
9.6
11.2
11.2
16
3.5
4
4.5
5
16
19.2
22.4
22.4
5.5
6
7.3.3.2.2.4 Noise Gate Threshold
If the input speech average value falls below the level determined by this threshold, the AGC considers the
speech input to be silent and brings down the gain to 0 dB in steps of 0.5 dB every sample period and sets the
noise threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise
threshold setting. This threshold ensures that noise is not gained up during times of silence. The noise threshold
level in the AGC algorithm is programmable from –30 dB to –90 dB relative to full-scale. A disable noise gate
feature is also available. This operation includes programmable debounce and hysteresis functionality to avoid
the AGC gain from cycling between high gain and 0 dB when signals are near the noise threshold level. When
the noise threshold flag is set, ignore the status of gain applied by the AGC and the saturation flag.
7.3.3.2.2.5 Maximum PGA Gain Applicable
The maximum PGA gain that can be applied by the AGC algorithm can be restricted. This restriction can be used
for limiting PGA gain in situations where environmental noise is greater than the programmed noise threshold.
The PGA gain can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.
The time constants are correct when the ADC is not in double-rate audio mode. The time constants are achieved
by using the fS(ref) value programmed in the control registers. However, if the fS(ref) is set in the registers (for
example, to 48 kHz), but the actual audio clock or PLL programming results in a different fS(ref) in practice, then
the time constants are incorrect; see the Decay Time section for more information.
7.3.4 Mono Audio DAC
The TLV320AIC3109-Q1 includes a mono audio DAC supporting sampling rates from 8 kHz to 96 kHz. The DAC
consists of a digital audio processing block, a digital interpolation filter, a multi-bit digital delta-sigma modulator,
and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates
through increased oversampling and image filtering, thereby keeping quantization noise generated within the
delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. This is
realized by keeping the upsampled rate constant at 128 fS(ref) and changing the oversampling ratio when the
input sample rate changes. For an fS(ref) of 48 kHz, the digital delta-sigma modulator always operates at a rate of
6.144 MHz, which ensures that quantization noise generated within the delta-sigma modulator stays low within
the frequency band below 20 kHz at all sample rates. Similarly, for an fS(ref) rate of 44.1 kHz, the digital delta-
sigma modulator always operates at a rate of 5.6448 MHz.
The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is
enabled in the DAC.
•
•
•
•
Allowed Q values = 4, 8, 9, 12, 16
Q values where equivalent fS(ref) can be achieved by turning on the PLL
Q = 5, 6, 7 (set P = 5, 6, or 7, K = 16, and PLL enabled)
Q = 10, 14 (set P = 5 or 7, K = 8, and PLL enabled)
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7.3.4.1 Digital Audio Processing for Playback
The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, and
speaker equalization. The de-emphasis function is implemented by a programmable digital filter block with fully
programmable coefficients (see registers 21–26, page 1). If de-emphasis is not required in a particular
application, this programmable filter block can be used for some other purpose. 公式 4 gives the de-emphasis
filter transfer function:
*1
N0 ) N1 z
H(z) +
*1
32, 768 * D1 z
where
•
The N0, N1, and D1 coefficients are fully programmable individually
(4)
表 3 lists the coefficients that must be loaded to implement standard de-emphasis filters.
表 3. De-Emphasis Coefficients for Common Audio Sampling Rates
SAMPLING FREQUENCY
32 kHz
N0
N1
D1
16,950
15,091
14,677
–1,220
–2,877
–3,283
17,037
20,555
21,374
44.1 kHz
48 kHz(1)
(1) The 48-kHz coefficients listed in 表 3 are used as defaults.
In addition to the de-emphasis filter block, the DAC digital effects processing includes a fourth-order digital IIR
filter with programmable coefficients. This filter is implemented as a cascade of two biquad sections with the
frequency response given by:
N0 ) 2 N1 z*1 ) N2 z*2
N3 ) 2 N4 z*1 ) N5 z*2
ǒ
Ǔǒ
Ǔ
32, 768 * 2 D1 z*1 * D2 z*2 32, 768 * 2 D4 z*1 * D5 z*2
(5)
The N and D coefficients are fully programmable and the entire filter can be enabled or bypassed. The structure
of the filtering when configured for channel processing is illustrated in 图 19, with LB1 corresponding to the first
biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarly corresponds to the second biquad filter
using coefficients N3, N4, N5, D4, and D5.
LB1
LB2
B0154-01
图 19. Structure of Digital Effects Processing for Channel Processing
The coefficients for this filter implement a variety of sound effects, with bass boost or treble boost being the most
commonly used in portable audio applications. The default N and D coefficients in the device are given in 表 4
and implement a shelving filter with 0-dB gain from dc to approximately 150 Hz, at which point the filter rolls off to
a 3-dB attenuation for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and D
coefficients are represented by 16-bit, 2's-complement numbers with values ranging from –32,768 to 32,767.
表 4. Default Digital Effects Processing Filter Coefficients,
When in Independent Channel Processing Configuration
COEFFICIENTS
N0 = N3
D1 = D4
N1 = N4
D2 = D5
N2 = N5
27,619
32,131
–27,034
–31,506
26,461
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The digital effects filters are recommended to be disabled when the filter coefficients are being modified. When
new coefficients are being written to the device over the control port, a filter using partially updated coefficients
can possibly implement an unstable system and lead to oscillation or objectionable audio output. By disabling the
filters, changing the coefficients, and then reenabling the filters, these types of effects can be entirely avoided.
7.3.4.2 Digital Interpolation Filter
The digital interpolation filter upsamples the output of the digital audio processing block by the required
oversampling ratio before data are provided to the digital delta-sigma modulator and analog reconstruction filter
stages. The filter provides a linear phase output with a group delay of 21 / fS. In addition, programmable digital
interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at
multiples of 8-kHz (that is, 8 kHz, 16 kHz, 24 kHz, and so forth). The images at 8 kHz and 16 kHz are below
20 kHz and are still audible to the listener; therefore, these images must be filtered heavily to maintain a good
quality output. The interpolation filter is designed to maintain at least 65-dB rejection of images that are below
7.455 fS. In order to use the programmable interpolation capability, program fS(ref) to a higher rate (restricted to be
in the range of 39 kHz to 53 kHz when the PLL is in use), and the actual fS is set using the NCODEC divider,
where NCODEC = NDAC = NADC. For example, if fS = 8 kHz is required, then fS(ref) can be set to 48 kHz and
the DAC fS set to fS(ref) / 6. This setting ensures that all images of the 8-kHz data are sufficiently attenuated well
beyond a 20-kHz audible frequency range.
7.3.4.3 Delta-Sigma Audio DAC
The mono audio DAC incorporates a third-order, multi-bit, delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise
shaping techniques. The analog reconstruction filter design consists of a six-tap analog FIR filter followed by a
continuous-time RC filter. The analog FIR operates at a rate of 128 fS(ref) (6.144 MHz when fS(ref) = 48 kHz,
5.6448 MHz when fS(ref) = 44.1 kHz). The DAC analog performance can be degraded by excessive clock jitter on
the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.
7.3.4.4 Audio DAC Digital Volume Control
The audio DAC includes a digital volume control block that implements a programmable digital gain. The volume
level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, or set to mute, independently for each channel. The
volume level can also be changed by the master volume control. Gain changes are implemented with a soft-
stepping algorithm that only changes the actual volume by one step per input sample, either up or down, until the
desired volume is reached. The rate of soft-stepping can be slowed to one step per two input samples through a
register bit.
The host does not know when the DAC is muted because of the soft-stepping, which may be important if the
host wishes to mute the DAC before making a significant change, such as changing sample rates. In order to
help with this situation, the device provides a flag back to the host via a read-only register bit that alerts the host
when the device completes the soft-stepping and the actual volume reaches the desired volume level. The soft-
stepping feature can be disabled through register programming. If soft-stepping is enabled, keep the MCLK
signal applied to the device until the DAC power-down flag is set. When this flag is set, the internal soft-stepping
process and power-down sequence is complete, and the MCLK can then be stopped if desired.
The TLV320AIC3109-Q1 also includes functionality to detect when the selection of de-emphasis or digital audio
processing functionality is changed. When the new selection is detected, the TLV320AIC3109-Q1 (1) soft-mutes
the DAC volume control, (2) changes the operation of the digital effects processing to match the new selection,
and (3) soft-unmutes the device. These steps avoid any possible pops or clicks in the audio output resulting from
instantaneous changes in the filtering. A similar algorithm is used when first powering up or powering down the
DAC. The circuit begins operation at power-up with the volume control muted, then soft-steps the volume up to
the desired level. At power-down, the logic first soft-steps the volume down to a mute level, then powers down
the circuitry.
7.3.4.5 Increasing DAC Dynamic Range
The TLV320AIC3109-Q1 allows trading off dynamic range with power consumption. The DAC dynamic range can
be increased by writing to bits 7–6 in register 109, page 0. The lowest DAC current setting is the default, and the
dynamic range is displayed in the Audio DAC, Differential Line Output section of the Electrical Characteristics
table. Increasing the current can increase the DAC dynamic range by up to 1.5 dB.
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7.3.4.6 Analog Output Common-mode Adjustment
The output common-mode voltage and output range of the analog output are determined by an internal band-gap
reference, in contrast to other codecs that can use a scaled version of the analog supply. This scheme is used to
reduce noise coupling that can be on the supply (such as 217-Hz noise in a GSM cell phone) into the audio
signal path.
However, because of the possible wide variation in analog supply range (2.7 V–3.6 V), an output common-mode
voltage setting of 1.35 V, which is used for a 2.7-V supply case, is overly conservative if the supply is much
larger (such as 3.3 V or 3.6 V). In order to optimize device operation, the TLV320AIC3109-Q1 includes a
programmable output common-mode level that can be set by register programming to a level most appropriate to
the actual supply range used by a particular customer. The output common-mode level can be varied among four
different values, ranging from 1.35 V (most appropriate for low supply ranges, near 2.7 V) to 1.8 V (most
appropriate for high supply ranges, near 3.6 V). As described in 表 5, the recommended DVDD voltage is
dependent on the CM setting.
表 5. Appropriate Settings
CM SETTING
1.35 V
RECOMMENDED AVDD, DRVDD
RECOMMENDED DVDD
1.525 V–1.95 V
1.65 V–1.95 V
1.8 V–1.95 V
2.7 V–3.6 V
3 V–3.6 V
3.3 V–3.6 V
3.6 V
1.5 V
1.65 V
1.8 V
1.95 V
7.3.5 Audio Analog Inputs
The TLV320AIC3109-Q1 includes two single-ended audio inputs. These pins connect through series resistors
and switches to the virtual ground pins of two fully differential operational amplifiers. By selecting to turn on only
one set of switches per operational amplifier at a time, the inputs can be multiplexed effectively to the PGA.
By selecting to turn on multiple sets of switches per operational amplifier at a time, mixing can also be achieved.
Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal operational
amplifiers, resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented,
take adequate precautions to avoid such saturation from occurring. In general, the mixed signal should not
exceed 2 VPP (single-ended).
In most mixing applications, there is also a general need to adjust the levels of the individual signals being
mixed. For example, if a soft signal and a large signal are to be mixed and played together, the soft signal
generally should be amplified to a level comparable to the large signal before mixing. In order to accommodate
this need, the TLV320AIC3109-Q1 includes input level controls on each of the individual inputs before being
mixed or multiplexed into the ADC PGA, with gain programmable from 0 dB to –12 dB in 1.5-dB steps. This input
level control is not intended to be a volume control, but instead used occasionally for level setting. Soft-stepping
of the input level control settings is implemented in this device, with the speed and functionality following the
settings used by the ADC PGA for soft-stepping.
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图 20 shows the single-ended mixing configuration for the PGA, which enables mixing of the signals LINE1L and
LINE1R. The PGA MIX is similar, enabling mixing of the LINE1R and LINE1L signals.
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
MIC1P/LINE1P
To ADC PGA
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
MIC2P/LINE2P
B0156-01
图 20. Single-Ended Analog Input Mixing Configuration
7.3.6 Analog Fully Differential Line Output Drivers
The TLV320AIC3109-Q1 has two fully differential line output drivers, each capable of driving a 10-kΩ differential
load. 图 21 and 图 22 illustrate the output stage design leading to the fully differential line output drivers. This
design includes extensive capability to adjust signal levels independently before any mixing occurs, beyond that
already provided by the PGA gain and the DAC digital volume control.
The PGA signal refers to the output of the ADC PGA stage that is passed around the ADC to the output stage.
PGA_AUX is the output of the auxiliary PGA. The DAC output can be sent to the output driver and mixed with
the PGA or PGA_AUX signal. Undesired signals can also be disconnected from the MIX through register control.
DAC_1
Mono
Audio
DAC
DAC
DAC_3
PGA
PGA_AUX
DAC_1
Volume
Controls,
Mixing
LEFT_LOP
LEFT_LOM
Gain = 0 dB to 9 dB,
Mute
DAC_3
PGA
PGA_AUX
DAC_1
RIGHT_LOP
RIGHT_LOM
Volume
Controls,
Mixing
Gain = 0 dB to 9 dB,
Mute
图 21. Architecture of the Output Stage Leading to the Fully Differential Line Output Drivers
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PGA
0 dB to –78 dB
0 dB to –78 dB
PGA_AUX
+
DAC_1
0 dB to –78 dB
图 22. Detail of the Volume Control and Mixing Function in 图 19 and 图 29
The DAC signal is the output of the mono audio DAC that can be steered by register control based on the
requirements of the system. If mixing of the DAC audio with other signals is not required, and the DAC output is
only needed at the mono line outputs, then use the routing through the DAC_3 path to the fully differential line
outputs. This configuration results in lower-power operation because the analog volume controls and mixing
blocks ahead of these drivers can be powered down.
If instead the DAC analog output must be routed to multiple output drivers simultaneously (such as to
LEFT_LOP, LEFT_LOM and RIGHT_LOP, RIGHT_LOM) or must be mixed with other analog signals, then
switch the DAC outputs through the DAC_1 path. This option provides the maximum flexibility for routing of the
DAC analog signals to the output drivers.
The TLV320AIC3109-Q1 includes an output level control on each output driver with limited gain adjustment from
0 dB to 9 dB. The output driver circuitry in this device is designed to provide a low-distortion output when playing
full-scale mono DAC signals at a 0-dB gain setting. However, a higher amplitude output can be obtained at the
cost of increased signal distortion at the output. This output level control allows this tradeoff to be made based on
the requirements of the end equipment. This output level control is not intended to be used as a standard output
volume control, but is expected to be used only sparingly for level setting (that is, for adjustment of the full-scale
output range of the device).
Each differential line output driver can be powered down independently of the others when not needed in the
system. When placed into powerdown through register programming, the driver output pins are placed into a
high-impedance state.
7.3.7 Analog High-Power Output Drivers
The TLV320AIC3109-Q1 includes two high-power output drivers with extensive flexibility in their usage. These
output drivers are individually capable of driving 30 mW each into a 16-Ω load in single-ended configuration, and
can be used in pairs connected in a bridge-terminated load (BTL) configuration between two driver outputs.
The high-power output drivers can be configured in a variety of ways, including:
1. Driving up to two single-ended output signals
2. Driving one single-ended output signal, with the remaining driver driving a fixed VCM level
The output stage architecture leading to the high-power output drivers is provided in 图 23, with the volume
control and mixing blocks being effectively identical to those in 图 22. Each of these drivers has an output level
control block like those included with the line output drivers, allowing gain adjustment up to 9 dB on the output
signal. As in the previous case, this output level adjustment is not intended to be used as a standard volume
control, but instead is included for additional full-scale output signal-level control.
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PGA
Volume
Controls,
Mixing
PGA_AUX
Volume Level
0 dB to 9 dB, Mute
VCM
HPCOM
DAC_1
PGA
Volume Level
0 dB to 9 dB, Mute
Volume
Controls,
Mixing
HPOUT
PGA_AUX
DAC_2
图 23. Architecture of the Output Stage Leading to the High-Power Output Drivers
The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on
and power-off transient conditions. First program the type of output configuration being used in register 14, page
0 to allow the device to select the optimal power-up scheme to avoid output artifacts. The power-up delay time
for the high-power output drivers is also programmable over a wide range of time delays, from instantaneous up
to 4 s, using register 42, page 0.
When powered down, place these output drivers into a variety of output conditions based on register
programming. If lowest-power operation is desired, then the outputs can be placed into a high-impedance state
and all power to the output stage is removed. However, this generally results in the output nodes drifting to rest
near the upper or lower analog supply because of small leakage currents at the pins, which then results in a
longer delay requirement to avoid output artifacts during driver power-on. In order to reduce this required power-
on delay, the TLV320AIC3109-Q1 includes an option for the output pins of the drivers to be weakly driven to the
VCM level that the pins normally rest at when powered with no signal applied. This output VCM level is
determined by an internal band-gap voltage reference, and thus results in extra power dissipation when the
drivers are in power down. However, this option provides the fastest method for transitioning the drivers from
power-down to full-power operation without any output artifact introduced.
The device includes a further option that falls between the other two—although less power is required when the
output drivers are in power down, a slightly longer delay is required to power up without artifacts than if the band-
gap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a
voltage of approximately half the DRVDD supply level using an internal voltage divider. This voltage does not
match the actual VCM of a fully powered driver, but because of the output voltage being close to the final value,
a much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output
voltage options are controlled in page 0, register 42.
The high-power output drivers can also be programmed to power up first with the output level (gain) control in a
highly attenuated state; then the output driver automatically reduces the output attenuation slowly to reach the
programmed output gain. This capability is enabled by default but can be enabled in register 40, page 0.
7.3.8 Output Stage Volume Controls
A basic analog volume control with a range from 0 dB to –78 dB and mute is replicated multiple times in the
output stage network, connected to each of the analog signals that route to the output stage. In addition, to
enable completely independent mixing operations to be performed for each output driver, each analog signal
coming into the output stage can have up to seven separate volume controls. These volume controls all have
approximately 0.5-dB step programmability over most of the gain range, with steps increasing slightly at the
lowest attenuations. 表 6 lists the detailed gain versus programmed setting for this basic volume control.
32
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表 6. Output Stage Volume Control Settings and Gains
GAIN
SETTING
ANALOG
GAIN
GAIN
SETTING
ANALOG
GAIN
GAIN
SETTING
ANALOG
GAIN
GAIN
SETTING
ANALOG
GAIN
(dB)
(dB)
(dB)
(dB)
0
1
0
–0.5
–1
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
–15
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
–30.1
–30.6
–31.1
–31.6
–32.1
–32.6
–33.1
–33.6
–34.1
–34.6
–35.1
–35.7
–36.1
–36.7
–37.1
–37.7
–38.2
–38.7
–39.2
–39.7
–40.2
–40.7
–41.2
–41.7
–42.2
–42.7
–43.2
–43.8
–44.3
–44.8
90
91
–45.2
–45.8
–46.2
–46.7
–47.4
–47.9
–48.2
–48.7
–49.3
–50
–15.5
–16
2
92
3
–1.5
–2
–16.5
–17
93
4
94
5
–2.5
–3
–17.5
–18
95
6
96
7
–3.5
–4
–18.6
–19.1
–19.6
–20.1
–20.6
–21.1
–21.6
–22.1
–22.6
–23.1
–23.6
–24.1
–24.6
–25.1
–25.6
–26.1
–26.6
–27.1
–27.6
–28.1
–28.6
–29.1
–29.6
97
8
98
9
–4.5
–5
99
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118–127
—
–50.3
–51
–5.5
–6
–51.4
–51.8
–52.2
–52.7
–53.7
–54.2
–55.3
–56.7
–58.3
–60.2
–62.7
–64.3
–66.2
–68.7
–72.2
–78.3
Mute
—
–6.5
–7
–7.5
–8
–8.5
–9
–9.5
–10
–10.5
–11
–11.5
–12
–12.5
–13
–13.5
–14
–14.5
7.3.9 Input Impedance and VCM Control
The TLV320AIC3109-Q1 includes several programmable settings to control analog input pins, particularly when
these inputs are not selected for connection to a PGA. The default option allows unselected inputs to be put into
a high-impedance state such that the input impedance of the device is extremely high. However, the pins on the
device do include protection diode circuits connected to AVDD and AVSS. Thus, if any voltage is driven onto a
pin approximately one diode drop (~0.6 V) above AVDD or one diode drop below AVSS, these protection diodes
begin conducting current, resulting in an effective impedance that no longer appears as a high-impedance state.
In most cases, ac-couple the analog input pins on the TLV320AIC3109-Q1 to the analog input sources, except if
an ADC is used for dc voltage measurement. The ac-coupling capacitor causes a high-pass filter pole to be
inserted into the analog signal path, so the size of the capacitor must be chosen to move that filter pole
sufficiently low in frequency to cause minimal effect on the processed analog signal. The input impedance of the
analog inputs when selected for connection to a PGA varies with the setting of the input level control, starting at
approximately 20 kΩ with an input level control setting of 0 dB, and increasing to approximately 80 kΩ when the
input level control is set at –12 dB. For example, using a 0.1-μF ac-coupling capacitor at an analog input results
in a high-pass filter pole of 80 Hz when the 0-dB input level control setting is selected.
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7.3.10 MICBIAS Generation
The TLV320AIC3109-Q1 includes a programmable microphone bias output voltage (MICBIAS), capable of
providing output voltages of 2 V or 2.5 V (both derived from the on-chip, band-gap voltage) with a 4-mA output
current drive. In addition, the MICBIAS can be programmed to be connected to AVDD directly through an on-chip
switch, or powered down completely when not needed for power savings. This function is controlled by register
programming in register 25, page 0.
7.3.11 Short-Circuit Output Protection
The TLV320AIC3109-Q1 includes programmable short-circuit protection for the high-power output drivers for
maximum flexibility in a given application. By default, if shorted, these output drivers automatically limit the
maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device from an
overcurrent condition. In this mode, register 95, page 0 can be read to determine whether the device is in short-
circuit protection or not, and then the device can be programmed to power-down the output drivers if needed.
However, the device includes further capability to power-down an output driver automatically whenever the driver
goes into short-circuit protection without requiring user intervention. In this case, the output driver remains in a
power-down condition until specifically programmed to power down and then power back up again to clear the
short-circuit flag.
7.3.12 Jack and Headset Detection
The TLV320AIC3109-Q1 includes extensive capability to monitor a headphone, microphone, or headset jack,
determine if a plug has been inserted into the jack, and then determine what type of headset or headphone is
wired to the plug. 图 24 shows one configuration of the device that enables detection and determination of
headset type when a pseudo-differential (capacitor free) mono headphone output configuration is used. The
registers used for this function are registers 14, 96, 97, and 13, page 0. The type of headset detected can be
read back from register 13, page 0. For best results, select a MICBIAS value as high as possible and program
the output driver common-mode level at a 1.35-V or 1.5-V level.
AVDD
MICBIAS
MICDET
To Detection Block
g
s
s
Mono
MIC1P
MIC PreAmp
g
m
Cellular
HPOUT
HPCOM
Pwr
Amp
m = mic
s = ear speaker
g = ground/vcm
To
Detection
Block
图 24. Configuration of Device for Jack Detection Using a Pseudo-Differential (Capacitor Free)
Headphone Output Connection
34
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图 25 shows a modified output configuration used when the output drivers are ac-coupled.
AVDD
MICBIAS
MICDET
To Detection Block
MIC PreAmp
g
s
s
s
Mono
MIC1P
g
m
Cellular
HPCOM
HPOUT
Pwr
Amp
Pwr
Amp
m = mic
s = ear speaker
g = ground/vcm
图 25. Configuration of Device for Jack Detection Using an AC-Coupled Mono Headphone Output
Connection
7.4 Device Functional Modes
7.4.1 Bypass Path Mode
The TLV320AIC3109-Q1 is a versatile device designed for low-power applications. In some cases, only a few
features of the device are required. For these applications, the unused stages of the device must be powered
down to save power and use an alternate route. This path is called a bypass path. The bypass path modes let
the device save power by turning off unused stages (such as the ADC, DAC, and PGA).
7.4.1.1 ADC PGA Signal Bypass Path Functionality
In addition to the input bypass path described previously, the TLV320AIC3109-Q1 also includes the ability to
route the ADC PGA output signals past the ADC for mixing with other analog signals and then for direct
connection to the output drivers. These bypass functions are described in more detail in the Analog Fully
Differential Line Output Drivers and Analog High-Power Output Drivers sections.
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Device Functional Modes (接下页)
7.4.1.2 Passive Analog Bypass During Power Down
Programming the TLV320AIC3109-Q1 to passive analog bypass occurs by configuring the output stage switches
for passthrough. 图 26 shows that this process is done by opening switches SW-L0, SW-L3, SW-R0, and SW-R3
and closing either SW-L1 and SW-R1. Programming this mode is done by writing to register 108, page 0.
Connecting the MIC1P/LINE1P input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW-L0;
this action is done by writing a 1 to bit 0 in register 108, page 0. Connecting the MIC1M/LINE1M input signal to
the LEFT_LOM pin is done by closing SW-L4 and opening SW-L3; this action is done by writing a 1 to bit 1 in
register 108, page 0.
Connecting the MIC2P/LINE2P input signal to the RIGHT_LOP pin is done by closing SW-R1 and opening SW-
R0; this action is done by writing a 1 to bit 4 in register 108, page 0. 图 26 shows a diagram of the passive
analog bypass mode configuration.
SW-L1
SW-L0
LEFT_LOP
SW-L3
LINE1P
LEFT_LOM
SW-L4
MIC1P/LINE1P
MIC1M/LINE1M
LINE1M
SW-R1
SW-R0
RIGHT_LOP
SW-R3
LINE2P
RIGHT_LOM
SW-R4
MIC2P/LINE2P
MIC2M/LINE2M
LINE2M
B0174-01
图 26. Passive Analog Bypass Mode Configuration
36
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Device Functional Modes (接下页)
7.4.2 Digital Audio Processing for Record Path
In applications where record-only is selected and the DAC is powered down, the playback path signal processing
blocks can be used in the ADC record path. These filtering blocks can support high-pass, low-pass, band-pass,
or notch filtering. In this mode, the record-only path has switches SW-D1 and SW-D2 closed, and reroutes the
ADC output data through the digital signal processing blocks. Because the DAC digital signal processing blocks
are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digital
processing and are located in registers 1–26, page 1. This record-only mode is enabled by powering down the
DAC by writing to bit 7 in register 37, page 0 (where bit 7 = 0). Next, enable the digital filter pathway for the ADC
by writing a 1 to bit 3 in register 107, page 0. (This pathway is only enabled if the DAC is powered down.) 图 27
shows the record-only path.
Digital Audio Data Serial Interface
DAC
Powered
Down
AGC
Record Path
SW-D2
PGA
0 dB–59.5 dB,
0.5-dB Steps
Digital
Filters
Volume
Control
Analog Inputs
+
DAC
ADC
SW-D1
B0173-01
图 27. Record-Only Mode With Digital Processing Path Enabled
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7.5 Programming
7.5.1 I2C Control Interface
The TLV320AIC3109-Q1 supports the I2C control protocol using 7-bit addressing and is capable of both standard
and fast modes. As illustrated in 图 28, the minimum timing for each tHD-STA, tSU-STA, and tSU-STO is 0.9 μs for I2C
fast mode. The TLV320AIC3109-Q1 responds to the I2C address of 001 1000. I2C is a two-wire, open-drain
interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus
lines low by connecting the lines to ground; the devices never drive the bus lines high. Instead, the bus wires are
pulled high by pullup resistors so the bus wires are high when not being driven low by a device. This way two
devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
SDA
tHD-STA ³ 0.9 ms
SCL
tSU-STA ³ 0.9 ms
tSU-STO ³ 0.9 ms
tHD-STA ³ 0.9 ms
S
Sr
P
S
T0114-02
图 28. I2C Interface Timing
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
the master. Some I2C devices can act as masters or slaves, but the TLV320AIC3109-Q1 can only act as a slave
device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data are
transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the
appropriate level when SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). When
the SDA line settles, the SCL line is brought high then low. This pulse on SCL clocks the SDA bit into the
receiver shift register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.
Under normal circumstances the master drives the clock line.
Most of the time the bus is idle, no communication is taking place, and both lines are high. When communication
is taking place, the bus is active. Only master devices can start a communication by causing a START condition
on the bus. Normally, the data line is only allowed to change state when the clock line is low. If the data line
changes state when the clock line is high, then the data line state is either a START condition or a STOP
condition. A START condition is when the clock line is high and the data line goes from high to low. A STOP
condition is when the clock line is high and the data line goes from low to high.
After the master issues a START condition, the master sends a byte that indicates which slave device to
communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address.
(Slaves can also have 10-bit addresses; see the I2C specification for details.) The master sends an address in
the address byte with a bit indicating whether to read from or write to the slave device.
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Programming (接下页)
Every byte transmitted on the I2C bus, address or data, is acknowledged with an acknowledge bit. When a
master finishes sending a byte (eight data bits) to a slave, the master stops driving SDA and waits for the slave
to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock
pulse to clock the acknowledge bit. Similarly, when a master finishes reading a byte, the master pulls SDA low to
acknowledge this operation to the slave. The master then sends a clock pulse to clock the bit.
A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not
present on the bus and the master attempts to address the device, the master receives a not-acknowledge
because no device is present at that address to pull the line low.
When a master finishes communicating with a slave, the master can issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master can also issue another START condition. When a
START condition is issued when the bus is active, this condition is called a repeated START condition.
The TLV320AIC3109-Q1 also responds to and acknowledges a general call, which consists of the master issuing
a command with a slave-address byte of 00h. 图 29 and 图 30 show timing diagrams for I2C write and read
operations, respectively.
SCL
DA(6)
DA(0)
RA(7)
RA(0)
D(7)
D(0)
SDA
Start
(M)
7-Bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-Bit Register Address
(M)
Slave
Ack
(S)
8-Bit Register data
(M)
Slave
Ack
(S)
Stop
(M)
(M) – SDA Controlled by Master
(S) – SDA Controlled by Slave
T0147-01
图 29. I2C Write
SCL
SDA
DA(6)
DA(0)
D(7)
D(0)
DA(6)
DA(0)
RA(7)
RA(0)
Start
(M)
7-Bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-Bit Register Address Slave Repeat
7-Bit Device Address Read
(M) (M)
Slave
Ack
(S)
8-Bit Register Data
(S)
Master
No Ack
(M)
Stop
(M)
(M)
Ack
(S)
Start
(M)
(M) – SDA Controlled by Master
(S) – SDA Controlled by Slave
T0148-01
图 30. I2C Read
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-
increment mode. So in the next eight clocks, the data on SDA are treated as data for the next incremental
register.
Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an acknowledge, the slave takes over control of the SDA bus and transmits for the
next 8 clocks the data of the next incremental register.
7.5.1.1 I2C Bus Debug in a Glitched System
Occasionally, some systems can encounter noise or glitches on the I2C bus. In the unlikely event that this noise
affects bus performance, use the I2C debug register. This feature terminates the I2C bus error allowing the I2C
device and system to resume communications. The I2C bus error detector is enabled by default. The
TLV320AIC3109-Q1 I2C error detector status can be read from bit 0 in register 107, page 0. If desired, the
detector can be disabled by writing to bit 2 in register 107, page 0.
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7.6 Register Maps
7.6.1 Register Map Structure
The register map of the TLV320AIC3109-Q1 consists of two pages of registers, with each page containing 128
registers. The register at address zero on each page is used as a page-control register and writing to this register
determines the active page for the device. All subsequent read/write operations access the page that is active at
the time unless a register write is performed to change the active page. The active page defaults to page 0 on
device reset.
Table 7 lists the different access codes used in the TLV320AIC3109-Q1 registers.
Table 7. TLV320AIC3109-Q1 Access Type Codes
Access Type
Code
R
Description
Read
R
R-W
W
R/W
W
Read or write
Write
-n
Value after reset or the default
value
The control registers for the TLV320AIC3109-Q1 are described in this section. All registers are 8 bits in width,
with bit 7 referring to the most-significant bit of each register and bit 0 referring to the least-significant bit. Table 8
lists the registers for page 0 and page 1.
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Table 8. TLV320AIC3109-Q1 Register Map
REGISTER DATA
7
6
5
4
3
2
1
0
0
0
PAGE 0 REGISTERS
Register 0
0
0
0
0
0
0
0
0
0
0
0
Page Select
0
Register 1
Software Reset
Register 2
ADC Sample Rate Select
DAC Sample Rate Select
PLL P
Register 3
PLL Q
PLL Q
PLL J
Register 4
0
Register 5
PLL D
Register 6
PLL D
0
0
0
0
DAC Dual-Rate
DAC Data Path
Control
Register 7
Register 8
Register 9
fS(ref) Setting
DAC Data Path Control
0
Control
Word Clock
Directional Control
Serial Output Data
Driver
Bit, Word Clock Drive Bit, Word Clock Drive
0
0
0
0
Control
Control
Re-Sync Mute
Behavior
Re-Sync Mute
Behavior
Audio Serial Data Interface Transfer Mode
Bit Clock Rate Control
Bit Clock Rate Control
ADC Re-Sync
Register 10
Register 11
Audio Serial Data Word Offset Control
0
ADC Overflow Flag
ADC High-Pass Filter Control
Headset Detection
0
DAC Overflow Flag
0
PLL R
DAC De- Emphasis
DAC De- Emphasis
Filter Control
Register 12
Register 13
Register 14
0
0
0
Filter Control
Headset Glitch Suppression Debounce Control
for Button Press
Headset Type Detection Results
Headset Glitch Suppression Debounce Control for Button Press
Headset Detection
Control
Driver Capacitive
Coupling
0
0
0
0
0
0
Flag
Register 15
Register 16
ADC PGA Mute
PGA_AUX Mute
ADC PGA Gain Setting
PGA _AUX Gain Setting
MIC1P/LINE1P Input
Level Control for ADC
PGA Mix
ADC PGA Soft-
Stepping Control
Register 19
Register 21
MIC1P/LINE1P Input Level Control for ADC PGA Mix
MIC2P/LINE2P Input Level Control for ADC PGA Mix
ADC PGA Soft-Stepping Control
MIC2P/LINE2P Input
Level Control for ADC
PGA Mix
0
0
0
0
0
0
Register 25
Register 26
Register 27
MICBIAS Level Control
AGC Enable
0
0
0
AGC Attack Time
AGC Decay Time
AGC Decay Time
AGC Maximum Gain Allowed
0
AGC Clip Stepping
Control
Register 28
Noise Gate Hysteresis Level Control
AGC Clip Stepping Control
Register 32
Register 34
Channel Gain Applied by AGC Algorithm
AGC Noise Detection Debounce Control
AGC Signal Detection
AGC Signal Detection Debounce Control
Register 36
Register 37
ADC PGA Status
ADC Power Status
AGC Saturation Flag
0
0
0
0
0
0
0
0
Status
DAC Power Control
0
0
0
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Table 8. TLV320AIC3109-Q1 Register Map (continued)
REGISTER DATA
REGISTER
7
6
5
4
3
2
1
0
Short-Circuit
Protection Mode
Control
Short-Circuit
Protection Control
Register 38
0
0
HPCOM Output Driver Configuration Control
0
Register 40
Register 41
Output Common-Mode Voltage Control
DAC Output Switching Control
0
0
0
0
0
0
0
0
Output Volume Control Soft- Stepping
0
0
Weak Output
Common-Mode
Voltage Control
Register 42
Output Driver Power-On Delay Control
Driver Ramp-Up Step Timing Control
DAC Digital Volume Control Setting
0
Register 43
Register 60
DAC Digital Mute
PGA Output Routing
Control
PGA to HPOUT Analog Volume Control
DAC_1 to HPOUT Analog Volume Control
PGA_AUX to HPOUT Analog Volume Control
DAC_1 Output
Routing Control
Register 61
Register 63
Register 65
Register 67
Register 68
Register 70
Register 72
Register 81
Register 82
Register 84
Register 86
Register 88
Register 89
Register 91
PGA_AUX Output
Routing Control
HPOUT Power- Down
Drive Control
HPOUT Volume
Control Status
HPOUT Power
Control
HPOUT Output Level Control
HPCOM Output Level Control
LEFT_LOP/M Output Level Control
HPOUT Mute
PGA Output Routing
Control
PGA to HPCOM Analog Volume Control
DAC_1 to HPCOM Analog Volume Control
PGA_AUX to HPCOM Analog Volume Control
DAC_1 Output
Routing Control
PGA_AUX Output
Routing Control
HPCOM Volume
Control Status
HPCOM Volume
Control Status
HPCOM Power
Control
HPCOM Mute
PGA Output Routing
Control
PGA to LEFT_LOP/M Analog Volume Control
DAC_1 to LEFT_LOP/M Analog Volume Control
PGA_AUX to LEFT_LOP/M Analog Volume Control
DAC_1 Output
Routing Control
PGA_AUX Output
Routing Control
LEFT_LOP/M Volume LEFT_LOP/M Power
LEFT_LOP/M Mute
0
Control Status
Status
PGA Output Routing
Control
DAC_1 Output Routing Control
DAC_1 Output
Routing Control
DAC_1 to RIGHT_LOP/M Analog Volume Control
PGA_AUX to RIGHT_LOP/M Analog Volume Control
PGA_AUX Output
Routing Control
RIGHT_LOP/M
Volume Control
Status
RIGHT_LOP/M Power
Status
Register 93
RIGHT_LOP/M Output Level Control
RIGHT_LOP/M Mute
0
42
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REGISTER
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
Table 8. TLV320AIC3109-Q1 Register Map (continued)
REGISTER DATA
7
6
5
4
3
2
1
0
LEFT_LOP/M Power RIGHT_LOP/M Power
HPOUT Driver Power
Status
Register 94
Register 95
Register 96
Register 97
DAC Power Status
0
0
0
0
Status
Status
HPOUT Short- Circuit
Detection Status
HPCOM Short- Circuit
Detection Status
0
0
0
0
0
0
0
0
0
HPCOM Power Status
0
0
0
0
HPOUT Short- Circuit
Detection Status
HPCOM Short- Circuit
Detection Status
Headset Detection
Status
ADC AGC Noise Gate
Status
0
0
HPOUT Short- Circuit
Detection Status
HPCOM Short- Circuit
Detection Status
Headset Detection
Status
ADC AGC Noise Gate
Status
CODEC_CLKIN
Source Selection
Register 101
Register 102
Register 103
0
0
0
0
0
0
0
1
0
CLKDIV_IN Source Selection
PLLCLK_IN Source Selection
Baseline AGC Attack Time
Baseline AGC Decay Time
0
0
Attack Time Register
Selection
Multiplication Factor for Baseline AGC
Decay Time Register
Selection
Register 104
Register 107
Register 108
Multiplication Factor for Baseline AGC
ADC Digital Output to
0
0
0
Channel High- Pass
Filter Coefficient
Selection
I2C Bus Condition
I2C Bus Error
Detection Status
0
0
0
0
Programmable Filter
Path Selection
Detector
LINE1RM Path
Selection
LINE1RP Path
Selection
LINE1LM Path
Selection
LINE1LP Path
Selection
0
0
0
0
0
Register 109
PAGE 1 REGISTERS
Register 0
DAC Current Adjustment
0
0
0
0
0
0
0
0
0
0
0
Page Select Bit
Register 1
Audio Effects Filter N0 Coefficient MSB
Audio Effects Filter N0 Coefficient LSB
Audio Effects Filter N1 Coefficient MSB
Audio Effects Filter N1 Coefficient LSB
Audio Effects Filter N2 Coefficient MSB
Audio Effects Filter N2 Coefficient LSB
Audio Effects Filter N3 Coefficient MSB
Audio Effects Filter N3 Coefficient LSB
Audio Effects Filter N4 Coefficient MSB
Audio Effects Filter N4 Coefficient LSB
Audio Effects Filter N5 Coefficient MSB
Audio Effects Filter N5 Coefficient LSB
Audio Effects Filter D1 Coefficient MSB
Audio Effects Filter D1 Coefficient LSB
Audio Effects Filter D2 Coefficient MSB
Audio Effects Filter D2 Coefficient LSB
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
Register 16
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Table 8. TLV320AIC3109-Q1 Register Map (continued)
REGISTER DATA
REGISTER
7
6
5
4
3
2
1
0
Register 17
Register 18
Register 19
Register 20
Register 21
Register 22
Register 23
Register 24
Register 25
Register 26
Register 65
Register 66
Register 67
Register 68
Register 69
Register 70
Audio Effects Filter D4 Coefficient MSB
Audio Effects Filter D4 Coefficient LSB
Audio Effects Filter D5 Coefficient MSB
Audio Effects Filter D5 Coefficient LSB
De-Emphasis Filter N0 Coefficient MSB
De-Emphasis Filter N0 Coefficient LSB
De-Emphasis Filter N1 Coefficient MSB
De-Emphasis Filter N1 Coefficient LSB
De-Emphasis Filter D1 Coefficient MSB
De-Emphasis Filter D1 Coefficient LSB
ADC High-Pass Filter N0 Coefficient MSB
Channel ADC High-Pass Filter N0 Coefficient LSB
Channel ADC High-Pass Filter N1 Coefficient MSB
Channel ADC High-Pass Filter N1 Coefficient LSB
Channel ADC High-Pass Filter D1 Coefficient MSB
Channel ADC High-Pass Filter D1 Coefficient LSB
44
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ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
7.6.2 Page 0 Registers
These registers are held within page 0.
7.6.2.1 Register 0: Page Select (address = 0h) [reset = 0000 0000], Page 0
Figure 31. Register 0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Page Select
R/W-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 9. Register 0 Field Descriptions
Bit
7:1
0
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Always write zeros to these bits.
Page select bit.
Page Select
R/W
0h
Writing a 0 to this bit sets page 0 as the active page for the
following register accesses. Writing a 1 to this bit sets page 1 as
the active page for the following register accesses. This register
bit is recommended to be read back after each write to ensure
that the proper page is being accessed for future register reads
or writes.
7.6.2.2 Register 1: Software Reset Register (address = 1h) [reset = 0000 0000], Page 0
Figure 32. Register 1
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Software Reset
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
Table 10. Register 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
Software Reset
W
0h
Software reset bit.
0 : Don’t care
1 : Self-clearing software reset
6:0
Reserved
W
0h
Reserved. Always write zeros to these bits.
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7.6.2.3 Register 2: Codec Sample Rate Select Register (address = 2h) [reset = 0000 0000], Page 0
Figure 33. Register 2
7
6
5
4
3
2
1
0
ADC Sample Rate Select
R/W-0h
DAC Sample Rate Select
R/W-0h
Table 11. Register 2 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
ADC Sample Rate Select(1)
R/W
0h
0000: ADC fS = fS(ref) / 1
0001: ADC fS = fS(ref) / 1.5
0010: ADC fS = fS(ref) / 2
0011: ADC fS = fS(ref) / 2.5
0100: ADC fS = fS(ref) / 3
0101: ADC fS = fS(ref) / 3.5
0110: ADC fS = fS(ref) / 4
0111: ADC fS = fS(ref) / 4.5
1000: ADC fS = fS(ref) / 5
1001: ADC fS = fS(ref) / 5.5
1010: ADC fS = fS(ref) / 6
1011–1111: Reserved. Do not write these sequences.
3:0
DAC Sample Rate Select(1)
R/W
0h
0000: DAC fS = fS(ref) / 1
0001: DAC fS = fS(ref) / 1.5
0010: DAC fS = fS(ref) / 2
0011: DAC fS = fS(ref) / 2.5
0100: DAC fS = fS(ref) / 3
0101: DAC fS = fS(ref) / 3.5
0110: DAC fS = fS(ref) / 4
0111: DAC fS = fS(ref) / 4.5
1000: DAC fS = fS(ref) / 5
1001: DAC fS = fS(ref) / 5.5
1010: DAC fS = fS(ref) / 6
1011–1111 : Reserved, do not write these sequences.
(1) In the TLV320AIC3109-Q1, the ADC fS must be set equal to the DAC fS, which is done by setting the value of bits 7–4 equal to the
value of bits 3–0.
46
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7.6.2.4 Register 3: PLL Programming Register A (address = 3h) [reset = 0001 0000], Page 0
Figure 34. Register 3
7
6
5
4
3
2
1
0
PLL
PLL Q
PLL P
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
Table 12. Register 3 Field Descriptions
Bit
Field
Type
Reset
Description
7
PLL
0h
PLL control bit.
0: PLL is disabled
1: PLL is enabled
6:3
PLL Q
0010h
These bits control the PLL Q value.
0000: Q = 16
0001: Q = 17
0010: Q = 2
0011: Q = 3
0100: Q = 4
…
1110: Q = 14
1111: Q = 15
PLL P
0h
These bits control the PLL P value.
000: P = 8
001: P = 1
010: P = 2
011: P = 3
100: P = 4
101: P = 5
110: P = 6
111: P = 7
7.6.2.5 Register 4: PLL Programming Register B (address = 4h) [reset = 0000 0100]
Figure 35. Register 4
7
6
5
4
3
2
1
0
0
0
PLL J
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
Table 13. Register 4 Field Descriptions
Bit
Field
Type
Reset
Description
7:2
PLL J
R/W
0000 01h
These bits control the PLL J value.
0000 00: Reserved, do not write this sequence
0000 01: J = 1
0000 10: J = 2
0000 11: J = 3
…
1111 10: J = 62
1111 11: J = 63
1:0
Reserved
R/W
0h
Reserved. Always write zeros to these bits.
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7.6.2.6 Register 5: PLL Programming Register C (address = 5h) [reset = 0000 0000], Page 0
Figure 36. Register 5
7
6
5
4
3
2
1
0
PLL D
R/W-0h
Table 14. Register 5 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
PLL D(1)
R/W
0h
These bits control the PLL D value. The eight most-significant
bits of a 14-bit unsigned integer valid values for D are from 0 to
9999, represented by a 14-bit integer located in registers 5–6,
page 0. Do not write values into these registers that result in a D
value outside the valid range.
(1) Whenever the D value is changed, write register 5 immediately followed by register 6. Even if only the MSB or LSB of the value
changes, both registers must be written.
7.6.2.7 Register 6: PLL Programming Register D (address = 6h) [reset = 0000 0000]
Figure 37. Register 6
7
6
5
4
3
2
1
0
0
0
PLL D
R/W-0h
R/W-0h
R/W-0h
Table 15. Register 6 Field Descriptions
Bit
Field
Type
Reset
Description
7:2
PLL D(1)
R/W
0h
These bits control the PLL D value. The six least-significant bits
of a 14-bit unsigned integer valid values for D are from 0 to
9999, represented by a 14-bit integer located in registers 5–6,
page 0. Do not write values into these registers that result in a D
value outside the valid range.
1:0
Reserved
R/W
0h
Reserved. Always write zeros to these bits.
(1) Whenever the D value is changed, write register 5 immediately followed by register 6. Even if only the MSB or LSB of the value
changes, both registers must be written.
48
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7.6.2.8 Register 7: Codec Data-Path Setup Register (address = 7h) [reset = 0000 0000], Page 0
Figure 38. Register 7
7
6
5
4
3
2
0
1
0
0
0
fS(ref) Setting
R/W-0h
ADC Dual-Rate Control DAC Dual-Rate Control DAC Data Path Control
R/W-0h R/W-0h R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 16. Register 7 Field Descriptions
Bit
Field
Type
Reset
Description
7
fS(ref) Setting
R/W
0h
This bit controls the fS(ref) setting.
This register setting controls timers related to the AGC time
constants.
0: fS(ref) = 48 kHz
1: fS(ref) = 44.1 kHz
6
ADC Dual-Rate Control
R/W
0h
0: ADC dual-rate mode is disabled
1: ADC dual-rate mode is enabled
The ADC dual-rate mode must match the DAC dual-rate mode.
5
DAC Dual-Rate Control
DAC Data Path Control
R/W
R/W
0h
0h
0: DAC dual-rate mode is disabled
1: DAC dual-rate mode is enabled
4:3
00: DAC data path is off (muted)
01: DAC data path plays left-channel input data
10: DAC data path plays right-channel input data
11: DAC data path plays mono mix of left- and right-channel
input data
2:0
Reserved
R/W
0h
Reserved. Always write zeros to these bits.
7.6.2.9 Register 8: Audio Serial Data Interface Control Register A (address = 8h) [reset = 0000 0000],
Page 0
Figure 39. Register 8
7
6
5
4
3
0
2
0
1
0
0
0
Bit Clock Directional
Control
Word Clock
Directional Control
Serial Output Data
Driver
Bit, Word Clock Drive
Control
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R-0h
R/W-0h
R/W-0h
R/W-0h
Table 17. Register 8 Field Descriptions
Bit
Field
Type
Reset
Description
7
Bit Clock Directional Control
Word Clock Directional Control
Serial Output Data Driver
R/W
0h
Bit clock directional control.
0: BCLK is an input (slave mode)
1: BCLK is an output (master mode)
6
5
R/W
R/W
0h
0h
Word clock directional control.
0: WCLK is an input (slave mode)
1: WCLK is an output (master mode)
Serial output data driver (DOUT) 3-state control.
0: Do not place DOUT in a high-impedance state when valid
data are not being sent
1: Place DOUT in high-impedance state when valid data are not
being sent
4
Bit, Word Clock Drive Control
R/W
0h
Bit, word clock drive control.
0: BCLK, WCLK do not continue to be transmitted when running
in master mode if the codec is powered down
1: BCLK, WCLK continue to be transmitted when running in
master mode, even if the codec is powered down
3
Reserved
Reserved
R
0h
0h
Reserved. Always write zeros to these bits.
Reserved. Always write zeros to these bits.
2:0
R/W
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7.6.2.10 Register 9: Audio Serial Data Interface Control Register B (address = 9h) [reset = 0000 0000],
Page 0
Figure 40. Register 9
7
6
5
4
3
2
1
0
Audio Serial Data Interface
Transfer Mode
Audio Serial Data Word Length
Control
Bit Clock Rate
Control
Re-Sync Mute
Behavior
DAC Re-Sync
R/W-0h
ADC Re-Sync
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 18. Register 9 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
Audio Serial Data Interface Transfer R/W
Mode
0h
Audio serial data interface transfer mode.
00: Serial data bus uses I2S mode
01: Serial data bus uses DSP mode
10: Serial data bus uses right-justified mode
11: Serial data bus uses left-justified mode
5:4
3
Audio Serial Data Word Length
Control
R/W
R/W
0h
0h
Audio serial data word length control.
00: Audio data word length = 16 bits
01: Audio data word length = 20 bits
10: Audio data word length = 24 bits
11: Audio data word length = 32 bits
Bit Clock Rate Control
Bit clock rate control.
This register only has effect when the bit clock is programmed
as an output.
0: Continuous-transfer mode used to determine master mode bit
clock rate
1: 256-clock transfer mode used, resulting in 256 bit clocks per
frame
2
1
0
DAC Re-Sync
R/W
R/W
R/W
0h
0h
0h
DAC re-sync.
0: Don’t care
1: Re-sync mono DAC with codec interface if the group delay
changes by more than ±DAC (fS / 4)
ADC Re-Sync
ADC re-sync.
0: Don’t care
1: Re-sync mono ADC with codec interface if the group delay
changes by more than ±ADC (fS / 4)
Re-Sync Mute Behavior
Re-sync mute behavior.
0: Re-sync is done without soft-muting the channel (ADC or
DAC)
1: Re-sync is done by internally soft-muting the channel (ADC or
DAC)
50
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7.6.2.11 Register 10: Audio Serial Data Interface Control Register C (address = Ah) [reset = 0000 0000],
Page 0
Figure 41. Register 10
7
6
5
4
3
2
1
0
Audio Serial Data Word Offset Control
R/W-0h
Table 19. Register 10 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Serial Data Word Offset
Control
R/W
0h
Audio serial data word offset control.
This register determines where valid data are placed or
expected in each frame by controlling the offset from beginning
of the frame where valid data begins. The offset is measured
from the rising edge of the word clock when in DSP mode.
0000 0000: Data offset = 0 bit clocks
0000 0001: Data offset = 1 bit clock
0000 0010: Data offset = 2 bit clocks
…
Note: In continuous transfer mode the maximum offset is 17 for
the I2S, left-justified format, and right-justified format modes and
16 for DSP mode. In 256-clock mode, the maximum offset is
242 for the I2S, left-justified format, and right-justified format
modes and 241 for DSP modes.
1111 1110: Data offset = 254 bit clocks
1111 1111: Data offset = 255 bit clocks
7.6.2.12 Register 11: Audio Codec Overflow Flag Register (address = Bh) [reset = 0000 0001], Page 0
Figure 42. Register 11
7
6
0
5
4
0
3
2
1
0
ADC Overflow Flag
R-0h
DAC Overflow Flag
R-0h
PLL R
R-0h
R-0h
R/W-0001h
Table 20. Register 11 Field Descriptions
Bit
Field
Type
Reset
Description
7
ADC Overflow Flag
R
0h
ADC overflow flag.
This bit is a sticky bit, which stays set if an overflow occurs,
even if the overflow condition is removed. The register bit is
reset to 0 after being read.
0: No overflow has occurred
1: An overflow has occurred
6
5
Reserved
R
R
0h
0h
Reserved. Always write zero to this bit.
DAC Overflow Flag
DAC overflow flag.
This bit is a sticky bit, which stays set if an overflow occurs,
even if the overflow condition is removed. The register bit is
reset to 0 after being read.
0: No overflow has occurred
1: An overflow has occurred
4
Reserved
PLL R
R
0h
Reserved. Always write zero to this bit.
3:0
R/W
0001h
PLL R value.
0000: R = 16
0001: R = 1
0010: R = 2
0011: R = 3
0100: R = 4
…
1110: R = 14
1111: R = 15
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7.6.2.13 Register 12: Audio Codec Digital Filter Control Register (address = Ch) [reset = 0000 0000],
Page 0
Figure 43. Register 12
7
6
5
0
4
0
3
2
1
0
0
0
ADC High-Pass Filter
Control
DAC Digital Effects Filter
Control
DAC De-Emphasis Filter
Control
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 21. Register 12 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
ADC High-Pass Filter Control
R/W
0h
ADC high-pass filter control.
00: ADC high-pass filter disabled
01: ADC high-pass filter –3-dB frequency = 0.0045 × ADC fS
10:ADC high-pass filter –3-dB frequency = 0.0125 × ADC fS
11: ADC high-pass filter –3-dB frequency = 0.025 × ADC fS
5:4
3
Reserved
R/W
R/W
0h
0h
Reserved. Always write zeros to these bits.
DAC Digital Effects Filter Control
DAC digital effects filter control.
0: DAC digital effects filter disabled (bypassed)
1: DAC digital effects filter enabled
2
DAC De-Emphasis Filter Control
Reserved
R/W
R/W
0h
0h
DAC de-emphasis filter control.
0: DAC de-emphasis filter disabled (bypassed)
1: DAC de-emphasis filter enabled
1:0
Reserved. Always write zeros to these bits.
7.6.2.14 Register 13: Headset/Button Press Detection Register A (address = Dh) [reset = 0000 0000],
Page 0
Figure 44. Register 13
7
6
5
4
3
2
1
0
Headset Glitch Suppression
Debounce Control for Button
Press
Headset Type Detection
Results
Headset Glitch Suppression Debounce
Control for Jack Detection
Headset Detection Control
R/W-0h
R-0h
R/W-0h
R/W-0h
Table 22. Register 13 Field Descriptions
Bit
Field
Type
Reset
Description
7
Headset Detection Control
R/W
0h
Headset detection control.
0: Headset detection disabled
1: Headset detection enabled
6:5
4:2
Headset Type Detection Results
R
0h
0h
Headset type detection results.
00: No headset detected
01: Headset without microphone detected
10: Ignore (reserved)
11: Headset with microphone detected
Headset Glitch Suppression
Debounce Control for Jack
Detection
R/W
Headset glitch suppression debounce control for jack detection.
000: Debounce = 16 ms (sampled with 2-ms clock)
001: Debounce = 32 ms (sampled with 4-ms clock)
010: Debounce = 64 ms (sampled with 8-ms clock)
011: Debounce = 128 ms (sampled with 16-ms clock)
100: Debounce = 256 ms (sampled with 32-ms clock)
101: Debounce = 512 ms (sampled with 64-ms clock)
110, 111: Reserved, do not write this bit sequence to these
register bits
1:0
Headset Glitch Suppression
Debounce Control for Button Press
R/W
0h
Headset glitch suppression debounce control for button press.
00: Debounce = 0 ms
01: Debounce = 8 ms (sampled with 1-ms clock)
10: Debounce = 16 ms (sampled with 2-ms clock)
11: Debounce = 32 ms (sampled with 4-ms clock)
52
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7.6.2.15 Register 14: Headset/Button Press Detection Register B (address = Eh) [reset = 0000 0000],
Page 0
Figure 45. Register 14
7
6
0
5
0
4
Headset Detection Flag
R-0h
3
0
2
0
1
0
0
0
Driver Capacitive
Coupling
R/W-0h
R/W-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 23. Register 14 Field Descriptions
Bit
Field
Type
Reset
Description
7
Driver Capacitive Coupling
R/W
0h
Driver capacitive coupling.
0: Programs high-power outputs for capacitor-free driver
configuration
1: Programs high-power outputs for ac-coupled driver
configuration
6
5
4
Reserved
R/W
R
0h
0h
0h
Reserved. Always write zero to this bit.
Reserved. Always write zero to this bit.
Reserved
Headset Detection Flag
R
Headset detection flag.
0: A headset is not detected
1: A headset is detected
3:0
Reserved
R
0h
Reserved. Always write zeros to these bits
7.6.2.16 Register 15: ADC PGA Gain Control Register (address = Fh) [reset = 1000 0000], Page 0
Figure 46. Register 15
7
6
5
4
3
2
1
0
ADC PGA Mute
R/W-1h
ADC PGA Gain Setting
R/W-0h
Table 24. Register 15 Field Descriptions
Bit
Field
Type
Reset
Description
7
ADC PGA Mute
R/W
1h
ADC PGA mute.
0: The ADC PGA is not muted
1: The ADC PGA is muted
6:0
ADC PGA Gain Setting
R/W
0h
ADC PGA gain setting.
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB
000 0010: Gain = 1 dB
…
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
…
111 1111: Gain = 59.5 dB
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7.6.2.17 Register 16: Auxiliary PGA Gain Control Register (address = Fh) [reset = 1000 0000], Page 0
Figure 47. Register 16
7
6
5
4
3
2
1
0
PGA_AUX Mute
R/W-1h
PGA _AUX Gain Setting
R/W-0h
Table 25. Register 16 Field Descriptions
Bit
Field
Type
Reset
Description
7
PGA_AUX Mute
R/W
1h
PGA_AUX mute.
0: The auxiliary PGA is not muted
1: The auxiliary PGA is muted
6:0
PGA_AUX Gain Setting
R/W
0h
PGA_AUX gain setting.
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB
000 0010: Gain = 1 dB
…
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
…
111 1111: Gain = 59.5 dB
7.6.2.18 Register 17–18: Reserved (address = 11h–12h) [reset = 1111 1111], Page 0
Figure 48. Register 17
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
Table 26. Register 17 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write ones to these bits.
7:0
R/W
1h
54
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7.6.2.19 Register 19: MIC1P/LINE1P to ADC Control Register (address = 13h) [reset = 0111 1000], Page 0
Figure 49. Register 19
7
6
5
4
3
2
1
0
MIC1P/LINE1P Single-
Ended vs Fully Differential MIC1P/LINE1P Input Level Control for ADC PGA Mix
Control
ADC Channel Power
Control
ADC PGA Soft-Stepping
Control
R/W-0h
R/W-1h
R/W-0h
R/W-0h
Table 27. Register 19 Field Descriptions
Bit
Field
Type
Reset
Description
7
MIC1P/LINE1P Single-Ended vs
Fully Differential Control
R/W
0h
MIC1P/LINE1P single-ended vs fully differential control.
0: MIC1P/LINE1P is configured in single-ended mode
1: MIC1P/LINE1P and MIC1M/LINE1M are configured in fully
differential mode
6:3
MIC1P/LINE1P Input Level Control
for ADC PGA Mix
R/W
1h
MIC1P/LINE1P input level control for ADC PGA mix.
Setting the input level control to one of the following gains
automatically connects LINE1L to the ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved; do not write these sequences to these
register bits
1111: LINE1L is not connected to the ADC PGA
2
ADC Channel Power Control
R/W
R/W
0h
0h
ADC channel power control.
0: ADC channel is powered down
1: ADC channel is powered up
1:0
ADC PGA Soft-Stepping Control
ADC PGA soft-stepping control.
00: ADC PGA soft-stepping at one time per sample period
01: ADC PGA soft-stepping at one time per two sample periods
10–11: ADC PGA soft-stepping is disabled
7.6.2.20 Register 20: Reserved (address = 14h) [reset = 0111 1000], Page 0
Figure 50. Register 20
7
0
6
1
5
1
4
1
3
1
2
0
1
0
0
0
R-0h
R-1h
R-1h
R-1h
R-1h
R-0h
R-0h
R-0h
Table 28. Register 20 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0111 1000 to these bits
Reserved.
R
0111 1000h
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7.6.2.21 Register 21: MIC2P/LINE2P to ADC Control Register (address = 15h) [reset = 0111 1000], Page 0
Figure 51. Register 21
7
6
5
4
3
2
0
1
0
0
0
MIC2P/LINE2P Single-Ended
vs Fully Differential Control
MIC2P/LINE2P Input Level Control for ADC PGA Mix
R/W-1h
R/W-0h
R-0h
R-0h
R-0h
Table 29. Register 21 Field Descriptions
Bit
Field
Type
Reset
Description
7
MIC2P/LINE2P Single-Ended vs
Fully Differential Control
R/W
0h
MIC2P/LINE2P single-ended vs fully differential control.
0: MIC2P/LINE2P is configured in single-ended mode
1: MIC2P/LINE2P and MIC2M/LINE2M are configured in fully
differential mode
6:3
MIC2P/LINE2P Input Level Control
for ADC PGA Mix
R/W
1h
MIC2P/LINE2P input level control for ADC PGA mix.
Setting the input level control to one of the following gains
automatically connects LINE1R to the ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved; do not write these sequences to these
register bits
1111: LINE1R is not connected to the ADC PGA
2:0
Reserved
R
0h
Reserved. Always write zeros to these bits.
7.6.2.22 Registers 22–24: Reserved (address = 16h–18h) [reset = 0111 1000], Page 0
Figure 52. Register 22
7
0
6
1
5
1
4
1
3
1
2
0
1
0
0
0
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
Table 30. Register 22 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0111 1000 to these bits.
Reserved
R/W
0111 1000h
56
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7.6.2.23 Register 25: MICBIAS Control Register (address = 25h) [reset = 0000 0110], Page 0
Figure 53. Register 25
7
6
5
0
4
0
3
0
2
0
1
0
0
0
MICBIAS Level Control
R/W-0h
R-0h
R-0h
R-0h
R-Xh
R-Xh
R-Xh
Table 31. Register 25 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
MICBIAS Level Control
R/W
0h
MICBIAS level control.
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2 V
10: MICBIAS output is powered to 2.5 V
11: MICBIAS output is connected to AVDD
5:3
2:1
0
Reserved
Reserved
Reserved
R
R
R
0h
1h
0h
Reserved. Always write zeros to these bits
Reserved. Always write ones to these bits.
Reserved. Always write zero to this bit.
7.6.2.24 Register 26: AGC Control Register A (address = 1Ah) [reset = 0000 0000], Page 0
Figure 54. Register 26
7
6
5
4
3
2
1
0
AGC Enable
R/W-0h
AGC Target Level
R/W-0h
AGC Attack Time
R/W-0h
AGC Decay Time
Table 32. Register 26 Field Descriptions
Bit
Field
AGC Enable
Type
Reset
Description
7
R/W
0h
AGC enable.
0: AGC is disabled
1: AGC is enabled
6:4
AGC Target Level
R/W
0h
AGC target level.
000: AGC target level = –5.5 dB
001: AGC target level = –8 dB
010: AGC target level = –10 dB
011: AGC target level = –12 dB
100: AGC target level = –14 dB
101: AGC target level = –17 dB
110: AGC target level = –20 dB
111: AGC target level = –24 dB
3:2
1:0
AGC Attack Time
AGC Decay Time
R/W
R/W
0h
0h
AGC attack time.
These time constants(1) are not accurate when double-rate
audio mode is enabled.
00: AGC attack time = 8 ms
01: AGC attack time = 11 ms
10: AGC attack time = 16 ms
11: AGC attack time = 20 ms
AGC decay time.
These time constants(1) are not accurate when double-rate
audio mode is enabled.
00: AGC decay time = 100 ms
01: AGC decay time = 200 ms
10: AGC decay time = 400 ms
11: AGC decay time = 500 ms
(1) Time constants are valid when DRA is not enabled. The values change if DRA is enabled.
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7.6.2.25 Register 27: AGC Control Register B (address = 1Bh) [reset = 1111 1110], Page 0
Figure 55. Register 27
7
6
5
4
3
2
1
0
0
AGC Maximum Gain Allowed
R/W-1h
R/W-0h
Table 33. Register 27 Field Descriptions
Bit
Field
AGC Maximum Gain Allowed
Type
Reset
Description
7:1
R/W
1h
AGC maximum gain allowed.
0000 000: Maximum gain = 0 dB
0000 001: Maximum gain = 0.5 dB
0000 010: Maximum gain = 1 dB
…
1110 110: Maximum gain = 59 dB
1110 111–111 111: Maximum gain = 59.5 dB
0
Reserved
R/W
0h
Reserved. Always write zero to this bit.
7.6.2.26 Register 28: AGC Control Register C (address = 1Ch) [reset = 0000 0000], Page 0
Figure 56. Register 28
7
6
5
4
3
2
1
0
Noise Gate Hysteresis Level
Control
AGC Noise Threshold Control
R/W-0h
AGC Clip Stepping Control
R/W-0h
R/W-0h
Table 34. Register 28 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
Noise Gate Hysteresis Level Control R/W
0h
Noise gate hysteresis level control.
00: Hysteresis = 1 dB
01: Hysteresis = 2 dB
10: Hysteresis = 3 dB
11: Hysteresis is disabled
5:1
AGC Noise Threshold Control
R/W
0h
AGC noise threshold control.
00000: AGC noise/silence detection disabled
00001: AGC noise threshold = –30 dB
00010: AGC noise threshold = –32 dB
00011: AGC noise threshold = –34 dB
…
11101: AGC noise threshold = –86 dB
11110: AGC noise threshold = –88 dB
11111: AGC noise threshold = –90 dB
0
AGC Clip Stepping Control
R/W
0h
AGC clip stepping control.
0: AGC clip stepping disabled
1: AGC clip stepping enabled
58
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7.6.2.27 Register 29: Reserved (address = 1Dh) [reset = 0000 0000], Page 0
Figure 57. Register 29
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 35. Register 29 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
7.6.2.28 Register 30: Reserved (address = 1Eh) [reset = 1111 1110], Page 0
Figure 58. Register 30
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 36. Register 30 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1111 1110 to these bits.
Reserved
R/W
1111 1110h
7.6.2.29 Register 31: Reserved (address = 1Fh) [reset = 0000 0000], Page 0
Figure 59. Register 31
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 37. Register 31 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
7.6.2.30 Register 32: AGC Gain Register (address = 20h) [reset = 1000 0000], Page 0
Figure 60. Register 32
7
6
5
4
3
2
1
0
Channel Gain Applied by AGC Algorithm
R-0h
Table 38. Register 32 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Channel Gain Applied by AGC
Algorithm
R
80h
Channel gain applied by AGC algorithm.
1110 1000: Gain = –12 dB
1110 1001: Gain = –11.5 dB
1110 1010: Gain = –11 dB
…
0000 0000: Gain = 0.0 dB
0000 0001: Gain = 0.5 dB
…
0111 0110: Gain = 59 dB
0111 0111: Gain = 59.5 dB
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7.6.2.31 Register 33: Reserved (address = 21h) [reset = 0000 0000], Page 0
Figure 61. Register 33
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 39. Register 33 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
7.6.2.32 Register 34: AGC Noise Gate Debounce Register (address = 22h) [reset = 0000 0000], Page 0
Figure 62. Register 34
7
6
5
4
3
2
1
0
AGC Noise Detection Debounce Control
R/W-0h
AGC Signal Detection Debounce Control
R/W-0h
Table 40. Register 34 Field Descriptions
Bit
Field
Type
Reset
Description
7:3
AGC Noise Detection Debounce
Control
R/W
0h
AGC noise detection debounce control.
These times(1) are not accurate when double-rate audio mode is
enabled.
0000 0: Debounce = 0 ms
0000 1: Debounce = 0.5 ms
0001 0: Debounce = 1 ms
0001 1: Debounce = 2 ms
0010 0: Debounce = 4 ms
0010 1: Debounce = 8 ms
0011 0: Debounce = 16 ms
0011 1: Debounce = 32 ms
0100 0: Debounce = 64 × 1 = 64 ms
0100 1: Debounce = 64 × 2 = 128 ms
0101 0: Debounce = 64 × 3 = 192 ms
…
1111 0: Debounce = 64 × 23 = 1,472 ms
1111 1: Debounce = 64 × 24 = 1,536 ms
2:0
AGC Signal Detection Debounce
Control
R/W
0h
AGC signal detection debounce control.
These times(1) are not accurate when double-rate audio mode is
enabled.
000: Debounce = 0 ms
001: Debounce = 0.5 ms
010: Debounce = 1 ms
011: Debounce = 2 ms
100: Debounce = 4 ms
101: Debounce = 8 ms
110: Debounce = 16 ms
111: Debounce = 32 ms
(1) Time constants are valid when DRA is not enabled. The values change when DRA is enabled.
60
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7.6.2.33 Register 35: Reserved (address = 23h) [reset = 0000 0000], Page 0
Figure 63. Register 35
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 41. Register 35 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
7.6.2.34 Register 36: ADC Flag Register (address = 24h) [reset = 0000 0000], Page 0
Figure 64. Register 36
7
6
5
4
3
0
2
0
1
0
0
0
AGC Signal Detection
Status
ADC PGA Status
R-0h
ADC Power Status
R-0h
AGC Saturation Flag
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 42. Register 36 Field Descriptions
Bit
Field
Type
Reset
Description
7
ADC PGA Status
R
0h
ADC PGA status.
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
6
5
ADC Power Status
AGC Signal Detection Status
AGC Saturation Flag
Reserved
R
R
R
R
0h
0h
0h
0h
ADC power status.
0: ADC is in a power-down state
1: ADC is in a power-up state
AGC signal detection status.
0: Signal power is greater than or equal to noise threshold
1: Signal power is less than noise threshold
4
AGC saturation flag.
0: AGC is not saturated
1: AGC gain applied = maximum allowed gain for AGC
3:0
Reserved. Always write zeros to these bits.
7.6.2.35 Register 37: DAC Power and Output Driver Control Register (address = 25h) [reset = 0000 0000],
Page 0
Figure 65. Register 37
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DAC Power Control
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R-0h
R-0h
R-0h
R-0h
Table 43. Register 37 Field Descriptions
Bit
Field
Type
Reset
Description
7
DAC Power Control
R/W
0h
DAC power control.
0: DAC is not powered up
1: DAC is powered up
6:4
3:0
Reserved
Reserved
R/W
R
0h
0h
Reserved. Always write zeros to these bits.
Reserved. Always write zeros to these bits.
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7.6.2.36 Register 38: High-Power Output Driver Control Register (address = 26h) [reset = 0000 0000],
Page 0
Figure 66. Register 38
7
0
6
0
5
4
3
2
1
0
0
HPCOM Output Driver Configuration
Control
Short-Circuit Protection
Control
Short-Circuit Protection
Mode Control
R-0h
R-0h
R/W-0h
R/W-0h
R/W-0h
R-0h
Table 44. Register 38 Field Descriptions
Bit
7:6
5:3
Field
Reserved
Type
Reset
0h
Description
R
Reserved. Always write zeros to these register bits.
HPCOM Output Driver Configuration R/W
Control
0h
HPCOM output driver configuration control.
000: HPCOM is configured as a differential of HPOUT
001: HPCOM is configured as a constant VCM output
010: HPCOM is configured as independent single-ended output
011-111: Reserved
2
1
0
Short-Circuit Protection Control
R/W
R/W
R
0h
0h
0h
Short-circuit protection control.
0: Short-circuit protection on all high-power output drivers is
disabled
1: Short-circuit protection on all high-power output drivers is
enabled
Short-Circuit Protection Mode
Control
Short-circuit protection mode control.
0: If short-circuit protection is enabled, the maximum current is
limited to the load
1: If short-circuit protection is enabled, the output driver is
automatically powered down when a short is detected
Reserved
Reserved. Always write a zero to this bit.
7.6.2.37 Register 39: Reserved (address = 27h) [reset = 0000 0000], Page 0
Figure 67. Register 39
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 45. Register 39 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write zeros to these bits.
Reserved
R
0h
62
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7.6.2.38 Register 40: High-Power Output Stage Control Register (address = 28h) [reset = 0000 0000],
Page 0
Figure 68. Register 40
7
6
5
0
4
0
3
0
2
0
1
0
Output Common-Mode Voltage
Control
Output Volume Control Soft-
Stepping
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 46. Register 40 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
Output Common-Mode Voltage
Control
R/W
0h
Output common-mode voltage control.
00: Output common-mode voltage = 1.35 V
01: Output common-mode voltage = 1.5 V
10: Output common-mode voltage = 1.65 V
11: Output common-mode voltage = 1.8 V
5:2
1:0
Reserved
R/W
R/W
0h
0h
Reserved. Always write zeros to these bits.
Output Volume Control Soft-
Stepping
Output volume control soft-stepping.
00: Output soft-stepping = one step per sample period
01: Output soft-stepping = one step per two sample periods
10: Output soft-stepping disabled
11: Reserved; do not write this sequence to these bits
7.6.2.39 Register 41: DAC Output Switching Control Register (address = 29h) [reset = 0000 0000], Page 0
Figure 69. Register 41
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DAC Output Switching Control
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 47. Register 41 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
DAC Output Switching Control
R/W
0h
DAC output switching control.
00: DAC output selects DAC_1 path
01: DAC output selects DAC_3 path to left line output driver
10, 11: Reserved. Do not write this sequence to these register
bits
5:0
Reserved
R/W
0h
Reserved. Always write zeros to these bits.
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7.6.2.40 Register 42: Output Driver Pop Reduction Register (address = 2Ah) [reset = 0000 0000], Page 0
Figure 70. Register 42
7
6
5
4
3
2
1
0
0
Driver Ramp-Up Step Timing Weak Output Common-Mode
Output Driver Power-On Delay Control
R/W-0h
Control
Voltage Control
R/W-0h
R/W-0h
R/W-0h
Table 48. Register 42 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
Output Driver Power-On Delay
Control
R/W
0h
Output driver power-on delay control.
0000: Driver power-on time = 0 μs
0001: Driver power-on time = 10 μs
0010: Driver power-on time = 100 μs
0011: Driver power-on time = 1 ms
0100: Driver power-on time = 10 ms
0101: Driver power-on time = 50 ms
0110: Driver power-on time = 100 ms
0111: Driver power-on time = 200 ms
1000: Driver power-on time = 400 ms
1001: Driver power-on time = 800 ms
1010: Driver power-on time = 2 s
1011: Driver power-on time = 4 s
1100–1111: Reserved; do not write these sequences to these
register bits
3:2
1
Driver Ramp-Up Step Timing
Control
R/W
R/W
R/W
0h
0h
0h
Driver ramp-up step timing control.
00: Driver ramp-up step time = 0 ms
01: Driver ramp-up step time = 1 ms
10: Driver ramp-up step time = 2 ms
11: Driver ramp-up step time = 4 ms
Weak Output Common-Mode
Voltage Control
Weak output common-mode voltage control.
0: Weakly driven output common-mode voltage is generated
from resistor divider off the AVDD supply
1: Weakly driven output common-mode voltage is generated
from band-gap reference
0
Reserved
Reserved. Always write zero to this bit.
7.6.2.41 Register 43: DAC Digital Volume Control Register (address = 2Bh) [reset = 1000 0000], Page 0
Figure 71. Register 43
7
6
5
4
3
2
1
0
DAC Digital Mute
R/W-1h
DAC Digital Volume Control Setting
R/W-0h
Table 49. Register 43 Field Descriptions
Bit
Field
Type
Reset
Description
7
DAC Digital Mute
R/W
1h
DAC digital mute.
0: The DAC channel is not muted
1: The DAC channel is muted
6:0
DAC Digital Volume Control Setting R/W
0h
DAC digital volume control setting.
000 0000: Gain = 0 dB
000 0001: Gain = –0.5 dB
000 0010: Gain = –1 dB
…
111 1101: Gain = –62.5 dB
111 1110: Gain = –63 dB
111 1111: Gain = –63.5 dB
64
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7.6.2.42 Register 44: Reserved (address = 2Ch) [reset = 1000 0000], Page 0
Figure 72. Register 44
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 50. Register 44 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1000 0000 to these bits.
Reserved
R/W
1000 0000h
7.6.2.43 Registers 45–50: Reserved (address = 2Dh–32h) [reset = 0000 0000], Page 0
Figure 73. Register 45
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 51. Register 45 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
7.6.2.44 Register 51: Reserved (address = 33h) [reset = 0000 0100], Page 0
Figure 74. Register 51
7
0
6
0
5
0
4
0
3
0
2
1
1
1
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 52. Register 51 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0000 0100 to these bits.
Reserved
R/W
0000 0100h
7.6.2.45 Registers 52–57: Reserved (address = 34h–39h) [reset = 0000 0000], Page 0
Figure 75. Register 52
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 53. Register 52 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
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7.6.2.46 Register 58: Reserved (address = 3Ah) [reset = 0000 0100], Page 0
Figure 76. Register 58
7
0
6
0
5
0
4
0
3
0
2
1
1
1
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 54. Register 58 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0000 0100 to these bits.
Reserved
R/W
0000 0100h
7.6.2.47 Register 59: Reserved (address = 3Bh) [reset = 0000 0000], Page 0
Figure 77. Register 59
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 55. Register 59 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
7.6.2.48 Register 60: PGA to HPOUT Volume Control Register (address = 3Ch) [reset = 0000 0000],
Page 0
Figure 78. Register 60
7
6
5
4
3
2
1
0
PGA Output Routing Control
R/W-0h
PGA to HPOUT Analog Volume Control
R/W-0h
Table 56. Register 60 Field Descriptions
Bit
Field
Type
Reset
Description
7
PGA Output Routing Control
R/W
0h
PGA output routing control.
0: PGA is not routed to HPOUT
1: PGA is routed to HPOUT
6:0
PGA to HPOUT Analog Volume
Control
R/W
0h
PGA to HPOUT analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
66
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7.6.2.49 Register 61: DAC_1 to HPOUT Volume Control Register (address = 3Dh) [reset = 0000 0000],
Page 0
Figure 79. Register 61
7
6
5
4
3
2
1
0
DAC_1 Output Routing
Control
DAC_1 to HPOUT Analog Volume Control
R/W-0h
R/W-0h
Table 57. Register 61 Field Descriptions
Bit
Field
Type
Reset
Description
7
DAC_1 Output Routing Control
R/W
0h
DAC_1 output routing control.
0: DAC_1 is not routed to HPOUT
1: DAC_1 is routed to HPOUT
6:0
DAC_1 to HPOUT Analog Volume
Control
R/W
0h
DAC_1 to HPOUT analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.50 Register 62: Reserved Register (address = 3Eh) [reset = 0000 0000], Page 0
Figure 80. Register 62
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 58. Register 62 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
7.6.2.51 Register 63: PGA_AUX to HPOUT Volume Control Register (address = 3Fh) [reset = 0000 0000],
Page 0
Figure 81. Register 63
7
6
5
4
3
2
1
0
PGA_AUX Output Routing
Control
PGA_AUX to HPOUT Analog Volume Control
R/W-0h
R/W-0h
Table 59. Register 63 Field Descriptions
Bit
Field
Type
Reset
Description
7
PGA_AUX Output Routing Control
R/W
0h
PGA_AUX output routing control.
0: PGA_AUX is not routed to HPOUT
1: PGA_AUX is routed to HPOUT
6:0
PGA_AUX to HPOUT Analog
Volume Control
R/W
0h
PGA_AUX to HPOUT analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
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7.6.2.52 Register 64: Reserved (address = 40h) [reset = 0000 0000], Page 0
Figure 82. Register 64
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 60. Register 64 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
RW
0h
7.6.2.53 Register 65: HPOUT Output Level Control Register (address = 41h) [reset = 0000 0100], Page 0
Figure 83. Register 65
7
6
5
4
3
2
1
0
HPOUT Power-Down
Drive Control
HPOUT Volume
Control Status
HPOUT Power
Control
HPOUT Output Level Control
R/W-0h
HPOUT Mute
R/W-0h
R/W-1h
R-0h
R/W-0h
Table 61. Register 65 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
HPOUT Output Level Control
R/W
0h
HPOUT output level control.
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved; do not write these sequences to these
register bits
3
2
HPOUT Mute
R/W
0h
1h
HPOUT mute.
0: HPOUT is muted
1: HPOUT is not muted.
HPOUT Power-Down Drive Control R/W
HPOUT power-down drive control.
0: HPOUT is weakly driven to a common mode when powered
down
1: HPOUT is high-impedance when powered down
1
0
HPOUT Volume Control Status
HPOUT Power Control
R
0h
0h
HPOUT volume control status.
0: All programmed gains to HPOUT are applied
1: Not all programmed gains to HPOUT are applied yet
R/W
HPOUT power control.
0: HPOUT is not fully powered up
1: HPOUT is fully powered up
7.6.2.54 Register 66: Reserved (address = 42h) [reset = 0000 0000], Page 0
Figure 84. Register 66
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 62. Register 66 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
68
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7.6.2.55 Register 67: PGA to HPCOM Volume Control Register (address = 43h) [reset = 0000 0000],
Page 0
Figure 85. Register 67
7
6
5
4
3
2
1
0
PGA Output Routing Control
R/W-0h
PGA to HPCOM Analog Volume Control
R/W-0h
Table 63. Register 67 Field Descriptions
Bit
Field
Type
Reset
Description
7
PGA Output Routing Control
R/W
0h
PGA output routing control.
0: PGA is not routed to HPCOM
1: PGA is routed to HPCOM
6:0
PGA to HPCOM Analog Volume
Control
R/W
0h
PGA to HPCOM analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.56 Register 68: DAC_1 to HPCOM Volume Control Register (address = 44h) [reset = 0000 0000],
Page 0
Figure 86. Register 68
7
6
5
4
3
2
1
0
DAC_1 Output Routing
Control
DAC_1 to HPCOM Analog Volume Control
R/W-0h
R/W-0h
Table 64. Register 68 Field Descriptions
Bit
Field
Type
Reset
Description
7
DAC_1 Output Routing Control
R/W
0h
DAC_1 output routing control.
0: DAC_1 is not routed to HPCOM
1: DAC_1 is routed to HPCOM
6:0
DAC_1 to HPCOM Analog Volume
Control
R/W
0h
DAC_1 to HPCOM analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.57 Register 69: Reserved (address = 45h) [reset = 0000 0000], Page 0
Figure 87. Register 69
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 65. Register 69 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
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7.6.2.58 Register 70: PGA_AUX to HPCOM Volume Control Register (address = 46h) [reset = 0000 0000],
Page 0
Figure 88. Register 70
7
6
5
4
3
2
1
0
PGA_AUX Output Routing
Control
PGA_AUX to HPCOM Analog Volume Control
R/W-0h
R/W-0h
Table 66. Register 70 Field Descriptions
Bit
Field
Type
Reset
Description
7
PGA_AUX Output Routing Control
R/W
0h
PGA_AUX output routing control.
0: PGA_AUX is not routed to HPCOM
1: PGA_AUX is routed to HPCOM
6:0
PGA_AUX to HPCOM Analog
Volume Control
R/W
0h
PGA_AUX to HPCOM analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.59 Register 71: Reserved (address = 47h) [reset = 0000 0000], Page 0
Figure 89. Register 71
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 67. Register 71 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
70
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7.6.2.60 Register 72: HPCOM Output Level Control Register (address = 48h) [reset = 0000 0100], Page 0
Figure 90. Register 72
7
6
5
4
3
2
1
0
HPCOM Power-Down
Drive Control
HPCOM Volume
Control Status
HPCOM Power
Control
HPCOM Output Level Control
R/W-0h
HPCOM Mute
R/W-0h
R/W-1h
R/0h
R/W-0h
Table 68. Register 72 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
HPCOM Output Level Control
R/W
0h
HPCOM output level control.
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved; do not write these sequences to these
register bits
3
2
HPCOM Mute
R/W
0h
1h
HPCOM mute.
0: HPCOM is muted
1: HPCOM is not muted
HPCOM Power-Down Drive Control R/W
HPCOM power-down drive control.
0: HPCOM is weakly driven to a common mode when powered
down
1: HPCOM is high-impedance when powered down
1
0
HPCOM Volume Control Status
HPCOM Power Control
R
0h
0h
HPCOM volume control status.
0: All programmed gains to HPCOM are applied
1: Not all programmed gains to HPCOM are applied yet
R/W
HPCOM power control.
0: HPCOM is not fully powered up
1: HPCOM is fully powered up
7.6.2.61 Registers 73–80: Reserved (address = 49h–50h) [reset = 0000 0000], Page 0
Figure 91. Registers 73–80
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 69. Registers 73–80 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
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7.6.2.62 Register 81: PGA to LEFT_LOP/M Volume Control Register (address = 51h) [reset = 0000 0000],
Page 0
Figure 92. Register 81
7
6
5
4
3
2
1
0
PGA Output Routing Control
R/W-0h
PGA to LEFT_LOP/M Analog Volume Control
R/W-0h
Table 70. Register 81 Field Descriptions
Bit
Field
Type
Reset
Description
7
PGA Output Routing Control
R/W
0h
PGA output routing control.
0: PGA is not routed to LEFT_LOP, LEFT_LOM
1: PGA is routed to LEFT_LOP, LEFT_LOM
6:0
PGA to LEFT_LOP/M Analog
Volume Control
R/W
0h
PGA to LEFT_LOP, LEFT_LOM analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.63 Register 82: DAC_1 to LEFT_LOP/M Volume Control Register (address = 52h) [reset = 0000
0000], Page 0
Figure 93. Register 82
7
6
5
4
3
2
1
0
DAC_1 Output Routing
Control
DAC_1 to LEFT_LOP/M Analog Volume Control
R/W-0h
R/W-0h
Table 71. Register 82 Field Descriptions
Bit
Field
Type
Reset
Description
7
DAC_1 Output Routing Control
R/W
0h
DAC_1 output routing control.
0: DAC_1 is not routed to LEFT_LOP, LEFT_LOM
1: DAC_1 is routed to LEFT_LOP, LEFT_LOM
6:0
DAC_1 to LEFT_LOP/M Analog
Volume Control
R/W
0h
DAC_1 to LEFT_LOP, LEFT_LOM analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.64 Register 83: Reserved (address = 53h) [reset = 0000 0000], Page 0
Figure 94. Register 83
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 72. Register 83 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
72
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7.6.2.65 Register 84: PGA_AUX to LEFT_LOP/M Volume Control Register (address = 54h) [reset = 0000
0000], Page 0
Figure 95. Register 84
7
6
5
4
3
2
1
0
PGA_AUX Output Routing
Control
PGA_AUX to LEFT_LOP/M Analog Volume Control
R/W-0h
R/W-0h
Table 73. Register 84 Field Descriptions
Bit
Field
PGA_AUX Output Routing Control
Type
Reset
Description
7
R/W
0h
PGA_AUX output routing control.
0: PGA_AUX is not routed to LEFT_LOP, LEFT_LOM
1: PGA_AUX is routed to LEFT_LOP, LEFT_LOM
6:0
PGA_AUX to LEFT_LOP/M Analog R/W
Volume Control
0h
PGA_AUX to LEFT_LOP, LEFT_LOM analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.66 Register 85: Reserved (address = 55h) [reset = 0000 0000], Page 0
Figure 96. Register 85
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 74. Register 85 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
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7.6.2.67 Register 86: LEFT_LOP/M Output Level Control Register (address = 56h) [reset = 0000 0000],
Page 0
Figure 97. Register 86
7
6
5
4
3
2
0
1
0
LEFT_LOP/M Volume
Control Status
LEFT_LOP/M Power
Status
LEFT_LOP/M Output Level Control
R/W-0h
LEFT_LOP/M Mute
R/W-0h
R-0h
R-0h
R-0h
Table 75. Register 86 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
LEFT_LOP/M Output Level Control R/W
0h
LEFT_LOP, LEFT_LOM output level control.
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved; do not write these sequences to these
register bits
3
LEFT_LOP/M Mute
Reserved
R/W
0h
LEFT_LOP, LEFT_LOM mute.
0: LEFT_LOP, LEFT_LOM are muted
1: LEFT_LOP, LEFT_LOM are not muted
2
1
R
R
0h
0h
Reserved. Always write zero to this bit.
LEFT_LOP/M Volume Control
Status
LEFT_LOP, LEFT_LOM volume control status.
0: All programmed gains to LEFT_LOP, LEFT_LOM are applied
1: Not all programmed gains to LEFT_LOP, LEFT_LOM are
applied yet
0
LEFT_LOP/M Power Status
R
0h
LEFT_LOP, LEFT_LOM power status.
0: LEFT_LOP, LEFT_LOM is not fully powered up
1: LEFT_LOP, LEFT_LOM is fully powered up
7.6.2.68 Register 87: Reserved (address = 57h) [reset = 0000 0000], Page 0
Figure 98. Register 87
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 76. Register 87 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
74
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7.6.2.69 Register 88: PGA to RIGHT_LOP/M Volume Control (address = 58h) [reset = 0000 0000], Page 0
Figure 99. Register 88
7
6
5
4
3
2
1
0
PGA Output Routing Control
R/W-0h
PGA to RIGHT_LOP/M Analog Volume Control
R/W-0h
Table 77. Register 88 Field Descriptions
Bit
Field
Type
Reset
Description
7
PGA Output Routing Control
R/W
0h
PGA output routing control.
0: PGA is not routed to RIGHT_LOP, RIGHT_LOM
1: PGA is routed to RIGHT_LOP, RIGHT_LOM
6:0
PGA to RIGHT_LOP/M Analog
Volume Control
R/W
0h
PGA to RIGHT_LOP, RIGHT_LOM analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.70 Register 89: DAC_1 to RIGHT_LOP/M Volume Control (address = 59h) [reset = 0000 0000],
Page 0
Figure 100. Register 89
7
6
5
4
3
2
1
0
DAC_1 Output Routing
Control
DAC_1 to RIGHT_LOP/M Analog Volume Control
R/W-0h
R/W-0h
Table 78. Register 89 Field Descriptions
Bit
Field
Type
Reset
Description
7
DAC_1 Output Routing Control
R/W
0h
DAC_1 output routing control.
0: DAC_1 is not routed to RIGHT_LOP, RIGHT_LOM
1: DAC_1 is routed to RIGHT_LOP, RIGHT_LOM
6:0
DAC_1 to RIGHT_LOP/M Analog
Volume Control
R/W
0h
DAC_1 to RIGHT_LOP, RIGHT_LOM analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.71 Register 90: Reserved (address = 5A) [reset = 0000 0000], Page 0
Figure 101. Register 90
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 79. Register 90 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
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7.6.2.72 Register 91: PGA_AUX to RIGHT_LOP/M Volume Control (address = 5Bh) [reset = 0000 0000],
Page 0
Figure 102. Register 91
7
6
5
4
3
2
1
0
PGA_AUX Output Routing
Control
PGA_AUX to RIGHT_LOP/M Analog Volume Control
R/W-0h
R/W-0h
Table 80. Register 91 Field Descriptions
Bit
Field
Type
Reset
Description
7
PGA_AUX Output Routing Control
R/W
0h
PGA_AUX output routing control.
0: PGA_AUX is not routed to RIGHT_LOP, RIGHT_LOM
1: PGA_AUX is routed to RIGHT_LOP, RIGHT_LOM
6:0
PGA_AUX to RIGHT_LOP/M
Analog Volume Control
R/W
0h
PGA_AUX to RIGHT_LOP, RIGHT_LOM analog volume control.
For 7-bit register settings versus analog gain values, see 表 6.
7.6.2.73 Register 92: Reserved (address = 5Ch) [reset = 0000 0000], Page 0
Figure 103. Register 92
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 81. Register 92 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
76
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7.6.2.74 Register 93: RIGHT_LOP/M Output Level Control (address = 5Dh) [reset = 0000 0000], Page 0
Figure 104. Register 93
7
6
5
4
3
2
0
1
0
RIGHT_LOP/M Volume RIGHT_LOP/M Power
RIGHT_LOP/M Output Level Control
R/W-0h
RIGHT_LOP/M Mute
R/W-0h
Control Status
Status
R-0h
R-0h
R-0h
Table 82. Register 93 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
RIGHT_LOP/M Output Level
Control
R/W
0h
RIGHT_LOP, RIGHT_LOM output level control.
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved; do not write these sequences to these
bits
3
RIGHT_LOP/M Mute
Reserved
R/W
0h
RIGHT_LOP, RIGHT_LOM mute.
0: RIGHT_LOP, RIGHT_LOM are muted
1: RIGHT_LOP, RIGHT_LOM are not muted
2
1
R
R
0h
0h
Reserved. Always write zero to this bit.
RIGHT_LOP/M Volume Control
Status
RIGHT_LOP, RIGHT_LOM volume control status.
0: All programmed gains to RIGHT_LOP, RIGHT_LOM are
applied
1: Not all programmed gains to RIGHT_LOP, RIGHT_LOM are
applied yet
0
RIGHT_LOP/M Power Status
R
0h
RIGHT_LOP, RIGHT_LOM power status/
0: RIGHT_LOP, RIGHT_LOM are not fully powered up
1: RIGHT_LOP, RIGHT_LOM are fully powered up
7.6.2.75 Register 94: Module Power Status Register (address = 5Eh) [reset = 0000 0000], Page 0
Figure 105. Register 94
7
6
0
5
0
4
3
2
0
1
0
0
LEFT_LOP/M Power RIGHT_LOP/M Power
HPOUT Driver Power
Status
DAC Power Status
R-0h
Status
Status
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 83. Register 94 Field Descriptions
Bit
Field
Type
Reset
Description
7
DAC Power Status
R
0h
DAC power status.
0: DAC is not fully powered up
1: DAC is fully powered up
6:5
4
Reserved
R
R
0h
0h
Reserved. Always write zeros to these bits.
LEFT_LOP/M Power Status
RIGHT_LOP/M Power Status
LEFT_LOP, LEFT_LOM power status.
0: LEFT_LOP, LEFT_LOM output driver is powered down
1: LEFT_LOP, LEFT_LOM output driver is powered up
3
R
0h
RIGHT_LOP, RIGHT_LOM power status.
0: RIGHT_LOP, RIGHT_LOM is not fully powered up
1: RIGHT_LOP, RIGHT_LOM is fully powered up
2
1
Reserved
R
R
0h
0h
Reserved. Always write zero to this bit.
HPOUT Driver Power Status
HPOUT driver power status.
0: HPOUT driver is not fully powered up
1: HPOUT driver is fully powered up
0
Reserved
R
0h
Reserved. Always write zero to this bit.
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7.6.2.76 Register 95: Output Driver Short-Circuit Detection Status Register (address = 5Fh) [reset = 0000
0000], Page 0
Figure 106. Register 95
7
0
6
5
0
4
3
0
2
1
0
0
0
HPOUT Short-Circuit
Detection Status
HPCOM Short-Circuit
Detection Status
HPCOM Power Status
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 84. Register 95 Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Always write zero to this bit.
6
HPOUT Short-Circuit Detection
Status
R
0h
HPOUT short-circuit detection status.
0: No short circuit detected at HPOUT
1: Short circuit detected at HPOUT
5
4
Reserved
R
R
0h
0h
Reserved. Always write zero to this bit.
HPCOM Short-Circuit Detection
Status
HPCOM short-circuit detection status.
0: No short circuit detected at HPCOM
1: Short circuit detected at HPCOM
3
2
Reserved
R
R
0h
0h
Reserved. Always write zero to this bit.
HPCOM Power Status
HPCOM power status.
0: HPCOM is not fully powered up
1: HPCOM is fully powered up
1:0
Reserved
R
0h
Reserved. Always write zeros to these bits.
7.6.2.77 Register 96: Sticky Interrupt Flags Register (address = 60h) [reset = 0000 0000], Page 0
Figure 107. Register 96
7
0
6
5
0
4
3
0
2
1
0
0
HPOUT Short-Circuit
Detection Status
HPCOM Short-Circuit
Detection Status
Headset Detection
Status
ADC AGC Noise Gate
Status
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 85. Register 96 Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Always write zero to this bit.
6
HPOUT Short-Circuit Detection
Status
R
0h
HPOUT short-circuit detection status.
0: No short circuit detected at HPOUT driver
1: Short circuit detected at HPOUT driver
5
4
Reserved
R
R
0h
0h
Reserved. Always write zero to this bit.
HPCOM Short-Circuit Detection
Status
HPCOM short-circuit detection status.
0: No short circuit detected at HPCOM driver
1: Short circuit detected at HPCOM driver
3
2
Reserved
R
R
0h
0h
Reserved. Always write zero to this bit.
Headset Detection Status
Headset detection status.
0: No headset insertion or removal is detected
1: Headset insertion or removal is detected
1
0
ADC AGC Noise Gate Status
Reserved
R
R
0h
0h
ADC AGC noise gate status.
0: DC signal power is greater than or equal to noise threshold
for AGC
1: ADC signal power is less than noise threshold for AGC
Reserved. Always write zero to this bit.
78
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7.6.2.78 Register 97: Real-Time Interrupt Flags Register (address = 61h) [reset = 0000 0000], Page 0
Figure 108. Register 97
7
0
6
5
0
4
3
0
2
1
0
0
HPOUT Short-Circuit
Detection Status
HPCOM Short-Circuit
Detection Status
Headset Detection
Status
ADC AGC Noise Gate
Status
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 86. Register 97 Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Always write zero to this bit.
6
HPOUT Short-Circuit Detection
Status
R
0h
HPOUT short-circuit detection status.
0: No short circuit detected at HPOUT driver
1: Short circuit detected at HPOUT driver
5
4
Reserved
R
R
0h
0h
Reserved. Always write zero to this bit.
HPCOM Short-Circuit Detection
Status
HPCOM short-circuit detection status.
0: No short circuit detected at HPCOM driver
1: Short circuit detected at HPCOM driver
3
2
Reserved
R
R
0h
0h
Reserved. Always write zero to this bit.
Headset Detection Status
Headset Detection Status
0: No headset insertion/removal is detected.
1: Headset insertion/removal is detected.
1
0
ADC AGC Noise Gate Status
Reserved
R
R
0h
0h
ADC AGC Noise Gate Status
0: ADC signal power is greater than noise threshold for lAGC.
1: ADC signal power lower than noise threshold for AGC.
Reserved. Always write zero to this bit.
7.6.2.79 Registers 98–100: Reserved (address = 62h–64h) [reset = 0000 0000], Page 0
Figure 109. Registers 98–100
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 87. Registers 98–100 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write zeros to these bits.
Reserved
R
0h
7.6.2.80 Register 101: Clock Register (address = 65h) [reset = 0000 0000], Page 0
Figure 110. Register 101
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CODEC_CLKIN Source
Selection
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R/W-0h
Table 88. Register 101 Field Descriptions
Bit
7:1
0
Field
Reserved
CODEC_CLKIN Source Selection
Type
R
Reset
0h
Description
Reserved. Always write zeros to these bits.
R/W
0h
CODEC_CLKIN source selection.
0: CODEC_CLKIN uses PLLDIV_OUT
1: CODEC_CLKIN uses CLKDIV_OUT
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7.6.2.81 Register 102: Clock Generation Control Register (address = 66h) [reset = 0000 0000], Page 0
Figure 111. Register 102
7
6
5
4
3
0
2
0
1
1
0
0
CLKDIV_IN Source Selection
R/W-0h
PLLCLK_IN Source Selection
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 89. Register 102 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
CLKDIV_IN Source Selection
R/W
0h
CLKDIV_IN source selection.
00: CLKDIV_IN uses MCLK
01: CLKDIV_IN uses GPIO2
10: CLKDIV_IN uses BCLK
11: Reserved; do not use
5:4
PLLCLK_IN Source Selection
R/W
0h
PLLCLK_IN source selection.
00: PLLCLK_IN uses MCLK
01: PLLCLK_IN uses GPIO2
10: PLLCLK _IN uses BCLK
11: Reserved; do not use
3:0
Reserved
R/W
0h
Reserved. Always write zeros to these bits.
7.6.2.82 Register 103: AGC New Programmable Attack Time Register (address = 67h) [reset = 0000
0000], Page 0
Figure 112. Register 103
7
6
5
4
3
2
1
0
0
0
Attack Time Register
Selection
Baseline AGC Attack Time
R/W-0h
Multiplication Factor for Baseline AGC
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 90. Register 103 Field Descriptions
Bit
Field
Type
Reset
Description
7
Attack Time Register Selection
R/W
0h
Attack time register selection.
0: Attack time for the AGC is generated from register 26, page 0
1: Attack time for the AGC is generated from this register
6:5
4:2
Baseline AGC Attack Time
R/W
R/W
0h
0h
Baseline AGC attack time.
00: AGC attack time = 7 ms
01: AGC attack time = 8 ms
10: AGC attack time = 10 ms
11: AGC attack time = 11 ms
Multiplication Factor for Baseline
AGC
Multiplication factor for baseline AGC.
000: Multiplication factor for the baseline AGC attack time = 1
001: Multiplication factor for the baseline AGC attack time = 2
010: Multiplication factor for the baseline AGC attack time = 4
011: Multiplication factor for the baseline AGC attack time = 8
100: Multiplication factor for the baseline AGC attack time = 16
101: Multiplication factor for the baseline AGC attack time = 32
110: Multiplication factor for the baseline AGC attack time = 64
111: Multiplication factor for the baseline AGC attack time = 128
1:0
Reserved
R/W
0h
Reserved. Always write zeros to these bits.
80
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7.6.2.83 Register 104: AGC New Programmable Decay Time Register (address = 68h) [reset = 0000
0000], Page 0
Figure 113. Register 104
7
6
5
4
3
2
1
0
0
0
Decay Time Register
Selection
Baseline AGC Decay Time
R/W-0h
Multiplication Factor for Baseline AGC
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 91. Register 104 Field Descriptions
Bit
Field
Type
Reset
Description
7
Decay Time Register Selection(1)
R/W
0h
Decay time register selection.
0: Decay time for the AGC is generated from register 26, page 0
1: Decay time for the AGC is generated from this register
6:5
4:2
Baseline AGC Decay Time
R/W
R/W
0h
0h
Baseline AGC decay time.
00: AGC decay time = 50 ms
01: AGC decay time = 150 ms
10: AGC decay time = 250 ms
11: -AGC decay time = 350 ms
Multiplication Factor for Baseline
AGC
Multiplication factor for baseline AGC.
000: Multiplication factor for the baseline AGC decay time = 1
001: Multiplication factor for the baseline AGC decay time = 2
010: Multiplication factor for the baseline AGC decay time = 4
011: Multiplication factor for the baseline AGC decay time = 8
100: Multiplication factor for the baseline AGC decay time = 16
101: Multiplication factor for the baseline AGC decay time = 32
110: Multiplication factor for the baseline AGC decay time = 64
111: Multiplication factor for the baseline AGC decay time = 128
1:0
Reserved
R/W
0h
Reserved. Always write zeros to these bits.
(1) Decay time is limited based on the NCODEC ratio that is selected. For NCODEC = 1, maximum decay time = 4 s; NCODEC = 1.5,
maximum decay time = 5.6 s; NCODEC = 2, maximum decay time = 8 s; NCODEC = 2.5, maximum decay time = 9.6 s; NCODEC = 3
or 3.5, maximum decay time = 11.2 s; NCODEC = 4 or 4.5, maximum decay time = 16 s; NCODEC = 5, maximum decay time = 19.2 s;
and NCODEC = 5.5 or 6, maximum decay time = 22.4 s.
7.6.2.84 Registers 105–106: Reserved (address = 69h–6Ah) [reset = 0000 0000], Page 0
Figure 114. Register 105
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 92. Register 105 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Always write zeros to these bits.
7:0
R/W
0h
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7.6.2.85 Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register (address =
6Bh) [reset = 0000 0000], Page 0
Figure 115. Register 107
7
6
0
5
0
4
0
3
2
1
0
0
Channel High-Pass
Filter Coefficient
Selection
ADC Digital Output to
Programmable Filter
Path Selection
I2C Bus Condition
Detector
I2C Bus Error
Detection Status
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R-0h
R-0h
Table 93. Register 107 Field Descriptions
Bit
Field
Type
Reset
Description
7
Channel High-Pass Filter Coefficient R/W
Selection
0h
Channel high-pass filter coefficient selection.
0: Default coefficients are used when ADC high pass is enabled
1: Programmable coefficients are used when ADC high pass is
enabled
6:4
3
Reserved
R/W
R/W
0h
0h
Reserved. Always write zeros to these bits.
ADC Digital Output to
Programmable Filter Path Selection
ADC digital output to programmable filter path selection.
0: No additional programmable filters other than the HPF are
used for the ADC
1: The programmable filter is connected to the ADC output if
both DACs are powered down
2
I2C Bus Condition Detector
R/W
0h
I2C bus condition detector.
0: Internal logic is enabled to detect an I2C bus error and clears
the bus error condition
1: Internal logic is disabled to detect an I2C bus error
1
0
Reserved
I2C Bus Error Detection Status
R
R
0h
0h
Reserved. Always write zero to this bit
I2C bus error detection status.
0: I2C bus error is not detected
1: I2C bus error is detected; this bit is cleared by reading this
register
82
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7.6.2.86 Register 108: Passive Analog Signal Bypass Selection During Power Down Register (address =
6Ch) [reset = 0000 0000], Page 0
Figure 116. Register 108
7
0
6
0
5
4
3
0
2
0
1
0
LINE1RM Path
Selection
LINE1RP Path
Selection
LINE1LM Path
Selection
LINE1LP Path
Selection
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 94. Register 108 Field Descriptions(1)
Bit
7:6
5
Field
Type
R/W
R/W
Reset
0h
Description
Reserved
Reserved. Always write zeros to these bits.
LINE1RM Path Selection
0h
LINE1RM path selection.
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOM
4
LINE1RP Path Selection
R/W
0h
LINE1RP path selection.
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP
3:2
1
Reserved
R/W
R/W
0h
0h
Reserved. Always write zeros to these bits
LINE1LM Path Selection
LINE1LM path selection.
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOM
0
LINE1LP Path Selection
R/W
0h
LINE1LP path selection.
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP
(1) Based on the register 108 settings, if both LINE1 and LINE2 inputs are routed to the output at the same time, then the two switches
used for the connection short the two input signals together on the output pins. The shorting resistance between the two input pins is
two times the bypass switch resistance (Rdson). In general, avoid this shorting condition because higher drive currents are likely to occur
on the circuitry that feeds these two input pins of this device.
7.6.2.87 Register 109: DAC Quiescent Current Adjustment Register (address = 6Dh) [reset = 0000 0000],
Page 0
Figure 117. Register 109
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DAC Current Adjustment
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 95. Register 109 Field Descriptions
Bit
Field
Type
Reset
Description
7:8
DAC Current Adjustment
R/W
0h
DAC current adjustment.
00: Default
01: 50% increase in DAC reference current
10: Reserved
11: 100% increase in DAC reference current
5:0
Reserved
R/W
0h
Reserved. Always write zeros to these bits.
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7.6.2.88 Registers 110–127: Reserved (address = 6Eh–7Fh) [reset = 0000 0000], Page 0
Figure 118. Registers 110–127
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 96. Registers 110–127 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write zeros to these bits.
Reserved
R
0h
7.6.3 Page 1 Register Descriptions
These registers are held within page 1.
7.6.3.1 Register 0: Page Select Register (address = 0h) [reset = 0000 0000], Page 1
Figure 119. Register 0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Page Select Bit
R/W-0h
X-0h
X-0h
X-0h
X-0h
X-0h
X-0h
X-0h
Table 97. Register 0 Field Descriptions
Bit
7:1
0
Field
Type
X
Reset
0h
Description
Reserved
Reserved. Always write zeros to these bits.
Page Select Bit
R/W
0h
Page select bit.
Writing zero to this bit sets page 0 as the active page for
following register accesses. Writing a one to this bit sets page 1
as the active page for following register accesses. This register
bit is recommended to be read back after each write to ensure
that the proper page is being accessed for future register
read/writes. This register has the same functionality on page 0
and page 1.
7.6.3.2 Register 1: Audio Effects Filter N0 Coefficient MSB Register (address = 1h) [reset = 0110 1011],
Page 1
Figure 120. Register 1
7
6
5
4
3
2
1
0
Audio Effects Filter N0 Coefficient MSB
R/W-0h R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
Table 98. Register 1 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N0 Coefficient R/W
MSB(1)
0110 1011h
Audio effects filter N0 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
(1) When programming any coefficient value in page 1, always write the MSB register first, immediately followed by the LSB register. Even
if only the MSB or LSB of the coefficient changes, write both registers in this sequence.
84
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7.6.3.3 Register 2: Audio Effects Filter N0 Coefficient LSB Register (address = 2h) [reset = 1110 0011],
Page 1
Figure 121. Register 2
7
6
5
4
3
2
1
0
Audio Effects Filter N0 Coefficient LSB
R/W-0h R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
Table 99. Register 2 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N0 Coefficient R/W
LSB
1110 0011h
Audio effects filter N0 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.4 Register 3: Audio Effects Filter N1 Coefficient MSB Register (address = 3h) [reset = 1001 0110],
Page 1
Figure 122. Register 3
7
6
5
4
3
2
1
0
Audio Effects Filter N1 Coefficient MSB
R/W-0h R/W-1h R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 100. Register 3 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N1 Coefficient R/W
MSB
1001 0110h
Audio effects filter N1 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.5 Register 4: Audio Effects Filter N1 Coefficient LSB Register (address = 4h) [reset = 0110 0110],
Page 1
Figure 123. Register 4
7
6
5
4
3
2
1
0
Audio Effects Filter N1 Coefficient LSB
R/W-0h R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 101. Register 4 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N1 Coefficient R/W
LSB
0110 0110h
Audio effects filter N1 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
Copyright © 2017, Texas Instruments Incorporated
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7.6.3.6 Register 5: Audio Effects Filter N2 Coefficient MSB Register (address = 5h) [reset = 0110 0111],
Page 1
Figure 124. Register 5
7
6
5
4
3
2
1
0
Audio Effects Filter N2 Coefficient MSB
R/W-1h R/W-0h R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
Table 102. Register 5 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N2 Coefficient R/W
MSB
0110 0111h
Audio effects filter N2 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.7 Register 6: Audio Effects Filter N2 Coefficient LSB Register (address = 6h) [reset = 0101 1101],
Page 1
Figure 125. Register 6
7
6
5
4
3
2
1
0
Audio Effects Filter N2 Coefficient LSB
R/W-1h R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
Table 103. Register 6 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N2 Coefficient R/W
LSB
0101 1101h
Audio effects filter N2 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.8 Register 7: Audio Effects Filter N3 Coefficient MSB Register (address = 7h) [reset = 0110 1011],
Page 1
Figure 126. Register 7
7
6
5
4
3
2
1
0
Audio Effects Filter N3 Coefficient MSB
R/W-0h R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
Table 104. Register 7 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N3 Coefficient R/W
MSB
0110 1011h
Audio effects filter N3 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
86
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7.6.3.9 Register 8: Audio Effects Filter N3 Coefficient LSB Register (address = 8h) [reset = 1110 0011],
Page 1
Figure 127. Register 8
7
6
5
4
3
2
1
0
Audio Effects Filter N3 Coefficient LSB
R/W-0h R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
Table 105. Register 8 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N3 Coefficient R/W
LSB
1110 0011h
Audio effects filter N3 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.10 Register 9: Audio Effects Filter N4 Coefficient MSB Register (address = 9h) [reset = 1001 0110],
Page 1
Figure 128. Register 9
7
6
5
4
3
2
1
0
Audio Effects Filter N4 Coefficient MSB
R/W-1h R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 106. Register 9 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N4 Coefficient R/W
MSB
1001 0110h
Audio effects filter N4 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.11 Register 10: Audio Effects Filter N4 Coefficient LSB Register (address = Ah) [reset = 0110 0110],
Page 1
Figure 129. Register 10
7
6
5
4
3
2
1
0
Audio Effects Filter N4 Coefficient LSB
R/W-0h R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 107. Register 10 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N4 Coefficient R/W
LSB
0110 0110h
Audio effects filter N4 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
Copyright © 2017, Texas Instruments Incorporated
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7.6.3.12 Register 11: Audio Effects Filter N5 Coefficient MSB Register (address = Bh) [reset =
0110 0111], Page 1
Figure 130. Register 11
7
6
5
4
3
2
1
0
Audio Effects Filter N5 Coefficient MSB
R/W-0h R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
Table 108. Register 11 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N5 Coefficient R/W
MSB
0110 0111h
Audio effects filter N5 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.13 Register 12: Audio Effects Filter N5 Coefficient LSB Register (address = Ch) [reset = 0101 1101],
Page 1
Figure 131. Register 12
7
6
5
4
3
2
1
0
Audio Effects Filter N5 Coefficient LSB
R/W-1h R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
Table 109. Register 12 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter N5 Coefficient R/W
LSB
0101 1101h
Audio effects filter N5 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.14 Register 13: Audio Effects Filter D1 Coefficient MSB Register (address = Dh) [reset =
0111 1101], Page 1
Figure 132. Register 13
7
6
5
4
3
2
1
0
Audio Effects Filter D1 Coefficient MSB
R/W-1h R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
Table 110. Register 13 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter D1 Coefficient R/W
MSB
0111 1101h
Audio effects filter D1 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
88
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7.6.3.15 Register 14: Audio Effects Filter D1 Coefficient LSB Register (address = Eh) [reset =
1000 0011h], Page 1
Figure 133. Register 14
7
6
5
4
3
2
1
0
Audio Effects Filter D1 Coefficient LSB
R/W-0h R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 111. Register 14 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter D1 Coefficient R/W
LSB
1000 0011h
Audio effects filter D1 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.16 Register 15: Audio Effects Filter D2 Coefficient MSB Register (address = Fh) [reset = 1000 0100],
Page 1
Figure 134. Register 15
7
6
5
4
3
2
1
0
Audio Effects Filter D2 Coefficient MSB
R/W-0h R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
Table 112. Register 15 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter D2 Coefficient R/W
MSB
1000 0100h
Audio effects filter D2 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.17 Register 16: Audio Effects Filter D2 Coefficient LSB Register (address = 10h) [reset =
1110 1110], Page 1
Figure 135. Register 16
7
6
5
4
3
2
1
0
Audio Effects Filter D2 Coefficient LSB
R/W-0h R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 113. Register 16 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter D2 Coefficient R/W
LSB
1110 1110h
Audio effects filter D2 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
Copyright © 2017, Texas Instruments Incorporated
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7.6.3.18 Register 17: Audio Effects Filter D4 Coefficient MSB Register (address = 11h) [reset =
0111 1101], Page 1
Figure 136. Register 17
7
6
5
4
3
2
1
0
Audio Effects Filter D4 Coefficient MSB
R/W-1h R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
Table 114. Register 17 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter D4 Coefficient R/W
MSB
0111 1101h
Audio effects filter D4 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.19 Register 18: Audio Effects Filter D4 Coefficient LSB Register (address = 12h) [reset =
1000 0011], Page 1
Figure 137. Register 18
7
6
5
4
3
2
1
0
Audio Effects Filter D4 Coefficient LSB
R/W-0h R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 115. Register 18 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter D4 Coefficient R/W
LSB
1000 0011h
Audio effects filter D4 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.20 Register 19: Audio Effects Filter D5 Coefficient MSB Register (address = 13h) [reset =
1000 0100], Page 1
Figure 138. Register 19
7
6
5
4
3
2
1
0
Audio Effects Filter D5 Coefficient MSB
R/W-0h R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
Table 116. Register 19 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter D5 Coefficient R/W
MSB
1000 0100h
Audio effects filter D5 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
90
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7.6.3.21 Register 20: Audio Effects Filter D5 Coefficient LSB Register (address = 14h) [reset =
1110 1110], Page 1
Figure 139. Register 20
7
6
5
4
3
2
1
0
Audio Effects Filter D5 Coefficient LSB
R/W-0h R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 117. Register 20 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Audio Effects Filter D5 Coefficient R/W
LSB
1110 1110h
Audio effects filter D5 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.22 Register 21: De-Emphasis Filter N0 Coefficient MSB Register (address = 15h) [reset =
0011 1001], Page 1
Figure 140. Register 21
7
6
5
4
3
2
1
0
De-Emphasis Filter N0 Coefficient MSB
R/W-1h R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
Table 118. Register 21 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
De-Emphasis Filter N0 Coefficient R/W
MSB
0011 1001h
De-emphasis filter N0 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.23 Register 22: De-Emphasis Filter N0 Coefficient LSB Register (address = 16h) [reset =
0101 0101], Page 1
Figure 141. Register 22
7
6
5
4
3
2
1
0
De-Emphasis Filter N0 Coefficient LSB
R/W-1h R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
Table 119. Register 22 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
De-Emphasis Filter N0 Coefficient R/W
LSB
0101 0101h
De-emphasis filter N0 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
Copyright © 2017, Texas Instruments Incorporated
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7.6.3.24 Register 23: De-Emphasis Filter N1 Coefficient MSB Register (address = 17h) [reset =
1111 0011], Page 1
Figure 142. Register 23
7
6
5
4
3
2
1
0
De-Emphasis Filter N1 Coefficient MSB
R/W-1h R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
Table 120. Register 23 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
De-Emphasis Filter N1 Coefficient R/W
MSB
1111 0011h
De-emphasis filter N1 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.25 Register 24: De-Emphasis Filter N1 Coefficient LSB Register (address = 18h) [reset =
0010 1101], Page 1
Figure 143. Register 24
7
6
5
4
3
2
1
0
De-Emphasis Filter N1 Coefficient LSB
R/W-0h R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
Table 121. Register 24 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
De-Emphasis Filter N1 Coefficient R/W
LSB
0010 1101h
De-emphasis filter N1 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.26 Register 25: De-Emphasis Filter D1 Coefficient MSB Register (address = 19h) [reset =
0101 0011], Page 1
Figure 144. Register 25
7
6
5
4
3
2
1
0
De-Emphasis Filter D1 Coefficient MSB
R/W-1h R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 122. Register 25 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
De-Emphasis Filter D1 Coefficient R/W
MSB
0101 0011h
De-emphasis filter D1 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
92
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ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
7.6.3.27 Register 26: De-Emphasis Filter D1 Coefficient LSB Register (address = 1Ah) [reset =
0111 1110], Page 1
Figure 145. Register 26
7
6
5
4
3
2
1
0
De-Emphasis Filter D1 Coefficient LSB
R/W-1h R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 123. Register 26 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
De-Emphasis Filter D1 Coefficient R/W
LSB
0111 1110h
De-emphasis filter D1 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.28 Register 27: Reserved (address = 1Bh) [reset = 0110 1011], Page 1
Figure 146. Register 27
7
0
6
1
5
1
4
0
3
1
2
0
1
1
0
1
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
Table 124. Register 27 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0110 1011 to these bits.
Reserved
R/W
0110 1011h
7.6.3.29 Register 28: Reserved (address = 1Ch) [reset = 1110 0011], Page 1
Figure 147. Register 28
7
1
6
1
5
1
4
0
3
0
2
0
1
1
0
1
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 125. Register 28 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1110 0011 to these bits.
Reserved
R/W
1110 0011h
7.6.3.30 Register 29: Reserved (address = 1Dh) [reset = 1001 0110], Page 1
Figure 148. Register 29
7
1
6
0
5
0
4
1
3
0
2
1
1
1
0
0
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 126. Register 29 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1001 0110 to these bits.
Reserved
R/W
1001 0110h
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7.6.3.31 Register 30: Reserved (address = 1Eh) [reset = 0110 0110], Page 1
Figure 149. Register 30
7
0
6
1
5
1
4
0
3
0
2
1
1
1
0
0
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 127. Register 30 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0110 0110 to these bits.
Reserved
R/W
0110 0110h
7.6.3.32 Register 31: Reserved (address = 1Fh) [reset = 0110 0111], Page 1
Figure 150. Register 31
7
0
6
1
5
1
4
0
3
0
2
1
1
1
0
1
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
Table 128. Register 31 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0110 0111 to these bits.
Reserved
R/W
0110 0111h
7.6.3.33 Register 32: Reserved (address = 20h) [reset = 0101 1101], Page 1
Figure 151. Register 32
7
0
6
1
5
0
4
1
3
1
2
1
1
0
0
1
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
Table 129. Register 32 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0101 1101 to these bits.
Reserved
R/W
0101 1101h
7.6.3.34 Register 33: Reserved (address = 21h) [reset = 0110 1011], Page 1
Figure 152. Register 33
7
0
6
1
5
1
4
0
3
1
2
0
1
1
0
1
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
Table 130. Register 33 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0110 1011 to these bits.
Reserved
R/W
0110 1011h
94
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7.6.3.35 Register 34: Reserved (address = 22h) [reset = 1110 0011], Page 1
Figure 153. Register 34
7
1
6
1
5
1
4
0
3
0
2
0
1
1
0
1
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 131. Register 34 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1110 0011 to these bits.
Reserved
R/W
1110 0011h
7.6.3.36 Register 35: Reserved (address = 23h) [reset = 1001 0110], Page 1
Figure 154. Register 35
7
1
6
0
5
0
4
1
3
0
2
1
1
1
0
0
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 132. Register 35 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1001 0110 to these bits.
Reserved
R/W
1001 0110h
7.6.3.37 Register 36: Reserved (address = 24h) [reset = 0110 0110], Page 1
Figure 155. Register 36
7
0
6
1
5
1
4
0
3
0
2
1
1
1
0
0
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 133. Register 36 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0110 0110 to these bits.
Reserved
R/W
0110 0110h
7.6.3.38 Register 37: Reserved (address = 25h) [reset = 0110 0111], Page 1
Figure 156. Register 37
7
0
6
1
5
1
4
0
3
0
2
1
1
1
0
1
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
Table 134. Register 37 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0110 0111 to these bits.
Reserved
R/W
0110 0111h
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7.6.3.39 Register 38: Reserved (address = 26h) [reset = 0101 1101], Page 1
Figure 157. Register 38
7
0
6
1
5
0
4
1
3
1
2
1
1
0
0
1
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
Table 135. Register 38 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0101 1101 to these bits.
Reserved
R/W
0101 1101h
7.6.3.40 Register 39: Reserved (address = 27h) [reset = 0111 1101], Page 1
Figure 158. Register 39
7
0
6
1
5
1
4
1
3
1
2
1
1
0
0
1
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
Table 136. Register 39 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0111 1101 to these bits.
Reserved
R/W
0111 1101h
7.6.3.41 Register 40: Reserved (address = 28h) [reset = 1000 0011], Page 1
Figure 159. Register 40
7
1
6
0
5
0
4
0
3
0
2
0
1
1
0
1
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 137. Register 40 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1000 0011 to these bits.
Reserved
R/W
1000 0011h
7.6.3.42 Register 41: Reserved (address = 29h) [reset = 1000 0100], Page 1
Figure 160. Register 41
7
1
6
0
5
0
4
0
3
0
2
1
1
0
0
0
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
Table 138. Register 41 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1000 0100 to these bits.
Reserved
R/W
1000 0100h
96
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7.6.3.43 Register 42: Reserved (address = 2Ah) [reset = 1110 1110], Page 1
Figure 161. Register 42
7
1
6
1
5
1
4
0
3
1
2
1
1
1
0
0
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 139. Register 42 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1110 1110 to these bits.
Reserved
R/W
1110 1110h
7.6.3.44 Register 43: Reserved (address = 2Bh) [reset = 0111 1101], Page 1
Figure 162. Register 43
7
0
6
1
5
1
4
1
3
1
2
1
1
0
0
1
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
Table 140. Register 43 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0111 1101 to these bits.
Reserved
R/W
0111 1101h
7.6.3.45 Register 44: Reserved (address = 2Ch) [reset = 1000 0011], Page 1
Figure 163. Register 44
7
1
6
0
5
0
4
0
3
0
2
0
1
1
0
1
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 141. Register 44 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1000 0011 to these bits.
Reserved
R/W
1000 0011h
7.6.3.46 Register 45: Reserved (address = 2Dh) [reset = 1000 0100], Page 1
Figure 164. Register 45
7
1
6
0
5
0
4
0
3
0
2
1
1
0
0
0
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
Table 142. Register 45 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1000 0100 to these bits.
Reserved
R/W
1000 0100h
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7.6.3.47 Register 46: Reserved (address = 2Eh) [reset = 1110 1110], Page 1
Figure 165. Register 46
7
1
6
1
5
1
4
0
3
1
2
1
1
1
0
0
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 143. Register 46 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1110 1110 to these bits.
Reserved
R/W
1110 1110h
7.6.3.48 Register 47: Reserved (address = 2Fh) [reset = 0011 1001], Page 1
Figure 166. Register 47
7
0
6
0
5
1
4
1
3
1
2
0
1
0
0
1
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
Table 144. Register 47 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0011 1001 to these bits.
Reserved
R/W
0011 1001h
7.6.3.49 Register 48: Reserved (address = 30h) [reset = 0101 0101], Page 1
Figure 167. Register 48
7
0
6
1
5
0
4
1
3
0
2
1
1
0
0
1
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
Table 145. Register 48 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0101 0101 to these bits.
Reserved
R/W
0101 0101h
7.6.3.50 Register 49: Reserved (address = 31h) [reset = 1111 0011], Page 1
Figure 168. Register 49
7
1
6
1
5
1
4
1
3
0
2
0
1
1
0
1
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 146. Register 49 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1111 0011 to these bits.
Reserved
R/W
1111 0011h
98
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7.6.3.51 Register 50: Reserved (address = 32h) [reset = 0010 1101], Page 1
Figure 169. Register 50
7
0
6
0
5
1
4
0
3
1
2
1
1
0
0
1
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
Table 147. Register 50 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0010 1101 to these bits.
Reserved
R/W
0010 1101h
7.6.3.52 Register 51: Reserved (address = 33h) [reset = 0101 0011], Page 1
Figure 170. Register 51
7
0
6
1
5
0
4
1
3
0
2
0
1
1
0
1
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
Table 148. Register 51 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0101 0011 to these bits.
Reserved
R/W
0101 0011h
7.6.3.53 Register 52: Reserved (address = 34h) [reset = 0111 1110], Page 1
Figure 171. Register 52
7
0
6
1
5
1
4
1
3
1
2
1
1
1
0
0
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 149. Register 52 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0111 1110 to these bits.
Reserved
R/W
0111 1110h
7.6.3.54 Register 53: Reserved (address = 35h) [reset = 0111 1111], Page 1
Figure 172. Register 53
7
0
6
1
5
1
4
1
3
1
2
1
1
1
0
1
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
Table 150. Register 53 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0111 1111 to these bits.
Reserved
R/W
0111 1111h
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7.6.3.55 Register 54: Reserved (address = 36h) [reset = 1111 1111], Page 1
Figure 173. Register 54
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
Table 151. Register 54 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write ones to these bits.
Reserved
R/W
1h
7.6.3.56 Registers 55–64: Reserved (address = 37h–40h) [reset = 0000 0000], Page 1
Figure 174. Registers 55–64
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 152. Registers 55–64 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write zeros to these bits.
Reserved
R/W
0h
7.6.3.57 Register 65: ADC High-Pass Filter N0 Coefficient MSB Register (address = 41h) [reset =
0011 1001], Page 1
Figure 175. Register 65
7
6
5
4
3
2
1
0
ADC High-Pass Filter N0 Coefficient MSB
R/W-1h R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-1h
Table 153. Register 65 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
ADC High-Pass Filter N0
Coefficient MSB
R/W
0011 1001h
ADC high-pass filter N0 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.58 Register 66: ADC High-Pass Filter N0 Coefficient LSB Register (address = 42h) [reset = 1110
1010], Page 1
Figure 176. Register 66
7
6
5
4
3
2
1
0
Channel ADC High-Pass Filter N0 Coefficient LSB
R/W-1h R/W-0h R/W-1h R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
Table 154. Register 66 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Channel ADC High-Pass Filter N0 R/W
Coefficient LSB
1110 1010h
Channel ADC high-pass filter N0 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
100
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ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
7.6.3.59 Register 67: Channel ADC High-Pass Filter N1 Coefficient MSB Register (address = 43h) [reset
= 1000 0000 , Page 1
Figure 177. Register 67
7
6
5
4
3
2
1
0
Channel ADC High-Pass Filter N1 Coefficient MSB
R/W-0h R/W-0h R/W-0h R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
Table 155. Register 67 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Channel ADC High-Pass Filter N1 R/W
Coefficient MSB
1000 0000h
Channel ADC high-pass filter N1 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.60 Register 68: Channel ADC High-Pass Filter N1 Coefficient LSB Register (address = 44h) [reset =
0001 0110], Page 1
Figure 178. Register 68
7
6
5
4
3
2
1
0
Channel ADC High-Pass Filter N1 Coefficient LSB
R/W-0h R/W-1h R/W-0h R/W-1h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
Table 156. Register 68 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Channel ADC High-Pass Filter N1 R/W
Coefficient LSB
0001 0110h
Channel ADC high-pass filter N1 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.61 Register 69: Channel ADC High-Pass Filter D1 Coefficient MSB Register (address = 45h) [reset
= 0111 1111], Page 1
Figure 179. Register 69
7
6
5
4
3
2
1
0
Channel ADC High-Pass Filter D1 Coefficient MSB
R/W-1h R/W-1h R/W-1h R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
Table 157. Register 69 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Channel ADC High-Pass Filter D1 R/W
Coefficient MSB
0111 1111h
Channel ADC high-pass filter D1 coefficient MSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
Copyright © 2017, Texas Instruments Incorporated
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7.6.3.62 Register 70: Channel ADC High-Pass Filter D1 Coefficient LSB Register (address = 46h) [reset =
1101 0101], Page 1
Figure 180. Register 70
7
6
5
4
3
2
1
0
Channel ADC High-Pass Filter D1 Coefficient LSB
R/W-0h R/W-1h R/W-0h R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
Table 158. Register 70 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Channel ADC High-Pass Filter D1 R/W
Coefficient LSB
1101 0101h
Channel ADC high-pass filter D1 coefficient LSB.
The 16-bit integer contained in the MSB and LSB registers
for this coefficient are interpreted as a 2's-complement
integer with possible values ranging from –32,768 to 32,767.
7.6.3.63 Register 71: Reserved (address = 47h) [reset = 0111 1111], Page 1
Figure 181. Register 71
7
0
6
1
5
1
4
1
3
1
2
1
1
1
0
1
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
Table 159. Register 71 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0111 1111 to these bits.
Reserved
R/W
0111 1111h
7.6.3.64 Register 72: Reserved (address = 48h) [reset = 1110 1010], Page 1
Figure 182. Register 72
7
1
6
1
5
1
4
0
3
1
2
0
1
1
0
0
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
Table 160. Register 72 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1110 1010 to these bits.
Reserved
R/W
1110 1010h
7.6.3.65 Register 73: Reserved (address = 49h) [reset = 1000 0000], Page 1
Figure 183. Register 73
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 161. Register 73 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1000 0000 to these bits.
Reserved
R/W
1000 0000h
102
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7.6.3.66 Register 74: Reserved (address = 4Ah) [reset = 0001 0110], Page 1
Figure 184. Register 74
7
0
6
0
5
0
4
1
3
0
2
1
1
1
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
Table 162. Register 74 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0001 0110 to these bits.
Reserved
R/W
0001 0110h
7.6.3.67 Register 75: Reserved (address = 4Bh) [reset = 0111 1111], Page 1
Figure 185. Register 75
7
0
6
1
5
1
4
1
3
1
2
1
1
1
0
1
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
Table 163. Register 75 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 0111 1111 to these bits.
Reserved
R/W
0111 1111h
7.6.3.68 Register 76: Reserved (address = 4Ch) [reset = 1101 0101], Page 1
Figure 186. Register 76
7
1
6
1
5
0
4
1
3
0
2
1
1
0
0
1
R/W-1h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
Table 164. Register 76 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
Reserved. Always write 1101 0101 to these bits.
Reserved
R/W
1101 0101h
7.6.3.69 Registers 77h–127h: Reserved (address = 4Dh) [reset = 0000 0000], Page 1
Figure 187. Registers 77h–127h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 165. Registers 77h–127h Field Descriptions
Bit
7-0
Field
Type
Reset
Description
Reserved. Always write zeros to these bits.
Reserved
R
0h
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV320AIC3109-Q1 is a highly integrated low-power mono audio codec with integrated headphone and line
amplifiers. All features of the TLV320AIC3109-Q1 are accessed by programmable registers. An external
processor with I2C protocol is required to control the device. Good practice is to perform a hardware reset after
initial power-up to ensure that all registers are in default states. Extensive register-based power control is
included, enabling mono 48-kHz DAC playback as low as 14-mW from a 3.3-V analog supply, making the device
ideal for portable battery-powered audio applications.
8.2 Typical Application
Governing bodies around the world have implemented specific legislation to require automotive companies to
install emergency call (E-Call) systems in order to reduce emergency response times and thereby save lives. E-
Call systems are activated during a collision or emergency situation and automatically facilitate a call to
emergency services. The state of a vehicle after a collision is difficult to predict and can include a disconnected
battery, trapped passengers, and a noisy environment. For this reason, the E-Call module must have its own
battery power source and be able to sustain a hands-free call for at least ten minutes (depending on specific
regional legislation). The TLV320AIC3109-Q1 as an audio codec and the TAS5411-Q1 as an audio amplifier are
optimal choices for an E-Call application because these devices offers low power consumption and still allow a
loud and clear conversation with an emergency operator.
104
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TLV320AIC3109-Q1
www.ti.com.cn
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
Typical Application (接下页)
IOVDD
Wireless Module and
I2C Control
RP
RP
AVDD
AVDD
DRVDD
DRVDD
0.1 mF
1 mF
1 mF
MICBIAS
1 kW
0.1µF
1mF
0.1µF
0.1 mF
0.1 mF
MIC1P/LINE1P
MIC1M/LINE1M
IOVDD
0.1µF
ANALOG
GROUND
IOVDD
DVDD
1 mF
DVDD
TI Device
1 kW
0.1µF
1µF
DVSS
MIC2P/LINE2P
MIC2M/LINE2M
DIGITAL
GROUND
(OPTIONAL
MIC/LINE)
AVSS
AVSS
DRVSS
ANALOG
GROUND
(OPTIONAL HEADPHONE)
TAS5411-Q1 OR SIMILAR
TAS5411-Q1 OR SIMILAR
Copyright © 2017, Texas Instruments Incorporated
图 188. Typical Connections for Emergency Call System (E-Call)
8.2.1 Design Requirements
表 166 shows the parameters used for this application.
表 166. Design Parameters
PARAMETER
AVDD, DRVDD
VALUE
3.3 V
IOVDD, DVDD
1.8 V
MCLK frequency
12.288 MHz
3.072 MHz
48 KHz
BCLK frequency
WCLK frequency (sample rate)
Current consumption (AVDD + DRVDD)
Current consumption (DVDD + IOVDD)
Total power consumption
4.31 mA
2.45 mA
20 mW
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www.ti.com.cn
8.2.2 Detailed Design Procedure
The audio codec in an E-Call system must be able to support full duplex communication between the digital
audio source from the wireless module, the microphone input, and the speaker output. The TLV320AIC3109-Q1
is a mono audio codec that meets the low power requirements and has all the features necessary for an E-Call
application.
The wireless module communicates to the audio codec through I2S interface. The class-D amplifier must
maintain sufficient output power to drive the speaker to the specified audio level with sufficient audio quality. The
amplifier must also have high efficiency to optimize power consumption and good EMI, EMC performance. In
addition, many E-Call systems require speaker diagnostics and device protection circuitry.
The TLV320AIC3109-Q1 is a low-power mono audio codec that integrates a mono preamplifier and offers
multiple inputs and outputs that are programmable in single-ended or fully differential configurations. The
TLV320AIC3109-Q1 flexible configuration allows certain internal blocks to be enabled or bypassed. This flexibility
allows for optimal power consumption, which is very important for E-Call systems.
The TAS5411-Q1 is a mono digital class-D audio amplifier ideal for use in automotive emergency call, telematics,
instrument cluster, and infotainment applications. The device provides up to 8 W into 4 Ω at less than 10%
THD+N from a 14.4-Vdc automotive battery. The wide operating voltage range and excellent efficiency make the
device ideal for start-stop support or running from a backup battery when required. The integrated load-dump
protection reduces external voltage clamp cost and size, and the onboard load diagnostics report the status of
the speaker through I2C interface.
Following the recommended component placement (see the schematic layout and routing provided in the Layout
section), integrate the TLV320AIC3109-Q1 and supporting components into the system PCB design.
Determining sample rate and master clock frequency is required because all internal timing are derived from the
master clock during power-up. See the Audio Clock Generation section for more information on how to configure
the required clocks for the device.
When powered up, the device has several features powered down because the audio codec device is designed
for low-power applications. Correct routing of the signals internal to the TLV320AIC3109-Q1 is achieved by
correctly setting the device registers, powering up the required stages of the device, and configuring the internal
switches for desired performance.
8.2.3 Application Curves
As shown in 图 189, the TAS5411-Q1 can reach up to 83% into a 4-Ω load. Output power can be up to 8 W at
10% THD+N into a 4-Ω load.
The TLV320AIC3109-Q1 features a configurable MICBIAS level (that is, 2 V, 2.5 V, or AVDD). As shown in 图
190, 2-V and 2.5-V MICBIAS levels remain stable with changes in the AVDD supply voltage. When the MICBIAS
output voltage is configured as AVDD, the MICBIAS output voltage follows AVDD.
3.6
3.4
3.2
MICBIAS = AVDD
3.0
2.8
MICBIAS = 2.5 V
2.6
2.4
2.2
2.0
1.8
MICBIAS = 2 V
TAS5411-Q1 Efficiency
2.7
2.8
2.9
3.0 3.1
3.2
3.3
3.4
3.5
3.6
AVDD - Supply Voltage - V
G007
图 189. Efficiency Curve for the TAS5411-Q1
图 190. MICBIAS Output Voltage vs AVDD for the
TLV320AIC3109-Q1
106
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TLV320AIC3109-Q1
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ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
9 Power Supply Recommendations
The TLV320AIC3109-Q1 is designed to be extremely tolerant of power-supply sequencing. However, in some
rare instances, unexpected conditions can be attributed to power-supply sequencing. The following sequence
provides the most robust operation.
Power-up IOVDD first. Power-up the analog supplies, which includes AVDD and DRVDD, second. Power-up the
digital supply DVDD last. Keep RESET low until all supplies are stable. The analog supplies must be greater
than or equal to DVDD at all times. 图 191 and 表 167 detail the preferred power-supply sequence.
IOVDD
t1
AVDD, DRVDD
t2
DVDD
t3
图 191. TLV320AIC3109-Q1 Power-Supply Sequencing
表 167. TLV320AIC3109-Q1 Power-Supply Sequencing
MIN
0
MAX UNIT
t1
t2
t3
IOVDD to AVDD, DRVDD
AVDD to DVDD
ms
0
5
ms
ms
IOVDD, to DVDD
0
10 Layout
10.1 Layout Guidelines
Printed circuit board (PCB) design is made considering the application, and the review is specific for each system
requirements. However, general considerations can optimize the system performance:
•
•
Connect the TLV320AIC3109-Q1 thermal pad to the analog output driver ground
Separate the analog and digital grounds to prevent possible digital noise from affecting the analog
performance of the board
•
•
The TLV320AIC3109-Q1 requires the decoupling capacitors to be placed as close as possible to the device
power-supply terminals
If possible, route the differential audio signals differentially on the PCB to obtain better noise immunity
版权 © 2017, Texas Instruments Incorporated
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ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
www.ti.com.cn
10.2 Layout Example
Analog Ground Plane
Digital Ground Plane
2.7 kꢁ
2.7 kꢁ
System
Processor
Thermal Pad Connected to
Analog Ground Plane
16
15
14
13
12
11
10
9
17
8
7
6
5
4
3
2
1
AVSS
0.1 ꢀF
18
DRVDD
IOVDD
19
NC
DVSS
20
NC
10 ꢀF
Thermal Pad
21
DRVSS
22
23
24
HPCOM
HPOUT
0.1 ꢀF
25
26
27
28
29
30
31
32
10 ꢀF
TLV320AIC3109
0.1 ꢀF
0.1 ꢀF
10 ꢀF
10 ꢀF
Decoupling Capacitors
Close to Supply Pins
System
Processor
10 kꢁ
If Possible, Route Differential
Audio Signals Differently
IOVDD
Via To Analog Ground Layer
Via To Digital Ground Layer
Top Layer Signal Traces
Ground Layer
图 192. Layout Example
108
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TLV320AIC3109-Q1
www.ti.com.cn
ZHCSGM5A –AUGUST 2017–REVISED NOVEMBER 2017
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
《具有负载突降和 I2C 诊断功能的 TAS5411-Q1 8W 单声道汽车 D 类音频放大器》
11.2 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
109
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
6PAIC3109TRHBRQ1
ACTIVE
ACTIVE
VQFN
VQFN
RHB
RHM
32
32
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
3109T
3109TW
Samples
Samples
6PAIC3109TWRHMRQ1
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
6PAIC3109TRHBRQ1
VQFN
RHB
RHM
32
32
3000
3000
330.0
330.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.1
8.0
8.0
12.0
12.0
Q2
Q2
6PAIC3109TWRHMRQ1 VQFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
6PAIC3109TRHBRQ1
VQFN
VQFN
RHB
RHM
32
32
3000
3000
367.0
346.0
367.0
346.0
35.0
33.0
6PAIC3109TWRHMRQ1
Pack Materials-Page 2
PACKAGE OUTLINE
RHM0032A
VQFNP - 0.9 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
0.05
0.00
(0.09)
PIN 1 ID
5.1
4.9
DETAIL A
DETAIL
SCALE 20.000
A
TYPICAL
(
4.75)
(0.15)
(0.15)
DETAIL
B
S
C
A
L
E
2
0
.
0
0
0
DETAIL B
TYPICAL
C
0.9 MAX
SEATING PLANE
0.08 C
(0.2)
SEE DETAIL A
3.7 0.1
SYMM
SEE DETAIL B
4X (45 X 0.6)
9
16
8
17
EXPOSED
THERMAL PAD
SYMM
33
4X
3.5
1
24
28X 0.5
0.30
0.18
32X
25
PIN 1 ID
(OPTIONAL)
32
0.1
C B A
C
0.5
32X
0.05
0.3
4219073/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHM0032A
VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.7)
4X (1.26)
4X (0.97)
32
25
32X (0.6)
1
24
32X (0.25)
4X
(0.97)
33
SYMM
4X
(4.8)
(1.26)
28X (0.5)
17
8
(
0.2) VIA
TYP
9
16
SYMM
(4.8)
(R0.05)
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219073/A 03/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHM0032A
VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(1.26 TYP)
32
25
32X (0.6)
33
1
24
32X (0.25)
(1.26)
TYP
SYMM
(4.8)
28X (0.5)
17
8
METAL
TYP
9
16
(R0.05)
TYP
4X ( 1.06)
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:18X
4219073/A 03/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
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