74ABT646CMSAX [TI]
ABT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, EIAJ TYPE2, PLASTIC, SSOP-24;
| 型号： | 74ABT646CMSAX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, EIAJ TYPE2, PLASTIC, SSOP-24 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1996
54ABT/74ABT646
Octal Transceivers and Registers with
TRI-STATE Outputs
É
General Description
Features
Y
Independent registers for A and B buses
The ’ABT646 consists of bus transceiver circuits with TRI-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus will
receive data when the enable control OE is Active LOW. In
the isolation mode (control OE HIGH), A data may be stored
in the B register and/or B data may be stored in the A regis-
ter.
Y
Multiplexed real-time and stored data
Y
A and B output sink capability of 64 mA, source capa-
bility of 32 mA
Y
Y
Y
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and 250 pF
loads
Y
Guaranteed simultaneous switching noise level and dy-
namic threshold performance
Y
Y
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Y
Y
Nondestructive hot insertion capability
Standard Military Drawing (SMD) 5962-9457701
Package
Commercial
Military
Package Description
Number
74ABT646CSC (Note 1)
M24B
24-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
54ABT646J/883
54ABT646W/883
J24A
24-Lead Ceramic Dual-In-Line
74ABT646CMSA (Note 1)
MSA24 24-Lead Molded Shrink Small Outline, EIAJ Type II
W24C
24-Lead Cerpak
54ABT5646E/883 E28A
28-Lead Ceramic Leadless Chip Carrier, Type C
74ABT646CMTC (Notes 1, 2)
MTC24 24-Lead Molded Thin Shrink Small Outline, JEDEC
e
Note 1: Devices also available in 13 reel. Use suffix
×
Note 2: Contact factory for package availability.
SCX, MSAX and MTCX.
Connection Diagrams
Pin Descriptions
Pin Assignment for
SOIC, SSOP and Flatpak
Pin Assignment for LCC
Pin
Description
Names
A –A
0
Data Register A Inputs/
TRI-STATE Outputs
Data Register B Inputs/
TRI-STATE Outputs
Clock Pulse Inputs
7
7
B –B
0
CPAB,
CPBA
SAB, SBA Select Inputs
OE
Output Enable Input
Direction Control Input
DIR
TL/F/10978–4
TL/F/10978–3
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
TL/F/10978
RRD-B30M96/Printed in U. S. A.
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Real Time Transfer
A-Bus to B-Bus
Real Time Transfer
B-Bus to A-Bus
Storage from
Bus to Register
Transfer from
Register to Bus
TL/F/10978–7
TL/F/10978–8
TL/F/10978–5
TL/F/10978–6
FIGURE 1
FIGURE 2
FIGURE 3
FIGURE 4
Inputs
Data I/O*
Function
OE DIR CPAB CPBA SAB SBA A –A B –B
7
0
7
0
H
H
H
X
X
X
H or L H or L
L
X
X
X
X
X
X
Isolation
Input Clock A Data into A Register
n
X
L
Input
X
Clock B Data into B Register
n
L
L
L
L
H
H
H
H
X
L
H or L
L
X
X
X
X
L
L
H
H
X
X
X
X
A to B ÐReal Time (Transparent Mode)
n n
Clock A Data into A Register
n
A Register to B (Stored Mode)
n
Clock A Data into A Register and Output to B
n
Input Output
n
L
L
L
L
L
L
L
L
X
X
X
X
X
L
H or L
L
X
X
X
X
L
L
H
H
B to A ÐReal Time (Transparent Mode)
n n
Clock B Data into B Register
n
B Register to A (Stored Mode)
n
Clock B Data into B Register and Output to A
n
Output Input
n
*The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always
enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
e
e
e
Immaterial
H
L
HIGH Voltage Level
LOW Voltage Level
X
e
L
LOW-to-HIGH Transition
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2
Logic Diagram
TL/F/10978–9
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
b
DC Latchup Source Current
Over Voltage Latchup (I/O)
500 mA
10V
b
b
a
65 C to 150 C
Storage Temperature
§
§
a
55 C to 125 C
Ambient Temperature under Bias
§
§
Recommended Operating
Conditions
Junction Temperature under Bias
Ceramic
Plastic
b
b
a
55 C to 175 C
§
§
a
55 C to 150 C
§
§
Free Air Ambient Temperature
Military
Commercial
V
Pin Potential to
CC
Ground Pin
b
b
a
55 C to 125 C
§
40 C to 85 C
§
b
a
0.5V to 7.0V
a
§
§
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Supply Voltage
Military
Commercial
b
a
30 mA to 5.0 mA
a
a
a
4.5V to 5.5V
a
4.5V to 5.5V
Voltage Applied to Any Output
in the Disable or Power-Off State
in the HIGH State
b
a
0.5V to 5.5V
b
Minimum Input Edge Rate
Data Input
Enable Input
(DV/Dt)
50 mV/ns
20 mV/ns
100 mV/ns
0.5V to V
CC
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Clock Input
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
ABT646
Typ
Symbol
Parameter
Units
V
CC
Conditions
Min
Max
V
Input HIGH Voltage
2.0
V
V
V
Recognized HIGH Signal
Recognized LOW Signal
IH
V
V
V
Input LOW Voltage
0.8
IL
b
e b
18 mA (Non I/O Pins)
Input Clamp Diode Voltage
1.2
Min
Min
I
CD
OH
IN
e b
e b
e b
Output HIGH Voltage 54ABT/74ABT 2.5
I
I
I
3 mA, (A , B )
n n
24 mA, (A , B )
OH
OH
OH
54ABT
74ABT
2.0
2.0
V
n n
32 mA, (A , B )
n
n
e
e
V
V
Output LOW Voltage 54ABT
74ABT
0.55
0.55
I
I
48 mA, (A , B )
n n
64 mA, (A , B )
OL
OL
OL
V
Min
0.0
n
n
e
1.9 mA, (Non-I/O Pins)
All Other Pins Grounded
Input Leakage Test
I
ID
ID
4.75
V
e
e
I
I
I
I
Input HIGH Current
5
5
V
V
2.7V (Non-I/O Pins) (Note 2)
(Non-I/O Pins)
IH
IN
IN
mA
mA
mA
mA
Max
Max
Max
Max
V
CC
e
Input HIGH Current
Breakdown Test
V
IN
7.0V (Non-I/O Pins)
BVI
BVIT
IL
7
e
Input HIGH Current
Breakdown Test (I/O)
V
IN
5.5V (A , B )
n n
100
b
b
e
e
Input LOW Current
5
5
V
IN
V
IN
0.5V (Non-I/O Pins) (Note 2)
0.0V (Non-I/O Pins)
a
e
e
e
e
e
e
e
I
I
I
I
I
I
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
50
mA
mA
mA
mA
0V–5.5V V
0V–5.5V V
2.7V (A , B ); OE
n
2.0V
2.0V
IH
OZH
OUT
OUT
OUT
OUT
OUT
n
a
b
50
I
0.5V (A , B ); OE
n n
IL
OZL
b
b
275
50
100
Max
Max
V
V
V
0V (A , B )
n n
OS
CEX
ZZ
V
CC
(A , B )
n n
5.5V (A , B );
n
n
100
mA
0.0V
All Others GND
I
I
I
I
Power Supply Current
Power Supply Current
Power Supply Current
250
30
mA
mA
mA
Max
Max
Max
All Outputs HIGH
All Outputs LOW
CCH
CCL
CCZ
CCT
50
Outputs TRI-STATE; All Others GND
e
b
2.1V
All Other Outputs at V or GND
Additional I /Input
CC
V
I
V
CC
2.5
mA
Max
CC
I
Dynamic I
(Note 2)
No Load
Outputs Open
CCD
CC
e
OE and DIR
e
GND,
GND or V (Note 1)
0.18 mA/MHz
Max
Non-I/O
CC
One Bit toggling, 50% duty cycle
k
Note 1: For 8-bit toggling, I
1.4 mA/MHz.
CCD
Note 2: Guaranteed but not tested.
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4
DC Electrical Characteristics (SOIC package) (Continued)
Conditions
Symbol
Parameter
Min
Typ
Max
Units
V
CC
e
e
e
e
e
e
e
500X
C
50 pF, R
L
L
V
OLP
Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
0.6
0.8
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
T
25 C (Note 1)
§
OL
A
A
A
A
A
b
b
V
OLV
1.2
2.5
2.2
0.9
T
T
T
T
25 C (Note 1)
§
OL
V
OHV
Minimum High Level Dynamic Output Voltage
3.0
25 (Note 3)
§
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
1.8
0.8
25 C (Note 2)
§
V
ILD
0.5
25 C (Note 2)
§
b
Note 1: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
b
Note 2: Max number of data inputs (n) switching. n
1 inputs switching 0V to 3V. Input-under-test switching: 3V to theshold (V ), 0V to threshold (V ).
ILD IHD
Guaranteed, but not tested.
b
Note 3: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics (SOIC and SSOP package)
74ABT
54ABT
74ABT
e a
e b
a
e b
T
A
e
V
CC
a
T
25 C
§
T
55 C to 125 C
§
40 C to 85 C
§
4.5V–5.5V
§
4.5V–5.5V
§
A
A
e a
5.0V
50 pF
e
Symbol
Parameter
V
V
Units
CC
CC
e
e
e
C 50 pF
L
C
C
L
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
f
Max Clock Frequency
200
200
200
MHz
ns
max
t
t
Propagation Delay
Clock to Bus
1.7
1.7
3.0
3.4
5.6
5.6
2.2
1.7
8.8
8.8
1.7
1.7
5.6
5.6
PLH
PHL
t
t
Propagation Delay
Bus to Bus
1.5
1.5
2.6
3.0
4.8
4.8
1.5
1.5
7.9
7.9
1.5
1.5
4.8
4.8
PLH
ns
ns
ns
ns
ns
ns
PHL
t
t
Propagation Delay
1.5
1.5
3.0
3.4
5.9
5.9
1.5
1.5
8.1
8.9
1.5
1.5
5.9
5.9
PLH
SBA or SAB to A to B
n
PHL
n
t
t
Enable Time
1.5
1.5
3.2
3.5
6.3
6.3
1.0
1.9
7.3
8.8
1.5
1.5
6.3
6.3
PZH
OE to A or B
n
PZL
n
n
t
t
Disable Time
1.5
1.5
3.7
3.2
6.0
6.0
1.5
1.5
9.3
9.3
1.5
1.5
6.0
6.0
PHZ
OE to A or B
n
PLZ
t
t
Enable Time
1.5
1.5
3.4
3.7
6.3
6.3
1.0
2.2
7.7
9.5
1.5
1.5
6.3
6.3
PZH
DIR to A or B
n
PZL
n
n
t
t
Disable Time
1.5
1.5
3.8
3.2
6.0
6.0
1.5
1.5
8.7
9.2
1.5
1.5
6.0
6.0
PHZ
DIR to A or B
n
PLZ
AC Operating Requirements
74ABT
54ABT
74ABT
e a
e a
e b
a
e b
T
A
e
V
CC
a
T
25 C
T
A
55 C to 125 C
§
40 C to 85 C
§
5.0V
§
4.5V–5.5V
§
4.5V–5.5V
§
A
e
Symbol
Parameter
V
V
CC
Units
CC
e
e
e
C
L
C
50 pF
C
L
50 pF
50 pF
L
Min
Max
Min
Max
Min
Max
t (H)
S
Setup Time, HIGH
1.5
1.5
3.0
1.0
4.0
1.5
1.0
3.0
ns
ns
ns
t (L)
S
or LOW Bus to Clock
t
t
(H)
(L)
Hold Time, HIGH
H
1.0
3.0
1.0
3.0
or LOW Bus to Clock
H
t
t
(H)
(L)
Pulse Width,
W
HIGH or LOW
W
5
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Extended AC Electrical Characteristics (SOIC package)
74ABT
74ABT
74ABT
e b
a
e b
a
e b
T
A
a
T
A
40 C to 85 C
§
T
40 C to 85 C
§
40 C to 85 C
§
§
4.5V–5.5V
§
4.5V–5.5V
§
4.5V–5.5V
A
e
e
e
V
V
CC
C
V
CC
C
CC
e
e
e
250 pF
L
Symbol
Parameter
C
L
50 pF
250 pF
Units
L
8 Outputs Switching
(Note 4)
1 Output Switching
(Note 5)
8 Outputs Switching
(Note 6)
Min
Max
Min
Max
Min
Max
t
t
Progagation Delay
Clock to Bus
1.5
1.5
5.5
5.5
2.0
2.0
7.5
7.5
2.5
2.5
10.0
10.0
PLH
ns
ns
PHL
t
t
Progagation Delay
Bus to Bus
1.5
1.5
6.0
6.0
2.0
2.0
7.0
7.0
2.5
2.5
9.5
9.5
PLH
PHL
t
t
Progagation Delay
SBA or SAB to
PLH
1.5
1.5
6.0
6.0
2.0
2.0
7.5
7.5
2.5
2.5
10.0
10.0
ns
PHL
A
or B
n
n
t
t
Output Enable Time
OE or DIR to A or B
1.5
1.5
6.0
6.0
2.0
2.0
8.0
8.0
2.5
2.5
10.5
10.5
PZH
ns
ns
PZL
n
n
n
t
t
Output Disable Time
OE or DIR to A or B
1.5
1.5
6.0
6.0
PHZ
(Note 7)
(Note 7)
PLZ
n
n
n
Note 4: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all low-to-high, high-
to-low, etc.).
Note 5: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load. This specification pertains to single output switching only.
Note 6: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all low-to-high, high-
to-low, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 7: The TRI-STATE delays are dominated by the RC network (500X, 250 pF) on the output and has been excluded from the datasheet.
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6
Skew (SOIC package)
74ABT
74ABT
e b
a
e b
A
a
T
A
40 C to 85 C
§
T
40 C to 85 C
§
§
4.5V–5.5V
§
4.5V–5.5V
e
e
V
V
CC
C
CC
e
e
250 pF
Symbol
Parameter
C
50 pF
Units
L
L
8 Outputs Switching
(Note 3)
8 Outputs Switching
(Note 4)
Max
Max
t
Pin to Pin Skew
HL Transitions
OSHL
(Note 1)
1.3
2.5
ns
ns
t
Pin to Pin Skew
LH Transitions
OSLH
(Note 1)
1.0
2.0
2.0
2.5
2.0
4.0
4.0
4.5
t
Duty Cycle
PS
(Note 5)
LH–HL Skew
t
Pin to Pin Skew
OST
(Note 1)
ns
ns
LH/HL Transitions
t
Device to Device Skew
LH/HL Transitions
PV
(Note 2)
Note 1: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH to LOW (t ), LOW to HIGH (t ), or any combination switching LOW to HIGH and/or HIGH to LOW
OSHL OSLH
(t
OST
). This specification is guaranteed but not tested.
Note 2: Propagation delay variation for a given set of conditions (i.e., temperature and V ) from device to device. This specification is guaranteed but not tested.
CC
Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,
HIGH-to-LOW, etc.).
Note 4: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load.
Note 5: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the
outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Conditions
e
Symbol
Parameter
Typ
Units
T
25 C
§
A
e
e
C
C
Input Capacitance
Output Capacitance
5
11
pF
pF
V
V
0V (non I/O pins)
5.0V (A , B )
IN
CC
(Note 1)
I/O
CC
n
n
e
Note 1: C
is measured at frequency, f
1 MHz, per MIL-STD-883B, Method 3012.
I/O
7
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t
vs Temperature (T
)
t
vs Temperature (T )
PHL A
e
L
PLH
A
50 pF, 1 Output Switching
e
C
Clock to Bus
C
Clock to Bus
50 pF, 1 Output Switching
L
TL/F/10978–18
TL/F/10978–19
t
vs Load Capacitance
e
t
vs Load Capacitance
PHL
PLH
e
1 Output Switching, T
Clock to Bus
25 C
§
1 Output Switching, T
Clock to Bus
25 C
§
A
A
TL/F/10978–20
TL/F/10978–21
t
vs Load Capacitance
t
vs Load Capacitance
PHL
PLH
e
e
8 Outputs Switching, T
Clock to Bus
25 C
§
8 Outputs Switching, T
Clock to Bus
25 C
§
A
A
TL/F/10978–22
TL/F/10978–23
t
vs Temperature (T
)
t
vs Temperature (T )
PLZ A
PZL
A
50 pF, 1 Output Switching
e
C
OE to Bus
e
C
OE to Bus
50 pF, 1 Output Switching
L
L
TL/F/10978–24
TL/F/10978–25
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
8
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t
vs Temperature (T
PZH
e
)
t
vs Temperature (T )
PHZ A
A
50 pF, 1 Output Switching
e
C
OE to Bus
C
50 pF, 1 Output Switching
L
L
TL/F/10978–26
TL/F/10978–27
t
vs Temperature (T
)
t
vs Temperature (T )
PHZ A
e
50 pF, 8 Outputs Switching
PZH
A
50 pF, 8 Outputs Switching
e
C
OE to Bus
C
L
L
OE to Bus
TL/F/10978–28
TL/F/10978–29
t
vs Temperature (T
)
t
vs Temperature (T )
PZL
A
50 pF, 8 Outputs Switching
PLZ A
e
C
OE to Bus
e
C
L
OE to Bus
50 pF, 8 Outputs Switching
L
TL/F/10978–30
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
TL/F/10978–31
9
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t
vs Load Capacitance
t
vs Load Capacitance
PZL
PZH
e
e
25 C
8 Outputs Switching, T
OE to Bus
25 C
§
8 Outputs Switching, T
OE to Bus
§
A
A
TL/F/10978–32
TL/F/10978–33
t
and t
e
e
vs Number Output Switching
e
25 C
PLH
PHL
5.0V, T
V
§
50 pF, Clock to Bus
CC
A
C
L
TL/F/10978–34
I
vs Frequency, Average,
CC
e
e
All Outputs Unloaded/Unterminated;
T
25 C, V
5.5V
§
A
CC
@
All Outputs Switching in phase 50% Duty Cycle
TL/F/10978–35
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
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10
t
LOW vs Temperature (T
)
t
HIGH vs Temperature (T )
SET A
SET
A
50 pF, 1 Output Switching
e
C
Bus to Clock
e
C
Bus to Clock
50 pF, 1 Output Switching
L
L
TL/F/10978–36
TL/F/10978–37
t
LOW vs Temperature (T
)
t
HIGH vs Temperature (T )
HOLD A
HOLD
A
50 pF, 1 Output Switching
e
C
Bus to Clock
e
C
Bus to Clock
50 pF, 1 Output Switching
L
L
TL/F/10978–38
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
TL/F/10978–39
11
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AC Loading
TL/F/10978–10
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
TL/F/10978–11
FIGURE 4. Propagation Delay,
Pulse Width Waveforms
TL/F/10978–12
FIGURE 2a. Test Input Signal Levels
Input Pulse Requirements
TL/F/10978–13
FIGURE 5. TRI-STATE Output HIGH
and LOW Enable and Disable Times
Amplitude
Rep. Rate
t
W
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 2b. Test Input Signal Requirements
TL/F/10978–15
TL/F/10978–14
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
FIGURE 3. Propagation Delay Waveforms for Inverting
and Non-Inverting Functions
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12
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
TL/F/10978–41
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Ceramic Leadless Chip Carrier (L)
Order Number 74ABT646CLC
NS Package Number E28A
13
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Ceramic Dual-in-Line Package (D)
Order Number 54ABT646J/883
NS Package Number J24A
24-Lead Small Outline Integrated Circuit (S)
Order Number 74ABT646CSC
NS Package Number M24B
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14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic EIAJ SSOP, Type II (MSA)
Order Number 74ABT646CMSA
NS Package Number MSA24
All dimensios ai.
24-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number 74ABT646CMTC
NS Package Number MTC24
15
http://www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Ceramic Flatpak Package (F)
Order Number 74ABT646CFM
NS Package Number W24C
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax: 49 (0) 180-530 85 86
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
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Tel: (852) 2737-1600
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Tel: 81-043-299-2308
Fax: 81-043-299-2408
@
Email: europe.support nsc.com
a
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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