74AC11138DR [TI]
3 线至 8 线解码器/多路解复用器 | D | 16 | -40 to 85;
| 型号： | 74AC11138DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3 线至 8 线解码器/多路解复用器 | D | 16 | -40 to 85 驱动 复用器 解复用器 解码器 驱动器 |
| 文件： | 总8页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B – MAY 1988 – REVISED APRIL 1996
D, N, OR PW PACKAGE
(TOP VIEW)
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
Y0
A
B
Y1
Y2
Y3
GND
Y4
Y5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
CC
C
V
CC
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
G1
G2A
G2B
Y6
Y7
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
description
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. In high-performance memory systems, this decoder
can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing
a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than
the typical access time of the memory. This means that the effective system delay introduced by the decoder
is negligible.
The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of
eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line
decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The 74AC11138 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
G2A
H
X
X
L
G2B
C
X
X
X
L
B
X
X
X
L
A
X
X
X
L
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y3
H
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
X
X
L
X
H
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B – MAY 1988 – REVISED APRIL 1996
†
logic symbols (alternatives)
BIN/OCT
DMUX
16
1
16
1
15
14
13
15
14
13
0
1
2
3
4
5
6
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
0
1
2
3
4
5
6
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A
B
C
1
2
4
A
B
C
0
2
0
G
7
2
2
3
3
&
&
11
10
5
11
10
5
G1
G2A
G2B
G1
G2A
G2B
6
6
EN
9
9
7
7
8
8
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
16
Y0
15
A
1
2
Y1
Y2
Y3
Y4
14
13
Select
Inputs
B
C
3
5
Data
Outputs
6
7
8
Y5
Y6
Y7
10
9
G2A
G2B
Enable
Inputs
11
G1
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B – MAY 1988 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . . 1.3 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
A
N package . . . . . . . . . . . . . . . . . . . . 1.1 W
PW package . . . . . . . . . . . . . . . . . . . 0.5 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
V
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
–4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B – MAY 1988 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
2.9
4.4
I
I
= –50 µA
4.5 V
5.5 V
3 V
4.4
OH
5.4
5.4
V
OH
= –4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= –24 mA
= –75 mA
OH
4.8
†
3.85
OH
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
V
OL
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
±1
V
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
†
= 75 mA
I
I
V = V
or GND
or GND,
or GND
±0.1
µA
µA
pF
I
I
CC
CC
CC
V = V
I = 0
O
4
40
CC
I
C
V = V
3.5
i
I
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
8.3
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
MAX
10.2
10.9
9.2
t
t
t
t
t
t
1.5
1.5
1.5
1.5
1.5
1.5
11.4
12.2
10.2
10.5
11.5
11.6
PLH
PHL
PLH
PHL
PLH
PHL
A, B, C
G1
Any Y
Any Y
Any Y
8.9
7.2
ns
7.3
9.4
8.2
10.4
10.4
ns
G2A, G2B
8.3
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
5.7
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
MAX
7.3
7.9
6.9
6.9
7.6
7.5
t
t
t
t
t
t
1.5
1.5
1.5
1.5
1.5
1.5
8.1
8.8
7.5
7.7
8.3
8.3
PLH
PHL
PLH
PHL
PLH
PHL
A, B, C
G1
Any Y
Any Y
Any Y
6.2
5.1
ns
5.2
5.8
ns
G2A, G2B
5.6
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B – MAY 1988 – REVISED APRIL 1996
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
C
Power dissipation capacitance per gate
C
51
pF
pd
PARAMETER MEASUREMENT INFORMATION
V
CC
0 V
PLH
Input
(see Note B)
From Output
Under Test
50% V
50% V
CC
CC
t
t
PHL
C
= 50 pF
L
500 Ω
(see Note A)
V
OH
50% V
CC
50% V
CC
Output
V
OL
VOLTAGE WAVEFORMS
LOAD CIRCUIT
NOTES: A.
C includes probe and jig capacitance.
L
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B – MAY 1988 – REVISED APRIL 1996
APPLICATION INFORMATION
74AC11138
BIN/OCT
16
1
15
14
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
2
13
3
4
11
10
9
5
&
V
CC
6
EN
7
8
74AC11138
BIN/OCT
16
1
15
14
0
1
2
3
4
5
6
7
8
A0
A1
A2
1
2
9
2
10
11
12
13
14
15
13
3
4
11
10
9
5
&
A3
A4
6
EN
7
8
74AC11138
BIN/OCT
16
1
15
14
0
1
2
3
4
5
6
7
16
17
18
19
20
21
22
23
1
2
2
13
3
4
11
10
9
5
&
6
EN
7
8
Figure 2. 24-Bit Decoding Scheme
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B – MAY 1988 – REVISED APRIL 1996
APPLICATION INFORMATION
74AC11138
BIN/OCT
16
1
15
14
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
A0
A1
A2
1
2
2
13
3
4
11
10
9
5
&
V
CC
6
A3
EN
7
A4
8
74AC11138
BIN/OCT
16
1
15
14
0
1
2
3
4
5
6
7
8
1
2
9
2
10
11
12
13
14
15
13
3
4
11
10
9
5
&
6
EN
7
8
74AC11138
BIN/OCT
16
1
15
14
0
1
2
3
4
5
6
7
16
17
18
19
20
21
22
23
1
2
2
13
3
4
11
10
9
5
&
6
EN
7
8
74AC11138
BIN/OCT
16
1
15
14
0
1
2
3
4
5
6
7
24
25
26
27
28
29
30
31
1
2
2
13
3
4
11
10
9
5
&
6
EN
7
8
Figure 3. 32-Bit Decoding Scheme
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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