74AC11160_10 [TI]
SYNCHRONOUS 4-BIT DECADE COUNTER;
| 型号： | 74AC11160_10 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS 4-BIT DECADE COUNTER |
| 文件： | 总9页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 – D3199, AUGUST 1988 – REVISED APRIL 1993
DW OR N PACKAGE
(TOP VIEW)
• Internal Look-Ahead for Fast Counting
• Carry Output for n-Bit Cascading
• Fully Synchronous Operation for Counting
RCO
CLR
CLK
A
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
Q
• Flow-Through Architecture to Optimize PCB
A
Q
B
Layout
GND
GND
GND
GND
B
• Center-Pin V
and GND Pin Configurations
Minimize High-Speed Switching Noise
CC
V
CC
V
CC
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
C
D
Q
Q
C
D
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
12 ENP
11
LOAD
ENT
description
This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for
application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when so instructed by the count-enable
inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally
associated with asynchronous (ripple clock) counters; however, counting spikes may occur on the ripple carry
out output (RCO). A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock
input waveform.
This counter is fully programmable in that they may be preset to any number between 0 and 9. As presetting
is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree
with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function
for the 74AC11160 is synchronous and a low level at the clear input sets all four of the flip-flops outputs low,
regardless of the levels of the clock, load, or enable inputs.
If one of these decade counters is preset to a number between 10 and 15 or assumes such an invalid state when
power is applied, it will progress to the normal sequence within two counts as shown in the state diagram.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry
output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the
ripple carry output (RCO). RCO thus enabled will produce a high-level pulse while the count is 9 (HLLH). This
high-level overflow ripple carry pulse can be used to enable successive cascaded stages. Transitions at the
ENP or ENT are allowed regardless of the level of the clock input.
This counter features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that will
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting
the setup and hold times.
The 74AC11160 is characterized for operation from –40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 –D3199, AUGUST 1988 – REVISED APRIL 1993
state diagram
0
1
2
3
4
5
15
14
13
12
6
7
8
11
10
9
†
logic symbol
CTRDIV10
20
CLR
CT = 0
10
LOAD
M1
M2
G3
1
11
RCO
3CT = 9
ENT
ENP
CLK
12
19
G4
C5/2,3,4+
18
17
14
13
2
3
8
9
A
B
C
D
1,5D [1]
[2]
Q
A
Q
B
[4]
[8]
Q
C
Q
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 – D3199, AUGUST 1988 – REVISED APRIL 1993
†
logic diagram (positive logic)
10
LOAD
11
ENT
1
RCO
12
ENP
19
CLK
CK
R
20
LD
CLR
M1
G2
1, 2T/1C3
2
3
Q
A
G4
3D
4R
18
A
M1
G2
1, 2T/1C3
Q
B
C
D
G4
3D
4R
17
B
M1
G2
1, 2T/1C3
8
9
Q
G4
3D
4R
14
C
M1
G2
1, 2T/1C3
Q
G4
3D
4R
13
D
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 –D3199, AUGUST 1988 – REVISED APRIL 1993
output sequence
Illustrated below is the following sequence:
1. Clear outputs to zero (54AC11160 and 74AC11160 are synchronous)
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit.
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
B
Outputs
Q
C
Q
D
RCO
7
8
9
0
1
2
3
Inhibit
Count
Sync
Clear
Preset
Async
Clear
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 – D3199, AUGUST 1988 – REVISED APRIL 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
O
O
CC
CC
or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±125 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
†
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
V
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
–4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
NOTE 2: Unused or floating inputs must be held high or low.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 –D3199, AUGUST 1988 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
4.5 V
5.5 V
3 V
2.9
4.4
I
I
= – 50 µA
4.4
OH
5.4
5.4
V
OH
= – 4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= – 24 mA
= –75 mA
OL
4.8
†
3.85
OH
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
V
OL
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
±1
V
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
†
= 75 mA
I
I
V = V
or GND
or GND,
or GND
±0.1
µA
µA
pF
I
I
CC
CC
CC
V = V
I = 0
O
8
80
CC
I
C
V = V
3.5
i
I
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements, V
= 3.3 V ± 0.3 V (see Figure 1)
CC
T
= 25°C
A
MIN
MAX
UNIT
MHz
ns
MIN
0
MAX
f
t
Clock frequency
Pulse duration
66
0
7.5
6
66
clock
CLK low or high
7.5
6
w
CLR low
A, B, C, D
LOAD
6.5
6.5
6
6.5
6.5
6
t
t
Setup time before CLK↑
Hold time after CLK↑
ns
ns
su
ENT, ENP
CLR inactive
6
6
1
1
h
timing requirements, V
= 5 V ± 0.5 V (see Figure 1)
CC
T
= 25°C
A
MIN
MAX
UNIT
MHz
ns
MIN
0
MAX
f
t
Clock frequency
Pulse duration
110
0
4.5
4.5
3.5
6.5
4.5
6
110
clock
CLK low or high
CLR low
4.5
4.5
3.5
6.5
4.5
6
w
A, B, C, D
LOAD
ns
t
t
Setup time before CLK↑
Hold time after CLK↑
su
ENT, ENP
CLR inactive
ns
ns
1
1
h
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 – D3199, AUGUST 1988 – REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
66
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
66
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
11.2
12.2
9
13.6
15.1
11.2
13.4
10.8
12.8
7.6
15.2
17.2
12.5
15.1
12.1
14.4
8.3
CLK
RCO
Any Q
Any Q
RCO
ns
ns
ns
ns
CLK (LOAD high)
CLK (LOAD low)
ENT
10.6
8.6
10.1
6
6.8
12
8.9
9.9
Any Q
RCO
15.2
17.3
17.3
19.7
CLR
14.1
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
110
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
110
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
7.8
8.5
6.3
7.4
6
9.5
10.6
8
10.7
12.1
8.9
CLK
RCO
Any Q
Any Q
RCO
ns
ns
ns
ns
CLK (LOAD high)
CLK (LOAD low)
ENT
9.8
7.5
9.4
5.5
6.7
10.7
12.2
11.2
8.4
7.1
4.2
5
10.7
6
7.5
Any Q
RCO
8.2
9.9
12.1
13.8
CLR
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
48
UNIT
C
C
pF
pd
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 –D3199, AUGUST 1988 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
V
CC
Timing Input
(see Note B)
50%
From Output
Under Test
0 V
V
t
h
t
su
C
= 50 pF
CC
L
Data
Input
500 Ω
50%
50%
(see Note A)
0 V
SETUP AND HOLD TIMES
LOAD CIRCUIT
V
CC
Input
(see Note B)
50%
50%
0 V
V
CC
t
PHL
High-Level
Input
50%
50%
t
t
PLH
PHL
0 V
V
OH
CC
OL
In-Phase
Output
50% V
50% V
50% V
CC
CC
t
w
V
V
CC
t
Low-Level
Input
PLH
50%
50%
0 V
V
OH
Out-of-Phase
Output
50% V
CC
V
OL
PULSE DURATION
PROPAGATION DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Inputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics: PRR ≤ 10 MHz, Z = 50 Ω, t =3ns, t =3ns. Fortesting
O
r
f
f
and pulse duration: t = 1 to 3 ns, t = 1 to 3 ns.
r f
max
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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