74AC11191DWR [TI]

AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO20, PLASTIC, SO-20;
74AC11191DWR
型号: 74AC11191DWR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO20, PLASTIC, SO-20

光电二极管 逻辑集成电路 触发器
文件: 总10页 (文件大小:139K)
中文:  中文翻译
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ꢀꢁ ꢂꢃ ꢄꢄꢄꢅ ꢄ  
ꢆꢇ ꢈꢃꢉꢊꢋ ꢈꢋ ꢌꢆ ꢍꢁ ꢎꢏꢐꢑ ꢍ ꢌꢒꢓꢔ ꢋꢕ ꢈꢍꢏꢐ ꢈꢂꢊꢇꢍꢃꢋ ꢌ ꢈꢑ ꢖꢊ  
SCAS105A − FEBRUARY 1990 − REVISED APRIL 1993  
DW OR N PACKAGE  
(TOP VIEW)  
Single Down/Up Count Control Line  
Look-Ahead Circuitry Enhances Speed of  
Cascaded Counters  
RCO  
D/U  
CLK  
A
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Q
A
Fully Synchronous in Count Modes  
Q
B
Asynchronously Presettable with Load  
GND  
GND  
GND  
GND  
B
V
Control  
CC  
V
CC  
Flow-Through Architecture to Optimize  
C
D
CTEN  
LOAD  
PCB Layout  
Q
Q
C
D
Center-Pin V  
and GND Configurations to  
Minimize High-Speed Switching Noise  
CC  
MAX/MIN  
EPICt (Enhanced-Performance Implanted  
CMOS) 1-mm Process  
500-mA Typical Latch-Up Immunity at  
125°C  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
description  
The 74AC11191 is a synchronous, 4-bit binary reversible up/down counter. Synchronous counting operation  
is provided by clocking all flip-flops simultaneously so that the outputs change coincident with each other when  
instructed by the steering logic. This mode of operation eliminates the output counting spikes normally  
associated with asynchronous (ripple clock) counters.  
The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the enable  
input (CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of  
the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down.  
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that  
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function  
of the counter will be dictated solely by the condition meeting the stable setup and hold times.  
These counters are fully programmable; that is, the outputs may be preset to any number between 0 and 15  
by placing a low on the load input and entering the desired data at the data inputs. The outputs will change to  
agree with the data inputs independently of the level of the clock input. This feature allows the counter to be  
used as a modulo-N divider by simply modifying the count length with the preset inputs.  
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum  
count. The latter output produces a high-level output pulse with a duration approximately equal to one complete  
cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. The  
ripple-clock output (RCO) produces a low-level output pulse under those same conditions but only while the  
clock input is low. The counter can easily be cascaded by feeding the ripple clock output to the enable input  
of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The  
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.  
The 74AC11191 is characterized for operation from − 40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢑꢣ  
Copyright 1993, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢡꢣ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  
ꢀ ꢁꢂ ꢃ ꢄꢄꢄ ꢅꢄ  
ꢆꢇ ꢈꢃ ꢉ ꢊ ꢋꢈ ꢋꢌ ꢆꢍ ꢁ ꢎꢏꢐ ꢑ ꢍꢌꢒ ꢓ ꢔꢋꢕꢈ ꢍ ꢏꢐꢈꢂ ꢊꢇꢍꢃ ꢋꢌ ꢈꢑꢖ ꢊ  
SCAS105A − FEBRUARY 1990 − REVISED APRIL 1993  
logic symbol  
CTRDIV16  
12  
G1  
CTEN  
20  
10  
1
M2 [DOWN]  
M3 [UP]  
1,2−/1,3+  
G4  
2(CT=0)Z6  
3(CT=15)Z6  
D/U  
MAX/MIN  
RCO  
19  
CLK  
6,1,4  
11  
LOAD  
C5  
2
3
8
9
18  
A
5D  
[1]  
[2]  
[4]  
[8]  
Q
Q
Q
Q
A
B
C
D
17  
B
14  
C
13  
D
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  
ꢀ ꢁꢂ ꢃ ꢄꢄꢄꢅ ꢄ  
ꢆꢇ ꢈꢃꢉꢊꢋ ꢈꢋ ꢌꢆ ꢍꢁ ꢎꢏꢐꢑ ꢍ ꢌꢒꢓꢔ ꢋꢕ ꢈꢍꢏꢐ ꢈꢂꢊꢇꢍꢃꢋ ꢌ ꢈꢑ ꢖꢊ  
SCAS105A − FEBRUARY 1990 − REVISED APRIL 1993  
logic diagram (positive logic)  
10  
MAX/MIN  
12  
CTEN  
1
RCO  
20  
D/U  
19  
CLK  
11  
LOAD  
18  
A
2
S
C1  
1D  
Q
A
R
17  
B
3
S
C1  
Q
B
1D  
R
14  
C
8
S
C1  
Q
C
1D  
R
13  
D
9
S
C1  
QD  
1D  
R
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  
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SCAS105A − FEBRUARY 1990 − REVISED APRIL 1993  
typical load, count, and inhibit sequences  
Illustrated below is the following sequence:  
1. Load (preset) to binary thirteen  
2. Count up to fourteen, fifteen (maximum), zero, one, and two  
3. Inhibit  
4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen.  
LOAD  
A
B
C
D
Data  
Inputs  
CLOCK  
D/U  
CTEN  
Q
Q
Q
Q
A
B
C
D
MAX/MIN  
RCO  
13  
14  
15  
0
1
2
2
2
1
0
15  
14  
13  
Count Up  
Inhibit  
Count Down  
Load  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  
ꢀ ꢁꢂ ꢃ ꢄꢄꢄꢅ ꢄ  
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SCAS105A − FEBRUARY 1990 − REVISED APRIL 1993  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
+ 0.5 V  
I
CC  
CC  
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
IK  
I
I
CC  
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Continuous current through V  
O
O
CC  
CC  
or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
V
Supply voltage  
3
2.1  
5
5.5  
V
CC  
IH  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 3 V  
= 4.5 V  
= 5.5 V  
= 3 V  
3.15  
3.85  
V
High-level input voltage  
V
V
0.9  
1.35  
1.65  
= 4.5 V  
= 5.5V  
V
IL  
Low-level input voltage  
V
V
Input voltage  
0
0
V
V
V
I
CC  
Output voltage  
V
CC  
−4  
O
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 3 V  
= 4.5 V  
= 5.5 V  
= 3 V  
24  
24  
12  
I
High-level output current  
Low-level output current  
mA  
mA  
OH  
= 4.5 V  
= 5.5 V  
24  
I
OL  
24  
Dt/Dv Input transition rise or fall rate  
Operating free-air temperature  
0
10  
ns/V  
T
A
− 40  
85  
°C  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  
ꢀ ꢁꢂ ꢃ ꢄꢄꢄ ꢅꢄ  
ꢆꢇ ꢈꢃ ꢉ ꢊ ꢋꢈ ꢋꢌ ꢆꢍ ꢁ ꢎꢏꢐ ꢑ ꢍꢌꢒ ꢓ ꢔꢋꢕꢈ ꢍ ꢏꢐꢈꢂ ꢊꢇꢍꢃ ꢋꢌ ꢈꢑꢖ ꢊ  
SCAS105A − FEBRUARY 1990 − REVISED APRIL 1993  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
PARAMETER  
TEST CONDITIONS  
V
MIN  
MAX  
UNIT  
CC  
MIN  
2.9  
TYP  
MAX  
3 V  
4.5 V  
5.5 V  
3 V  
2.9  
4.4  
4.4  
I
I
= − 50 mA  
OH  
5.4  
5.4  
= − 4 mA  
2.58  
3.94  
4.94  
2.48  
3.8  
V
OH  
V
OH  
4.5 V  
5.5 V  
5.5 V  
3 V  
I
I
= − 24 mA  
= − 75 mA  
OH  
4.8  
{
3.85  
OH  
0.1  
0.1  
0.1  
0.1  
4.5 V  
5.5 V  
3 V  
I
I
= 50 mA  
OL  
0.1  
0.1  
= 12 mA  
= 24 mA  
0.36  
0.36  
0.36  
0.44  
0.44  
0.44  
1.65  
1
V
OL  
V
OL  
4.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
5 V  
I
I
OL  
{
= 75 mA  
OL  
I
I
V = V  
or GND  
or GND,  
or GND  
0.1  
8
mA  
mA  
pF  
I
I
CC  
CC  
CC  
V = V  
I = 0  
O
80  
CC  
I
C
V = V  
4
i
I
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.  
timing requirements over recommended operating free-air temperature range,  
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)  
CC  
T
= 25°C  
A
MIN  
MAX  
UNIT  
MIN  
0
MAX  
f
t
Clock frequency  
50  
0
4.8  
10  
4
50  
MHz  
clock  
LOAD low  
4.8  
10  
4
Pulse duration  
ns  
w
CLK high or low  
Data before LOAD↑  
CTEN before CLK↑  
12.5  
13.5  
2.5  
1
12.5  
13.5  
2.5  
1
t
Setup time  
ns  
su  
h
D/U before CLK↑  
LOAD inactive before CLK↑  
Data after LOAD↑  
t
Hold time  
CTEN after CLK↑  
D/U after CLK↑  
0
0
ns  
0
0
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  
ꢀ ꢁꢂ ꢃ ꢄꢄꢄꢅ ꢄ  
ꢆꢇ ꢈꢃꢉꢊꢋ ꢈꢋ ꢌꢆ ꢍꢁ ꢎꢏꢐꢑ ꢍ ꢌꢒꢓꢔ ꢋꢕ ꢈꢍꢏꢐ ꢈꢂꢊꢇꢍꢃꢋ ꢌ ꢈꢑ ꢖꢊ  
SCAS105A − FEBRUARY 1990 − REVISED APRIL 1993  
timing requirements over recommended operating free-air temperature range,  
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)  
CC  
T
= 25°C  
A
MIN  
MAX  
UNIT  
MIN  
0
MAX  
f
t
Clock frequency  
100  
0
4
100  
MHz  
clock  
LOAD low  
4
Pulse duration  
ns  
w
CLK high or low  
7.2  
3
7.2  
3
Data before LOAD↑  
CTEN before CLK↑  
8
8
t
t
Setup time  
ns  
su  
D/U before CLK↑  
8.5  
2
8.5  
2
LOAD inactive before CLK↑  
Data after LOAD↑  
CTEN after CLK↑  
D/U after CLK↑  
1.5  
0.5  
0
1.5  
0.5  
0
Hold time  
ns  
h
switching characteristics over recommended operating free-air temperature range,  
= 3 V 0.3 V (unless otherwise noted) (see Figure 1)  
V
CC  
T
A
= 25°C  
TYP  
80  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
MIN  
MAX  
UNIT  
MIN  
50  
MAX  
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
50  
3.7  
3.6  
5
MHz  
max  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
3.7  
3.6  
5
10.7  
9.3  
13.4  
12.3  
18.7  
17.5  
20.2  
21.6  
12.3  
12.1  
18.2  
17.1  
19.9  
21.1  
11.5  
10.6  
9.8  
14.9  
14.1  
21.1  
19.6  
22.9  
24.7  
13.8  
13.7  
20.7  
19.3  
22.5  
24.3  
12.9  
11.9  
11.1  
12.7  
13.8  
16  
LOAD  
LOAD  
Any Q  
MAX/MIN  
RCO  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
14.2  
12.6  
15.4  
15.7  
9.8  
4.6  
5.2  
6
4.6  
5.2  
6
LOAD  
3.4  
3.5  
4.7  
4
3.4  
3.5  
4.7  
4
A, B, C, or D  
A, B, C, or D  
A, B, C, or D  
CLK  
Any Q  
8.9  
13.5  
11.8  
14.7  
15.1  
8.7  
MAX/MIN  
RCO  
5
5
5.3  
2.8  
2.8  
2.2  
2.7  
3.7  
4.1  
4.1  
4.1  
2.7  
3.1  
2.5  
2.6  
5.3  
2.8  
2.8  
2.2  
2.7  
3.7  
4.1  
4.1  
4.1  
2.7  
3.1  
2.5  
2.6  
RCO  
7.8  
7.5  
CLK  
Any Q  
7.5  
11  
9.9  
12.2  
14.4  
14.4  
14.3  
11.5  
11.8  
9
CLK  
MAX/MIN  
RCO  
10.2  
11.2  
10.2  
8.7  
15.9  
16.5  
12.7  
13.6  
10.3  
10  
D/U  
D/U  
MAX/MIN  
RCO  
8.3  
7.2  
CTEN  
6.6  
8.8  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  
ꢀ ꢁꢂ ꢃ ꢄꢄꢄ ꢅꢄ  
ꢆꢇ ꢈꢃ ꢉ ꢊ ꢋꢈ ꢋꢌ ꢆꢍ ꢁ ꢎꢏꢐ ꢑ ꢍꢌꢒ ꢓ ꢔꢋꢕꢈ ꢍ ꢏꢐꢈꢂ ꢊꢇꢍꢃ ꢋꢌ ꢈꢑꢖ ꢊ  
SCAS105A − FEBRUARY 1990 − REVISED APRIL 1993  
switching characteristics over recommended operating free-air temperature range,  
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)  
V
CC  
T
A
= 25°C  
TYP  
135  
6.7  
6.4  
8.8  
8.4  
9.7  
10.1  
6.2  
6.1  
8.4  
8
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
MIN  
MAX  
UNIT  
MIN  
100  
3.1  
3
MAX  
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
100  
3.1  
3
MHz  
ns  
max  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
9.4  
9
10.6  
10.2  
14.3  
13.7  
15.4  
16.3  
9.8  
LOAD  
LOAD  
Any Q  
MAX/MIN  
RCO  
4.3  
4
12.5  
12  
4.3  
4
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4.5  
5
13.7  
14.4  
8.7  
8.7  
12.2  
11.8  
13.5  
14  
4.5  
5
LOAD  
2.9  
3
2.9  
3
A, B, C, or D  
A, B, C, or D  
A, B, C, or D  
CLK  
Any Q  
9.8  
4.1  
3.5  
4.3  
4.7  
2.4  
2.9  
1.9  
2.4  
3
4.1  
3.5  
4.3  
4.7  
2.4  
2.9  
1.9  
2.4  
3
13.7  
13.4  
15.1  
16  
MAX/MIN  
RCO  
9.2  
9.7  
5.9  
5.6  
5.2  
5.4  
6.5  
7.1  
7.2  
6.9  
5.7  
5.9  
4.9  
4.8  
8.4  
7.7  
7.6  
8
9.1  
RCO  
8.7  
8.4  
CLK  
Any Q  
9.4  
8.8  
10.4  
10.2  
10  
10.4  
10.8  
11.3  
11.5  
9.1  
CLK  
MAX/MIN  
RCO  
3.6  
3.5  
3.5  
2.3  
2.7  
2.1  
2.2  
3.6  
3.5  
3.5  
2.3  
2.7  
2.1  
2.2  
D/U  
8.1  
8.6  
6.8  
6.7  
D/U  
MAX/MIN  
RCO  
9.7  
7.7  
CTEN  
7.7  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
= 50 pF, f = 1 MHz  
L
TYP  
66  
UNIT  
C
Power dissipation capacitance  
C
pF  
pd  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  
ꢀ ꢁꢂ ꢃ ꢄꢄꢄꢅ ꢄ  
ꢆꢇ ꢈꢃꢉꢊꢋ ꢈꢋ ꢌꢆ ꢍꢁ ꢎꢏꢐꢑ ꢍ ꢌꢒꢓꢔ ꢋꢕ ꢈꢍꢏꢐ ꢈꢂꢊꢇꢍꢃꢋ ꢌ ꢈꢑ ꢖꢊ  
SCAS105A − FEBRUARY 1990 − REVISED APRIL 1993  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
Timing Input  
(see Note B)  
50%  
From Output  
Under Test  
0 V  
V
t
h
t
su  
C
= 50 pF  
CC  
L
Data  
Input  
500 Ω  
50%  
50%  
(see Note A)  
0 V  
SETUP AND HOLD TIMES  
LOAD CIRCUIT  
V
CC  
Input  
(see Note B)  
50%  
50%  
0 V  
V
CC  
t
PHL  
High-Level  
Input  
50%  
50%  
t
t
PLH  
PHL  
0 V  
V
OH  
CC  
OL  
In-Phase  
Output  
50% V  
50% V  
50% V  
CC  
t
w
V
V
CC  
t
Low-Level  
Input  
PLH  
50%  
50%  
0 V  
V
OH  
Out-of-Phase  
Output  
50% V  
CC  
CC  
V
OL  
PULSE DURATION  
PROPAGATION DELAY TIMES  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. Input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
9
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POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  
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