74AC11374DBLE [TI]
Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs 24-SSOP -40 to 85;
| 型号： | 74AC11374DBLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs 24-SSOP -40 to 85 触发器 输出元件 |
| 文件： | 总7页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
DB, DW, OR NT PACKAGE
(TOP VIEW)
Eight D-Type Flip-Flops in a Single Package
3-State Bus-Driving True Outputs
Full Parallel Access for Loading
1Q
2Q
OE
1D
2D
3D
4D
V
1
24
23
22
21
20
19
18
17
16
15
14
13
2
Flow-Through Architecture Optimizes
PCB Layout
3Q
3
4Q
4
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
CC
GND
GND
GND
GND
5Q
5
6
CC
EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process
7
V
CC
5D
8
500-mA Typical Latch-Up Immunity at
125°C
9
6D
10
11
12
6Q
7D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
7Q
8D
8Q
CLK
description
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight flip-flops of the 74AC11374 are edge-triggered D-type flip-flops. On the positive transition of the clock,
the Q outputs are set to the logic levels set up at the D inputs.
The output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines signigicantly. The high-impedance third state provides the capability to drive the bus lines in a
bus-organized system without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74AC11374 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
L
H
↓
X
X
X
X
Q
Q
Q
0
0
0
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
†
logic symbol
24
OE
EN
C1
13
CLK
23
22
21
20
17
16
15
14
1
2
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
3
4
9
10
11
12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
24
13
OE
CLK
C1
1D
1
2
3
4
9
23
22
21
20
17
16
15
14
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
C1
1D
2D
3D
4D
5D
6D
7D
8D
C1
1D
C1
1D
C1
1D
C1
1D
10
C1
1D
11
12
C1
1D
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
A
DW package . . . . . . . . . . . . . . . . . . 1.7 W
NT package . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
V
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
–4
O
V
V
V
V
V
V
= 3 V
CC
CC
CC
CC
CC
CC
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
24
24
10
5
mA
mA
OH
I
= 4.5 V
= 5.5 V
OL
Data
OE
0
0
t/ v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
–40
85
°C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
2.9
4.4
I
= –50
A
4.5 V
5.5 V
3 V
4.4
OH
5.4
5.4
I
I
= –4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
V
OH
4.5 V
5.5 V
5.5 V
3 V
= –24 mA
OH
4.8
3.85
I
= –75 mA
OH
OL
0.1
0.1
0.1
0.1
I
= 50
A
4.5 V
5.5 V
3 V
0.1
0.1
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
±5
V
OL
V
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
OL
I
= 75 mA
OL
I
I
I
V
= V or GND
CC
±0.5
±0.1
8
A
A
OZ
O
V = V
or GND
or GND,
or GND
±1
I
I
CC
CC
CC
V = V
I = 0
O
80
A
CC
I
C
C
V = V
4
pF
pF
i
I
V
= V or GND
CC
5 V
10
o
O
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
t
t
Clock frequency
75
0
6.5
2.5
4.5
75
MHz
ns
clock
Pulse duration
CLK low or high
6.5
2.5
4.5
w
Setup time, data before CLK↑
Hold time, data after CLK↑
ns
su
h
ns
timing requirements over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
t
t
Clock frequency
95
0
5
95
MHz
ns
clock
Pulse duration
CLK low or high
5
w
Setup time, data before CLK↑
Hold time, data after CLK↑
2.5
3.5
2.5
3.5
ns
su
h
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
75
TYP
90
9.5
9
MAX
f
t
t
t
t
t
t
75
1.5
1.5
1.5
1.5
1.5
1.5
max
PLH
PHL
PZH
PZL
PHZ
PLZ
1.5
1.5
1.5
1.5
1.5
1.5
12.5
12.6
10.9
11.1
12.1
10.7
14.2
14
CLK
Any Q
Any Q
Any Q
8
12.3
12.3
12.5
11.6
ns
ns
OE
OE
8
10
8
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
110
6.5
5.5
5.5
5.5
9
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
95
MAX
f
t
t
t
t
t
t
95
1.5
1.5
1.5
1.5
1.5
1.5
max
PLH
PHL
PZH
PZL
PHZ
PLZ
1.5
1.5
1.5
1.5
1.5
1.5
9
9.1
8
10.2
10.1
9.1
CLK
OE
Any Q
Any Q
Any Q
ns
ns
8.4
11
9.4
11.2
9.2
OE
6
8.6
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF f =1 MHz
L
TYP
75
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per flip-flop
C
pF
pd
66
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
S1
500 Ω
From Output
Under Test
TEST
S1
t
t
/t
Open
PLH PHL
/t
C
= 50 pF
t
2 × V
CC
GND
L
500 Ω
PLZ PZL
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
V
CC
Timing Input
Data Input
50%
0 V
t
w
t
h
t
V
CC
su
V
CC
Input
50%
50%
50%
50%
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
Input
50%
50%
50%
50%
0 V
0 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
0 V
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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