74AC273LC [TI]
AC SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20;
| 型号： | 74AC273LC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AC SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20 输出元件 |
| 文件： | 总8页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1993
54AC/74AC273
Octal D Flip-Flop
General Description
Features
Y
Ideal buffer for microprocessor or memory
The ’273 has eight edge-triggered D-type flip-flops with indi-
vidual D inputs and Q outputs. The common buffered Clock
(CP) and Master Reset (MR) input load and reset (clear) all
flip-flops simultaneously.
Y
Eight edge-triggered D flip-flops
Y
Buffered common clock
Y
Buffered, asynchronous master reset
Y
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put.
See ’377 for clock enable version
Y
See ’373 for transparent latch version
Y
See ’374 for TRI-STATE version
Y
Outputs source/sink 24 mA
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
Y
’ACT has TTL-compatible inputs
Y
Standard Military Drawing (SMD)
Ð ’AC273: 5962-87756
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
TL/F/9954–1
TL/F/9954–2
TL/F/9954–3
Pin Assignment
for LCC
Pin Names
Description
D –D
0
Data Inputs
7
MR
CP
Master Reset
Clock Pulse Input
Data Outputs
Q –Q
0
7
FACTTM is a trademark of National Semiconductor Corporation.
TL/F/9954–4
C
1995 National Semiconductor Corporation
TL/F/9954
RRD-B30M75/Printed in U. S. A.
Mode Select-Function Table
Inputs
Outputs
Operating Mode
MR
L
CP
X
D
Q
n
n
e
e
e
Reset (Clear)
Load ‘1’
X
L
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
H
L
L
H
L
H
L
X
e
L
LOW-to-HIGH Transition
Load ‘0’
H
Logic Diagram
TL/F/9954–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Rating (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
’AC
)
CC
2.0V to 6.0V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
Input Voltage (V )
I
0V to V
0V to V
CC
DC Input Diode Current (I
)
IK
Output Voltage (V
)
O
CC
e b
b
a
V
I
V
I
0.5V
a
20 mA
20 mA
Operating Temperature (T )
A
e
V
CC
0.5V
b
b
a
40 C to 85 C
74AC
54AC
§
55 C to 125 C
§
§
b
a
0.5V
DC Input Voltage (V )
I
0.5V to V
CC
a
§
DC Output Diode Current (I
)
OK
Minimum Input Edge Rate (DV/Dt)
’AC Devices
e b
b
a
V
V
0.5V
a
20 mA
20 mA
O
O
e
V
CC
0.5V
V
V
from 30% to 70% of V
@
IN
CC
b
a
DC Output Voltage (V
DC Output Source
)
O
0.5V to to V
CC
0.5V
50 mA
50 mA
3.3V, 4.5V, 5.5V
125 mV/ns
CC
g
or Sink Current (I
)
O
DC V
or Ground Current
CC
g
per Output Pin (I or I
CC
)
GND
)
b
a
65 C to 150 C
Storage Temperature (T
§
§
STG
Junction Temperature (T )
J
CDIP
PDIP
175 C
§
140 C
§
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
74AC
54AC
74AC
e
e
T
A
V
T
CC
A
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
55 C to 125 C
b a
40 C to 85 C
(V)
§
§
§
§
Typ
Guaranteed Limits
e
0.1V
V
V
V
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.1
2.1
2.1
V
IH
OUT
b
2.25
2.75
3.15
3.85
3.15
3.85
3.15
3.85
V
V
V
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
0.9
0.9
0.9
V
OUT
0.1V
IL
b
2.25
2.75
1.35
1.65
1.35
1.65
1.35
1.65
or V
CC
0.1V
e b
OUT
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
I
50 mA
OH
e
*V
IN
V
IL
or V
IH
b
b
b
3.0
4.5
5.5
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
12 mA
V
V
I
24 mA
24 mA
OH
e
e
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V or V
IL IH
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
12 mA
V
I
24 mA
24 mA
OL
e
I
Maximum Input
Leakage Current
V
I
V , GND
CC
IN
g
g
g
1.0
5.5
0.1
1.0
mA
*All outputs loaded; thresholds on input associated with output under test.
²
Maximum test duration 2.0 ms, one output loaded at a time.
3
DC Characteristics for ’AC Family Devices (Continued)
74AC
54AC
74AC
e
e
T
A
V
T
CC
A
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
55 C to 125 C
b
a
40 C to 85 C
(V)
§
§
§
§
Typ
Guaranteed Limits
e
²
I
I
I
Minimum Dynamic
5.5
5.5
50
75
mA
mA
V
V
V
1.65V Max
OLD
OHD
CC
OLD
Output Current
b
b
e
3.85V Min
OHD
50
75
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
4.0
80.0
40.0
mA
or GND
*All outputs loaded; thresholds on input associated with output under test.
²
Maximum test duration 2.0 ms, one output loaded at a time.
@
@
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V
Note: I and I
IN
.
CC
CC
@ @
for 54AC 25 C is identical to 74AC 25 C.
§ §
I
CC
AC Electrical Characteristics
74AC
54AC
e b
74AC
e b
T
55 C
T
A
40 C
§
§
A
e a
A
V
CC
(V)
*
T
25 C
§
50 pF
a
a
Symbol
Parameter
to 125 C
to 85 C
Units
§
50 pF
§
50 pF
e
C
L
e
e
C
C
L
L
Min
Typ
Max
Min
Max
Min
Max
f
t
t
t
Maximum Clock
Frequency
3.3
5.0
90
125
175
75
90
75
max
PLH
PHL
PHL
MHz
ns
140
125
Propagation Delay
Clock to Output
3.3
5.0
4.0
3.0
7.0
5.5
12.5
9.0
1.0
1.0
15.0
11.0
3.0
2.5
14.0
10.0
Propagation Delay
Clock to Output
3.3
5.0
4.0
3.0
7.0
5.0
13.0
10.0
1.0
1.0
16.0
11.5
3.5
2.5
14.5
11.0
ns
Propagation Delay
MR to Output
3.3
5.0
4.0
3.0
7.0
5.0
13.0
10.0
1.0
1.0
16.0
11.5
3.5
2.5
14.0
10.5
ns
g
*Voltage Range 3.3 is 3.3V 0.3V
g
Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
74AC
54AC
74AC
e b
e b
40 C
T
55 C
T
A
§
to 125 C
§
to 85 C
A
e a
A
V *
CC
(V)
T
25 C
§
50 pF
a
a
Symbol
Parameter
Units
§
50 pF
§
e
C
L
e
e
50 pF
C
C
L
L
Typ
Guaranteed Minimum
t
t
t
t
t
Setup Time, HIGH or LOW
Data to CP
3.3
5.0
3.5
2.5
5.5
8.0
5.0
6.0
s
ns
ns
ns
ns
ns
4.0
4.5
b
b
Hold Time, HIGH or LOW
Data to CP
3.3
5.0
2.0
1.0
0
0
0
h
1.0
1.0
1.0
Clock Pulse Width
HIGH or LOW
3.3
5.0
3.5
5.5
4.0
6.5
5.0
6.0
4.5
w
w
rec
2.5
MR Pulse Width
HIGH or LOW
3.3
5.0
2.0
1.5
5.5
4.0
10.0
6.5
6.0
4.5
Recovery Time
MR to CP
3.3
5.0
1.5
1.0
3.5
2.0
6.0
4.0
4.5
3.0
g
*Voltage Range 3.3 is 3.3V 0.3V
g
Voltage Range 5.0 is 5.0V 0.5V
4
Capacitance
Symbol
Parameter
Typ
Units
Conditions
e
e
C
C
Input Capacitance
4.5
pF
V
V
Open
5.0V
IN
CC
Power Dissipation
Capacitance
PD
CC
50.0
pF
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74AC 273
P
C
X
Temperature Range Family
Special Variations
e
e
e
e
74AC
54AC
Commercial
Military
X
QB
Devices shipped in 13 reels
×
Military grade device with
environmental and burn-in
processing shipped in tubes
Device Type
Package Code
Temperature Range
e
e
e
e
e
P
D
F
L
Plastic DIP
Ceramic DIP
Flatpak
Leadless Ceramic Chip Carrier (LCC)
Small Outline (SOIC)
e
e
b a
C
M
Commercial ( 40 C to 85 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
S
5
Physical Dimensions inches (millimeters)
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
6
Physical Dimensions inches (millimeters) (Continued)
20 Lead Small Outline Integrated Circuit (S)
NS Package Number M20B
20 Lead Plastic Dual-In-Line Package (P)
NS Package Number N20B
7
Physical Dimensions inches (millimeters) (Continued)
20 Lead Ceramic Flatpak (F)
NS Package Number W20A
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