74ACT11191 [TI]
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER; 同步4位加/减二进制计数器
| 型号： | 74ACT11191 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER |
| 文件： | 总9页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993
DW OR N PACKAGE
(TOP VIEW)
• Inputs Are TTL-Voltage Compatible
• Single Down/Up Count Control Line
• Look-Ahead Circuitry Enhances Speed of
RCO
D/U
CLK
A
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Cascaded Counters
Q
A
• Fully Synchronous in Count Modes
Q
B
• Asynchronously Presettable With Load
GND
GND
GND
GND
B
V
V
Control
CC
CC
• Flow-Through Architecture Optimizes
C
PCB Layout
Q
Q
D
CTEN
LOAD
C
D
• Center-Pin V
and GND Configurations to
Minimize High-Speed Switching Noise
CC
MAX/MIN
• EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
The 74ACT11191 is a synchronous, 4-bit binary reversible up/down counter. A synchronous counting operation
is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other
when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally
associated with asynchronous (ripple clock) counters.
The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the enable
input (CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of
the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter will be dictated solely by the condition meeting the stable setup and hold times.
†
logic symbol
CTRDIV16
12
20
G1
CTEN
D/U
10
1
M2 [DOWN]
M3 [UP]
1,2−/1,3+
G4
2(CT=0)Z6
3(CT=15)Z6
MAX/MIN
RCO
19
11
CLK
6,1,4
LOAD
C5
2
3
8
9
18
17
14
13
A
B
5D
[1]
[2]
[4]
[8]
Q
Q
Q
Q
A
B
C
D
C
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
EPIC is a trademark of Texas Instruments Incorporated.
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Copyright 1993, Texas Instruments Incorporated
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2−1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅꢅ ꢆꢅ
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ꢗ
SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993
description (continued)
These counters are fully programmable; that is, they may be preset to any number between 0 and 15 by placing
a low on the load input and entering the desired data at the data inputs. The outputs will change to agree with
the data inputs independently of the level of the clock input. This feature allows the counter to be used as a
modulo-N divider by simply modifying the count length with the preset inputs.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum
count. The latter output produces a high-level output pulse with a duration approximately equal to one complete
cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. The
ripple clock output (ROC) produces a low-level output pulse under those same conditions but only while the
clock input is low. The counter can easily be cascaded by feeding the ripple clock output to the enable input
of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
The 74ACT11191 is characterized for operation from − 40°C to 85°C.
2−2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993
logic diagram (positive logic)
10
MAX/MIN
12
CTEN
1
RCO
20
D/U
19
CLK
11
LOAD
18
A
2
S
C1
1D
Q
A
R
17
B
3
S
C1
Q
B
1D
R
14
C
8
S
C1
Q
C
1D
R
13
D
9
S
C1
Q
D
1D
R
2−3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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ꢗ
SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1. Load (preset) to binary thirteen
2. Count up to fourteen, fifteen (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen.
LOAD
A
B
Data
Inputs
C
D
CLOCK
D/U
CTEN
Q
Q
Q
Q
A
B
C
D
MAX/MIN
RCO
13
14
15
0
1
2
2
2
1
0
15
14
13
Count Up
Inhibit
Count Down
Load
2−4
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
MAX
5.5
2
UNIT
V
V
V
V
V
V
Supply voltage
4.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
V
0
0
V
V
V
I
CC
Output voltage
V
O
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
24
mA
mA
ns/V
°C
OH
OL
Dt/Dv
0
10
T
− 40
85
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
4.4
TYP
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
4.4
5.4
I
= − 50 mA
OH
5.4
3.94
4.94
3.8
V
OH
V
OL
V
I
I
= − 24 mA
= − 75 mA
OH
4.8
}
3.85
OH
0.1
0.1
0.1
0.1
0.44
0.44
1.65
1
I
= 50 mA
OL
0.36
0.36
V
I
I
= 24 mA
OL
}
= 75 mA
OL
I
I
V = V
or GND
0.1
8
mA
mA
mA
pF
I
I
CC
V = V
or GND,
I = 0
O
80
CC
I
CC
w
DI
CC
One input at 3.4 V
V = V or GND
Other inputs at GND or V
0.9
1
CC
C
4
i
I
CC
‡
§
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
2−5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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ꢗ
SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
Clock frequency
Pulse duration
65
0
4
65
MHz
clock
LOAD low
4
ns
w
CLK high or low
7.7
3
7.7
3
Data before LOAD↓
CTEN before CLK↑
D/U before CLK↑
LOAD inactive before CLK↑
Data after LOAD↓
CTEN after CLK↑
D/U after CLK↑
7.5
8.5
2
7.5
8.5
2
t
Setup time
Hold time
ns
su
h
2.5
1.5
0.5
2.5
1.5
0.5
t
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
95
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
65
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
65
4
MHz
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
4
7.6
7.4
9.7
9.5
10.5
11
10.8
10.5
13.9
13.6
15.1
15.7
10.1
10.3
13.6
13.4
14.8
15.5
9.5
12.2
11.9
15.8
15.4
17.1
17.9
11.6
11.7
15.4
15.2
17.2
18
LOAD
LOAD
Any Q
MAX/MIN
RCO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.8
5.2
4.7
5.4
5.8
4.5
3.7
5.1
4.7
5.5
5.9
4.4
3.5
3.6
4.2
5
3.8
5.2
4.7
5.4
5.8
4.5
3.7
5.1
4.7
5.5
5.9
4.4
3.5
3.6
4.2
5
LOAD
7.6
7.1
9.5
9.2
10.3
10.9
7.4
6.7
6.7
7.1
8
A, B, C, or D
A, B, C, or D
A, B, C, or D
CLK
Any Q
MAX/MIN
RCO
11
RCO
9.5
10.8
10.4
10.8
11.7
13.1
13.1
13
9.2
CLK
Any Q
9.4
10.3
11.5
11.7
11.3
9.6
CLK
MAX/MIN
RCO
5.3
4.4
4.2
3.2
3.6
3.9
2.8
8.6
8.4
8.8
6.9
7.2
6.4
6
5.3
4.4
4.2
3.2
3.6
3.9
2.8
D/U
11
D/U
MAX/MIN
RCO
10.3
8.2
11.6
9.2
CTEN
8.4
9.5
2−6
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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ꢋ
SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
C
Power dissipation capacitance
C
68
pF
pd
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
t
w
3 V
C
= 50 pF
L
500 Ω
(see Note A)
Input
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
LOAD CIRCUIT
3 V
0 V
Input
(see Note B)
1.5 V
1.5 V
3 V
0 V
Timing Input
(see Note B)
t
t
PHL
PLH
1.5 V
V
OH
In-Phase
Output
50% V
CC
t
50% V
50% V
h
CC
t
V
OL
su
3 V
0 V
t
PLH
t
1.5 V
1.5 V
PHL
Data Input
V
OH
Out-of-Phase
Output
50% V
CC
CC
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2−7
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
2−8
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Products
Amplifiers
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Logic
Power Mgmt
Microcontrollers
RFID
Telephony
Video & Imaging
Wireless
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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