74ACT11373DBRE4 [TI]

ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24;
74ACT11373DBRE4
型号: 74ACT11373DBRE4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24

驱动 光电二极管 输出元件 逻辑集成电路
文件: 总20页 (文件大小:916K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
74ACT11373  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS015B – JUNE 1987 – REVISED APRIL 1996  
DB, DW, OR NT PACKAGE  
(TOP VIEW)  
Eight Latches in a Single Package  
3-State Bus Driving True Outputs  
Full Parallel Access for Loading  
Buffered Input and Output-Enable Pins  
Inputs Are TTL-Voltage Compatible  
1Q  
2Q  
OE  
1D  
2D  
3D  
4D  
V
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
3Q  
3
4Q  
4
Flow-Through Architecture Optimizes  
PCB Layout  
GND  
GND  
GND  
GND  
5Q  
5
6
CC  
Center-Pin V  
Minimize High-Speed Switching Noise  
and GND Configurations  
CC  
7
V
CC  
8
5D  
6D  
7D  
8D  
LE  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
9
10  
11  
12  
6Q  
500-mA Typical Latch-Up Immunity at  
125°C  
7Q  
8Q  
Package Options Include Plastic  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages, and Standard  
Plastic 300-mil DIPs (NT)  
description  
This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively  
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
The eight latches of the 74ACT11373 are transparent D-type latches. While the latch-enable (LE) input is high,  
the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels  
that were set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impendance third state and increased drive provide the capability to drive  
the bus lines in a bus-organized system without need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are off.  
The 74ACT11373 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
LE  
H
H
L
OE  
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
74ACT11373  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS015B – JUNE 1987 – REVISED APRIL 1996  
logic symbol  
24  
OE  
EN  
C1  
13  
LE  
23  
1D  
1
2
1D  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
22  
2D  
21  
3
3D  
20  
4
4D  
17  
9
5D  
16  
10  
11  
12  
6D  
15  
7D  
14  
8D  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
logic diagram (positive logic)  
24  
13  
OE  
LE  
C1  
1D  
1
2
23  
22  
21  
20  
17  
16  
15  
14  
1Q  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
C1  
1D  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
C1  
1D  
3
C1  
1D  
4
C1  
1D  
9
C1  
1D  
10  
11  
12  
C1  
1D  
C1  
1D  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
74ACT11373  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS015B – JUNE 1987 – REVISED APRIL 1996  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V  
+ 0.5 V  
+ 0.5 V  
I
CC  
CC  
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V  
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA  
IK  
I
I
CC  
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
Continuous current through V  
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA  
A
DW package . . . . . . . . . . . . . . . . . . 1.7 W  
NT package . . . . . . . . . . . . . . . . . . . 1.3 W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils,  
except for the NT package, which has a trace length of zero.  
recommended operating conditions  
MIN  
4.5  
2
MAX  
UNIT  
V
V
V
V
V
V
Supply voltage  
5.5  
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input voltage  
V
0.8  
V
0
0
V
V
V
I
CC  
Output voltage  
V
O
CC  
I
I
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Operating free-air temperature  
–24  
24  
mA  
mA  
ns/V  
°C  
OH  
OL  
t/ v  
0
10  
T
–40  
85  
A
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
74ACT11373  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS015B – JUNE 1987 – REVISED APRIL 1996  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
PARAMETER  
TEST CONDITIONS  
V
MIN  
MAX  
UNIT  
CC  
MIN  
4.4  
TYP  
MAX  
4.5 V  
5.5 V  
4.5 V  
5.5 V  
5.5 V  
4.5 V  
5.5 V  
4.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
5 V  
4.4  
5.4  
I
I
= –50 A  
OH  
5.4  
3.94  
4.94  
3.8  
V
V
OH  
OL  
= –24 mA  
= –75 mA  
OH  
4.8  
3.85  
I
I
OH  
0.1  
0.1  
0.1  
0.1  
0.44  
0.44  
1.65  
±5  
= 50  
A
OL  
0.36  
0.36  
V
V
I
I
= 24 mA  
= 75 mA  
OL  
OL  
I
I
I
V
= V or GND  
CC  
±0.5  
±0.1  
8
A
A
OZ  
O
V = V  
or GND  
or GND,  
±1  
I
I
CC  
CC  
V = V  
I = 0  
O
80  
A
CC  
I
I
One input at 3.4 V,  
V = V or GND  
Other inputs at GND or V  
CC  
0.9  
1
mA  
pF  
pF  
CC  
C
C
4
i
I
CC  
= V or GND  
CC  
V
5 V  
10  
o
O
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.  
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V  
.
CC  
timing requirements over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted) (see Figure 1)  
T
= 25°C  
A
MIN  
MAX  
UNIT  
MIN  
5
MAX  
t
w
t
su  
t
h
Pulse duration, LE high  
Setup time, data before LE↓  
Hold time, data LE↓  
5
3.5  
3.5  
ns  
ns  
ns  
3.5  
3.5  
switching characteristics over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted) (see Figure 1)  
T
A
= 25°C  
TYP  
7.5  
6.5  
8.5  
8.5  
7
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
MIN  
MAX  
UNIT  
ns  
MIN  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MAX  
10.3  
9.3  
t
t
t
t
t
t
t
t
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
11.8  
10  
PLH  
PHL  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
D
Q
11.3  
10.9  
10.7  
10.9  
12.1  
9.5  
13  
LE  
Any Q  
Any Q  
Any Q  
ns  
12.2  
12.5  
12  
ns  
OE  
OE  
7.5  
10  
12.2  
10.1  
ns  
7.5  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
74ACT11373  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS015B – JUNE 1987 – REVISED APRIL 1996  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
TYP  
65  
UNIT  
Outputs enabled  
Outputs disabled  
C
Power dissipation capacitance per latch  
C
= 50 pF,  
L
f = 1 MHz  
pF  
pd  
54  
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
Open  
GND  
S1  
500 Ω  
From Output  
Under Test  
TEST  
S1  
t
t
/t  
Open  
PLH PHL  
/t  
C
= 50 pF  
t
2 × V  
L
PLZ PZL  
CC  
500 Ω  
(see Note A)  
/t  
GND  
PHZ PZH  
LOAD CIRCUIT  
3 V  
Timing Input  
Data Input  
1.5 V  
0 V  
3 V  
0 V  
t
w
t
h
t
3 V  
su  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
0 V  
VOLTAGE WAVEFORMS  
VOLTAGE WAVEFORMS  
Output  
Control  
(low-level  
enabling)  
3 V  
0 V  
3 V  
0 V  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
t
PZL  
t
t
PHL  
PLH  
t
PLZ  
Output  
Waveform 1  
V
OH  
V
CC  
In-Phase  
Output  
50% V  
50% V  
CC  
50% V  
50% V  
CC  
V
CC  
20% V  
S1 at 2 × V  
(see Note B)  
CC  
CC  
CC  
V
V
OL  
OL  
t
PHZ  
t
PLH  
t
t
PHL  
PZH  
Output  
Waveform 2  
S1 at GND  
V
OH  
OH  
Out-of-Phase  
Output  
80% V  
50% V  
50% V  
CC  
CC  
CC  
0 V  
V
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
includes probe and jig capacitance.  
VOLTAGE WAVEFORMS  
NOTES: A.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t = 3 ns, t = 3 ns.  
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Nov-2009  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SSOP  
SSOP  
Drawing  
74ACT11373DBLE  
74ACT11373DBR  
OBSOLETE  
ACTIVE  
DB  
24  
24  
TBD  
Call TI  
Call TI  
DB  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
74ACT11373DBRE4  
74ACT11373DBRG4  
74ACT11373DW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
SSOP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
DB  
DB  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DW  
DW  
DW  
DW  
DW  
DW  
NT  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
74ACT11373DWE4  
74ACT11373DWG4  
74ACT11373DWR  
74ACT11373DWRE4  
74ACT11373DWRG4  
74ACT11373NT  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
15  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
74ACT11373NTE4  
NT  
15  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Nov-2009  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
29-Jul-2009  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
74ACT11373DBR  
74ACT11373DWR  
SSOP  
SOIC  
DB  
24  
24  
2000  
2000  
330.0  
330.0  
16.4  
24.4  
8.2  
8.8  
2.5  
2.7  
12.0  
12.0  
16.0  
24.0  
Q1  
Q1  
DW  
10.75 15.7  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
29-Jul-2009  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
74ACT11373DBR  
74ACT11373DWR  
SSOP  
SOIC  
DB  
24  
24  
2000  
2000  
346.0  
346.0  
346.0  
346.0  
33.0  
41.0  
DW  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Nov-2009  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SSOP  
SSOP  
Drawing  
74ACT11373DBLE  
74ACT11373DBR  
OBSOLETE  
ACTIVE  
DB  
24  
24  
TBD  
Call TI  
Call TI  
DB  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
74ACT11373DBRE4  
74ACT11373DBRG4  
74ACT11373DW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
SSOP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
DB  
DB  
24  
24  
24  
24  
24  
24  
24  
24  
24  
24  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DW  
DW  
DW  
DW  
DW  
DW  
NT  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
74ACT11373DWE4  
74ACT11373DWG4  
74ACT11373DWR  
74ACT11373DWRE4  
74ACT11373DWRG4  
74ACT11373NT  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
15  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
74ACT11373NTE4  
NT  
15  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Nov-2009  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
74ACT11373DBR  
74ACT11373DWR  
SSOP  
SOIC  
DB  
24  
24  
2000  
2000  
330.0  
330.0  
16.4  
24.4  
8.2  
8.8  
2.5  
2.7  
12.0  
12.0  
16.0  
24.0  
Q1  
Q1  
DW  
10.75 15.7  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
74ACT11373DBR  
74ACT11373DWR  
SSOP  
SOIC  
DB  
24  
24  
2000  
2000  
367.0  
367.0  
367.0  
367.0  
38.0  
45.0  
DW  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All  
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time  
of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or  
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the  
third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered  
documentation. Information of third parties may be subject to additional restrictions.  
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service  
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.  
TI is not responsible or liable for any such statements.  
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements  
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support  
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which  
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause  
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use  
of any TI components in safety-critical applications.  
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to  
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and  
requirements. Nonetheless, such components are subject to these terms.  
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties  
have executed a special agreement specifically governing such use.  
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in  
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components  
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and  
regulatory requirements in connection with such use.  
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which  
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such  
components to meet such requirements.  
Products  
Audio  
Applications  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
www.ti.com/security  
Medical  
Logic  
Security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense www.ti.com/space-avionics-defense  
microcontroller.ti.com  
www.ti-rfid.com  
Video and Imaging  
www.ti.com/video  
OMAP Mobile Processors www.ti.com/omap  
Wireless Connectivity www.ti.com/wirelessconnectivity  
TI E2E Community  
e2e.ti.com  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2012, Texas Instruments Incorporated  

相关型号:

74ACT11373DW

OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
TI

74ACT11373DWE4

ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOP-24
TI

74ACT11373DWG4

Octal Transparent D-Type Latches With 3-State Outputs 24-SOIC -40 to 85
TI

74ACT11373DWR

Octal Transparent D-Type Latches With 3-State Outputs 24-SOIC -40 to 85
TI

74ACT11373DWRE4

ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOP-24
TI

74ACT11373DWRG4

ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
TI

74ACT11373N

D Latch, 1-Func, 8-Bit, CMOS, PDIP24
PHILIPS

74ACT11373NSR

IC ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24, Bus Driver/Transceiver
TI

74ACT11373NSRG4

ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24
TI

74ACT11373NT

OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
TI

74ACT11373NTE4

Octal Transparent D-Type Latches With 3-State Outputs 24-PDIP -40 to 85
TI

74ACT11374

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
TI