74ACT11478NT [TI]
METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STATE OUTPUTS;
| 型号： | 74ACT11478NT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STATE OUTPUTS 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总5页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ACT11478
METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP
WITH 3–STATE OUTPUTS
SCAS131 – APRIL 1990 – REVISED APRIL 1993
DW OR NT PACKAGE
•
•
Inputs Are TTL-Voltage Compatible
(TOP VIEW)
Specifically Designed for Data
Synchronization Applications
1
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
OE
1D
2D
3D
4D
•
Improved Metastable Characteristics
Provide Greater System Reliability
2
3
•
•
3-State Outputs Drive Bus Lines Directly
4
4Q
5
GND
GND
GND
GND
5Q
6Q
7Q
8Q
Flow-Through Architecture to Optimize
PCB Layout
6
V
V
CC
CC
7
•
•
•
•
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations to
CC
8
5D
6D
7D
8D
9
EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process
10
11
12
500-mA Typical Latch-Up Immunity
at 125°C
CLK
Package Options Include Plastic Small
Outline Packages and Standard Plastic
300-mil DIPs
description
The 74ACT11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization
applications where the normal setup and hold time specifications are frequently violated.
Synchronization of two digital signals operating at different frequencies is a common system problem. This
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the
setup or hold time specification is violated, the output response is uncertain.
A flip-flop is metastable if its output hangs up in the region between V and V . The metastable condition lasts
IL
IH
until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can
be longer than the specified maximum propagation delay.
The problem of metastability is typically solved by adding an additional layer of synchronization. This type of
dual ranking is employed in the 74ACT11478. The probability of the second stage entering the metastable state
is exponentially reduced by this dual-rank architecture. The 74ACT11478 provides a one-chip solution for
system designers in asynchronous applications.
The 74ACT11478 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
†
OE
H
L
CLOCK
D
X
L
Q
Z
L
X
↑
L
↑
H
X
H
L
H
Q
O
†
Data presented at the D input requires two
clock cycles to appear at the Q output.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11478
METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP
WITH 3–STATE OUTPUTS
SCAS131 – APRIL 1990 – REVISED APRIL 1993
†
logic symbol
logic diagram (positive logic)
24
24
OE
OE
EN
C1
13
CLK
13
CLK
23
1
2
1D
1D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
23
1
22
1D
C1
1D
C1
1D
1Q
2D
21
3
3D
20
4
4D
17
9
5D
16
10
11
12
6D
To Seven Other Flip-Flops
15
7D
14
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
V
Supply voltage
5.5
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
0
V
V
V
I
CC
Output voltage
V
O
CC
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
– 24
24
mA
mA
ns /V
°C
OH
OL
t/ v
I
0
10
T
– 40
85
A
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11478
METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP
WITH 3–STATE OUTPUTS
SCAS131 – APRIL 1990 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
4.4
TYP
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.4
5.4
I
I
= – 50 A
OH
5.4
3.94
4.94
3.8
V
V
OH
OL
= – 24 mA
= – 75 mA
OH
4.8
3.85
I
I
OH
0.1
0.1
0.1
0.1
= 50
A
OL
0.36
0.36
0.44
0.44
1.65
± 5
V
V
I
I
= 24 mA
= 75 mA
OL
OL
I
I
I
V
= V or GND
CC
± 0.5
± 0.1
8
A
A
A
OZ
O
V = V
or GND
or GND,
± 1
I
I
CC
CC
V = V
I = 0
O
80
CC
I
One input at 3.4 V,
Other inputs at GND or V
‡
I
5.5 V
0.9
1
mA
CC
CC
C
C
V = V
or GND
5 V
5 V
4.5
12
pF
pF
i
I
CC
= V or GND
CC
V
O
o
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
= 25°C
A
MIN
MAX
UNIT
MHz
ns
MIN
0
MAX
Clock frequency
Pulse duration
75
0
4
75
f
t
clock
CLK high
CLK low
4
w
5
5
t
t
Setup time, data before CLK↑
Hold time, data after CLK↑
2.7
1.5
2.7
1.5
ns
ns
su
h
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
7.5
4.3
5.6
3.7
4.7
4.4
4.7
TYP
MAX
f
75
4.3
5.6
3.7
4.7
4.4
4.7
max
t
t
7.4
9.4
7.5
9.2
7.2
6.6
10.1
12.6
11.1
13.7
9.2
11.6
14.2
12.6
15.8
9.8
PLH
PHL
PZH
CLK
OE
Q
Q
Q
t
ns
ns
t
PZL
t
PHZ
OE
t
8.7
9.3
PLZ
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11478
METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP
WITH 3–STATE OUTPUTS
SCAS131 – APRIL 1990 – REVISED APRIL 1993
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
76
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per flip-flop
C
pF
pd
64
PARAMETER MEASUREMENT INFORMATION
2 X V
CC
Open
GND
S1
500 Ω
TEST
/t
S1
Open
2 x V
CC
GND
From Output
Under Test
t
t
t
PLH PHL
/t
PLZ PZL
/t
PHZ PZH
500 Ω
C
= 50 pF
L
(see Note A)
LOAD CIRCUIT
1.5 V
3 V
0 V
3 V
0
Timing Input
(see Note B)
High-Level
Input
1.5 V 1.5 V
t
t
h
w
t
su
3 V
0 V
Data
Input
3 V
0
1.5 V
1.5 V
Low-Level
Input
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
0
Output
Control
(Low-Level
Enabling)
1.5 V
1.5 V
3 V
Input
(see Note B)
1.5 V
1.5 V
0
t
PZL
t
PLZ
t
t
t
PHL
PLH
PHL
V
≈ V
OH
OL
CC
Output
Waveform 1
In-Phase
Output
50%
50%
50%
50%
t
20%
V
S1 at 2 x V
(see Note C)
CC
V
OL
t
PLH
PHZ
t
PZH
V
OH
OL
Out-of-Phase
Output
V
OH
Output
Waveform 2
S1 at GND
50%
80%
50%
V
≈ 0 V
(see Note C)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
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Copyright 1998, Texas Instruments Incorporated
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