74ACT11593_09 [TI]
8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS;
| 型号： | 74ACT11593_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS 输入元件 输出元件 |
| 文件： | 总8页 (文件大小：123K) |
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74ACT11593
8-BIT BINARY COUNTER
WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS
SCAS203 – JUNE 1992 – REVISED APRIL 1993
DW OR NT PACKAGE
• Inputs Are TTL-Voltage Compatible
(TOP VIEW)
• Parallel Register Inputs/Binary
Counter/3-State Outputs
A/Q
B/Q
C/Q
CCK
1
24
23
22
21
A
B
• Counter Has Direct Overriding Load and
CCLR
CCKEN
CCKEN
2
Clear
3
C
D
• Flow-Through Architecture Optimizes
D/Q
4
PCB Layout
GND
GND
GND
GND
5
20 CLOAD
6
19
18
V
V
• Center-Pin V
and GND Configurations
Minimize High-Speed Switching Noise
CC
CC
CC
7
8
17 OE
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
E/Q
9
16 OE
E
F/Q
10
11
12
15 RCK
14 RCK
13 RCO
F
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
G/Q
G
H/Q
H
description
The 74ACT11593 contains eight multiplexed parallel I/Os with 3-state output capability and an 8-bit storage
register that feeds an 8-bit binary counter. Both the register and the counter have individual positive-edge
triggered clocks.
The function tables show the operation of the counter clock-enable (CCKEN, CCKEN) and output-enable
(OE, OE) inputs.
The counter input has direct load and clear functions. A low-going RCO pulse is obtained when the counter
reaches the hex word FF.
Expansion is easily accomplished for two stages by connecting RCO of the first stage to CCKEN of the second
stage. Cascading for larger count chains is accomplished by connecting RCO of each stage to CCK of the
following stage.
The 74ACT11593 is characterized for operation from –40°C to 85°C.
Function Tables
COUNTER CLOCK ENABLE
INPUTS
OUTPUTS
OUTPUT ENABLE
INPUTS
OUTPUTS
A/Q THRU H/Q
A
A/Q THRU H/Q
A
H
H
CCKEN
CCKEN
OE
OE
L
L
L
L
H
L
Disable
Disable
Enable
Disable
L
L
Input mode
Input mode
Output mode
Input mode
H
H
H
H
H
L
H
H
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11593
8-BIT BINARY COUNTER
WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS
SCAS203 – JUNE 1992 – REVISED APRIL 1993
†
logic symbol
&
CTR8
17
16
OE
OE
EN6
G4
23
CT = 0
&
CCLR
22
21
24
20
CCKEN
CCKEN
CCK
13
CT = 255
RCO
4+
C3
CLOAD
14
15
G1
RCK
RCK
1C2
1
2D
A/Q
A
B
Z5
3D
5, 6
2
B/Q
3
4
C/Q
D/Q
C
D
9
E/Q
E
10
11
F/Q
F
G/Q
G
12
H/Q
H
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11593
8-BIT BINARY COUNTER
WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS
SCAS203 – JUNE 1992 – REVISED APRIL 1993
logic diagram (positive logic)
17
OE
16
OE
23
CCLR
22
13
CCKEN
RCO
21
CCKEN
24
CCK
20
CLOAD
14
RCK
15
RCK
1
1D
C1
S
A/Q
A
T
T
T
T
T
T
T
T
R
2
B/Q
1D
C1
S
B
R
3
4
9
1D
C1
S
C/Q
D/Q
C
D
R
1D
C1
S
R
E/Q
1D
C1
S
E
R
10
11
12
F/Q
1D
C1
S
F
R
G/Q
1D
C1
S
G
R
H/Q
1D
C1
S
H
R
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11593
8-BIT BINARY COUNTER
WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS
SCAS203 – JUNE 1992 – REVISED APRIL 1993
typical operating sequence
OE
OE
CCLR
CLOAD
CCK
CCKEN
CCKEN
RCK
RCK
Output Hex
00
H
Input Hex
FC
Output Hex
FC
Output Hex
FD
Output Hex Output Hex Output Hex
FE FF 00
A/Q through H/Q
A
RCO
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±225 mA
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11593
8-BIT BINARY COUNTER
WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS
SCAS203 – JUNE 1992 – REVISED APRIL 1993
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
V
0
0
V
V
V
I
CC
Output voltage
V
O
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
24
mA
mA
ns/V
°C
OH
OL
∆t/∆v
0
10
T
–40
85
A
NOTE 2: Unused or floating inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
4.4
TYP
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
4.4
5.4
I
= –50 µA
OH
5.4
V
3.94
4.94
3.8
V
OH
OL
I
I
I
= –24 mA
= –75 mA
= 50 µA
OH
OH
OL
4.8
†
3.85
0.1
0.1
0.1
0.1
0.44
0.44
1.65
±1
V
0.36
0.36
V
I
I
= 24 mA
OL
†
= 75 mA
OL
I
I
I
V = V
or GND
±0.1
±0.5
8
µA
µA
µA
mA
pF
pF
I
I
CC
V
= V
or GND
±5
OZ
CC
O
CC
V = V
or GND,
I
= 0
O
80
I
CC
‡
One input at 3.4 V,
V = V or GND
Other inputs at V
or GND
0.9
1
∆I
CC
CC
C
C
3.5
i
I
CC
= V or GND
CC
V
5 V
12.5
io
O
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11593
8-BIT BINARY COUNTER
WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS
SCAS203 – JUNE 1992 – REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
MAX
f
t
Clock frequency, CCK or RCK
Pulse duration
52
52
MHz
clock
CCK high or low
9.6
5.8
7.6
6.2
3.6
4
9.6
5.8
7.6
6.2
3.6
4
RCK high or low
ns
w
CCLR low
CLOAD low
CCKEN low before CCK↑
CCKEN high before CCK↑
CCLR high before CCK↑
CLOAD high before CCK↑
1.2
5.1
7.4
2.4
1.2
0.8
1.2
5.1
7.4
2.4
1.2
0.8
t
t
Setup time
Hold time
ns
ns
su
†
RCK↑ before CLOAD↑
Data A thru H before RCK↑
Data A thru H after RCK↑
All others
h
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
52
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
52
5.6
5.8
5.5
5.8
5
max
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
PLH
PHL
PLH
PHL
PLH
PLH
PHL
5.6
5.8
5.5
5.8
5
10.2
10.3
12
13.3
13.3
16.9
19.4
14.3
14.3
14.8
14.4
15
15.1
15
CCK
Q
19.1
21.7
16
Q
Q
Q
ns
ns
ns
CLOAD
CCLR
13.5
10.4
10.9
11.1
10.4
10.7
9
5.9
5.9
4.9
5.1
5.3
6.2
5.6
6.4
4.9
5.8
4.6
7.1
5.1
6.7
7.5
5.9
5.9
4.9
5.1
5.3
6.2
5.6
6.4
4.9
5.8
4.6
7.1
5.1
6.7
7.5
16.3
16.9
16.5
17
OE
OE
OE
Q
Q
ns
ns
ns
ns
11.8
13.1
10.7
12
12.9
14.4
11.6
13.3
13.7
16.3
15
10.2
8.6
Q
OE
9.9
9.2
12.1
14.3
13.3
18.5
14.5
15.6
17.8
CCK
RCO
10.9
9.6
ns
ns
ns
CLOAD
CCLR
RCK
RCO
RCO
13.6
10.3
12
21
16.2
17.7
20.2
RCO
13.6
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74ACT11593
8-BIT BINARY COUNTER
WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS
SCAS203 – JUNE 1992 – REVISED APRIL 1993
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
61
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance
C
pF
pd
15
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
0 V
Timing Input
(see Note B)
1.5 V
t
w
t
h
t
3 V
su
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
Input
(see Note B)
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note C)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
0 V
V
OL
(see Note C)
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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