74ACT16620DL [TI]
16-Bit Bus Transceivers With 3-State Outputs 48-SSOP -40 to 85;
| 型号： | 74ACT16620DL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Bus Transceivers With 3-State Outputs 48-SSOP -40 to 85 总线收发器 输出元件 |
| 文件： | 总6页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS184A − JUNE 1990 − REVISED APRIL 1996
54ACT16620 . . . WD PACKAGE
74ACT16620 . . . DL PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
Inverting Logic
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OEAB
1B1
1OEBA
1A1
Flow-Through Architecture Optimizes
PCB Layout
2
3
1B2
1A2
4
GND
1B3
GND
1A3
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
5
6
1B4
1A4
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
7
V
V
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
125°C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
V
V
CC
CC
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
The ’ACT16620 are inverting 16-bit transceivers
designed for asynchronous communication
between data buses. The control-function
implementation allows for maximum flexibility in
timing.
2OEAB
2OEBA
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the output-enable (OEAB or OEBA)
inputs. The output-enable inputs can be used to
disable the device so that the buses are effectively
isolated.
The dual-enable configuration gives the transceiver the capability to store data by simultaneously enabling
OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control
inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, the bus lines
remain at their last states.
The 74ACT16620 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16620 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16620 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢆ ꢇꢈ ꢉ ꢊ ꢁꢂꢃ ꢄꢅ ꢆ ꢆ ꢇ ꢈ
ꢅꢆ ꢋꢌꢍ ꢄ ꢌ ꢎ ꢏ ꢄ ꢐ ꢂ ꢑꢏ ꢃꢒ ꢍ ꢓꢒ ꢐꢏ
ꢔꢍ ꢄ ꢕ ꢖ ꢋꢏꢄꢂꢄ ꢒ ꢗꢎꢄ ꢘ ꢎꢄꢏ
SCAS184A − JUNE 1990 − REVISED APRIL 1996
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OEBA
OEAB
L
L
B data to A bus
B data to A bus,
A data to B bus
L
H
H
H
L
Isolation
H
A data to B bus
†
logic symbol
48
1
EN1
EN2
EN3
EN4
1OEBA
1OEAB
25
24
2OEBA
2OEAB
47
2
1A1
1B1
1
1
1
2
46
44
43
41
40
38
37
36
3
5
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
6
8
9
11
12
13
3
1
1
4
35
33
32
30
29
27
26
14
16
17
19
20
22
23
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS184A − JUNE 1990 − REVISED APRIL 1996
logic diagram (positive logic)
25
24
36
48
2OEBA
2OEAB
2A1
1OEBA
1
1OEAB
47
1A1
13
2
2B1
1B1
To Seven Other Channels
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
Maximum package power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.2 W
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16620
MIN NOM
74ACT16620
MIN NOM
UNIT
MAX
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
24
−24
24
mA
mA
ns/V
°C
OH
OL
I
∆t/∆v
0
10
0
10
T
−55
125
−40
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢆ ꢇꢈ ꢉ ꢊ ꢁꢂꢃ ꢄꢅ ꢆ ꢆ ꢇ ꢈ
ꢅꢆ ꢋꢌꢍ ꢄ ꢌ ꢎ ꢏ ꢄ ꢐ ꢂ ꢑꢏ ꢃꢒ ꢍ ꢓꢒ ꢐꢏ
ꢔꢍ ꢄ ꢕ ꢖ ꢋꢏꢄꢂꢄ ꢒ ꢗꢎꢄ ꢘ ꢎꢄꢏ
SCAS184A − JUNE 1990 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54ACT16620
74ACT16620
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
= −50 µA
OH
5.4
5.4
5.4
3.94
4.94
3.8
3.8
V
V
OH
I
I
= −24 mA
= −75 mA
OH
4.8
4.8
†
3.85
3.85
OH
0.1
0.1
0.1
0.1
0.44
0.44
1.65
1
0.1
0.1
0.44
0.44
1.65
1
I
= 50 µA
OL
0.36
0.36
V
V
OL
I
I
= 24 mA
OL
†
= 75 mA
OL
I
I
I
Control inputs V = V
or GND
or GND
0.1
0.5
8
µA
µA
µA
I
I
CC
‡
A or B ports
V
= V
5
5
O
CC
OZ
CC
V = V
or GND,
I
O
= 0
80
80
I
CC
One input at 3.4 V,
Other inputs at V
§
5.5 V
0.9
1
1
mA
∆I
CC
or GND
CC
or GND
C
C
Control inputs V = V
CC
5 V
5 V
4
pF
pF
i
I
A or B ports
V = V
O CC
or GND
15
io
†
‡
§
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
5
54ACT16620
74ACT16620
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
2
MAX
7.7
9.3
8.3
10
MIN
2
MAX
8.5
MIN
2
MAX
8.5
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
A or B
OEBA
OEBA
OEAB
OEAB
B or A
4
7
4
10.5
9.1
4
10.5
9.1
2.2
2.8
6
5.5
6.4
8.8
7.9
6.2
7.1
7.8
6.7
2.2
2.8
6
2.2
2.8
6
A
A
B
B
ns
10.9
11.9
10.6
8.9
10.9
11.9
10.6
8.9
11
ns
5.1
3.6
4.4
5
10
5.1
3.6
4.4
5
5.1
3.6
4.4
5
7.9
9.4
10.1
9.1
ns
10.5
10.8
9.6
10.5
10.8
9.6
ns
4.1
4.1
4.1
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
57
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per transceiver
C
pF
pd
10
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ꢡ ꢜ ꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢ ꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠ ꢟꢢꢡ ꢛꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ ꢆ ꢋꢌꢍ ꢄ ꢌꢎꢏ ꢄ ꢐꢂꢑꢏ ꢃꢒ ꢍ ꢓꢒ ꢐ
ꢅ
ꢆ
ꢆ
ꢇ
ꢈ
ꢏ
ꢏ
ꢔ ꢍꢄ ꢕ ꢖ ꢋꢏꢄꢂꢄ ꢒ ꢗ ꢎꢄ ꢘꢎ ꢄ
SCAS184A − JUNE 1990 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
500 Ω
Open
GND
t
/t
Open
From Output
Under Test
PLH PHL
t
/t
2 × V
CC
GND
PLZ PZL
t
/t
C
= 50 pF
PHZ PZH
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
3 V
0 V
LOAD CIRCUIT
1.5 V
1.5 V
t
PZL
3 V
0 V
t
PLZ
Output
Waveform 1
[ V
Input
CC
1.5 V
1.5 V
50% V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
V
OL
t
PLH
t
PHZ
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
80% V
CC
50% V
CC
50% V
Output
CC
50% V
CC
V
OL
[ 0 V
(see Note B)
VOLTAGE WAVEFORMS
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
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