74ACT16827DL [TI]

20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 20位缓冲器/驱动器,具有三态输出
74ACT16827DL
型号: 74ACT16827DL
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
20位缓冲器/驱动器,具有三态输出

总线驱动器 总线收发器 逻辑集成电路 光电二极管 输出元件
文件: 总8页 (文件大小:149K)
中文:  中文翻译
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54ACT16827, 74ACT16827  
20-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCAS163A – JUNE 1990 – REVISED APRIL 1996  
54ACT16827 . . . WD PACKAGE  
74ACT16827 . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Inputs Are TTL-Voltage Compatible  
3-State Outputs Drive Bus Lines Directly  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OE1  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
1OE2  
1A1  
1A2  
GND  
1A3  
A14  
Flow-Through Architecture Optimizes  
PCB Layout  
2
3
4
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
5
6
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
7
V
V
CC  
CC  
8
1Y5  
1Y6  
1Y7  
GND  
1Y8  
1Y9  
1Y10  
2Y1  
2Y2  
2Y3  
GND  
2Y4  
2Y5  
2Y6  
1A5  
1A6  
1A7  
GND  
1A8  
1A9  
1A10  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
500-mA Typical Latch-Up Immunity at  
125°C  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Packages Using  
25-mil Center-to-Center Pin Spacings and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Packages Using 25-mil Center-to-Center  
Pin Spacings  
description  
The ’ACT16827 are noninverting 20-bit buffers  
composed of two 10-bit sections with separate  
output-enable signals. For either 10-bit buffer  
section, the two output-enable (1OE1 and 1OE2  
or 2OE1 and 2OE2) inputs must both be low for  
the corresponding Y outputs to be active. If either  
output-enable input is high, the outputs of that  
10-bit buffer section are in the high-impedance  
state.  
V
V
CC  
CC  
2Y7  
2Y8  
GND  
2Y9  
2Y10  
2OE1  
2A7  
2A8  
GND  
2A9  
2A10  
2OE2  
The 74ACT16827 is packaged in TI’s shrink  
small-outline package, which provides twice the  
I/O pin count and functionality of standard  
small-outline packages in the same printed-  
circuit-board area.  
The 54ACT16827 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
74ACT16827 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each 8-bit section)  
INPUTS  
OUTPUT  
Y
A
L
OE1  
L
OE2  
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
54ACT16827, 74ACT16827  
20-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCAS163A – JUNE 1990 – REVISED APRIL 1996  
logic symbol  
1
&
&
1OE1  
1OE2  
EN1  
EN2  
56  
28  
29  
2OE1  
2OE2  
55  
54  
52  
51  
49  
48  
47  
45  
44  
43  
2
3
1A1  
1A2  
1A3  
1A4  
1A5  
1A6  
1A7  
1A8  
1A9  
1A10  
1
1
1Y1  
1Y2  
1Y3  
1Y4  
1Y5  
1Y6  
1Y7  
1Y8  
1Y9  
1Y10  
5
6
8
9
10  
12  
13  
14  
42  
41  
40  
38  
37  
36  
34  
33  
31  
30  
15  
16  
17  
19  
20  
21  
23  
24  
26  
27  
2A1  
2A2  
2A3  
2A4  
2A5  
2A6  
2A7  
2A8  
2A9  
2A10  
1
2
2Y1  
2Y2  
2Y3  
2Y4  
2Y5  
2Y6  
2Y7  
2Y8  
2Y9  
2Y10  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
logic diagram (positive logic)  
1
28  
29  
1OE1  
2OE1  
2OE2  
56  
1OE2  
55  
2
42  
15  
1Y1  
1A1  
2Y1  
2A1  
To Nine Other Channels  
To Nine Other Channels  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
54ACT16827, 74ACT16827  
20-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCAS163A – JUNE 1990 – REVISED APRIL 1996  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V  
+ 0.5 V  
+ 0.5 V  
I
CC  
CC  
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V  
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA  
IK  
I
I
CC  
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Continuous current through V  
Maximum package power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . 1.4 W  
Storage temperature range, T  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mA  
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils.  
recommended operating conditions (see Note 3)  
54ACT16827  
MIN NOM  
54ACT16827  
MIN NOM  
UNIT  
MAX  
MAX  
V
V
V
V
V
Supply voltage  
4.5  
2
5
5.5  
4.5  
2
5
5.5  
V
V
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input voltage  
0.8  
0.8  
V
0
0
V
V
0
0
V
V
V
I
CC  
CC  
Output voltage  
V
O
CC  
CC  
I
I
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Operating free-air temperature  
–24  
24  
–24  
24  
mA  
mA  
ns/V  
°C  
OH  
OL  
t/v  
0
10  
0
10  
T
–55  
125  
–40  
85  
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
54ACT16827, 74ACT16827  
20-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCAS163A – JUNE 1990 – REVISED APRIL 1996  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
54ACT16827  
74ACT16827  
PARAMETER  
TEST CONDITIONS  
V
UNIT  
CC  
MIN  
4.4  
TYP  
MAX  
MIN  
4.4  
MAX  
MIN  
4.4  
MAX  
4.5 V  
5.5 V  
4.5 V  
5.5 V  
5.5 V  
4.5 V  
5.5 V  
4.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
I
= –50 µA  
OH  
5.4  
5.4  
5.4  
V
3.94  
4.94  
3.8  
3.8  
V
OH  
OL  
I
I
I
= –24 mA  
= –75 mA  
= 50 µA  
OH  
OH  
OL  
4.8  
4.8  
3.85  
3.85  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
0.36  
0.36  
0.44  
0.44  
1.65  
±1  
0.44  
0.44  
1.65  
±1  
V
I
I
= 24 mA  
OL  
= 75 mA  
OL  
I
I
I
V = V  
or GND  
±0.1  
±0.5  
8
µA  
µA  
µA  
I
I
CC  
V
= V  
or GND  
±5  
±5  
OZ  
CC  
O
CC  
V = V  
or GND,  
I
O
= 0  
80  
80  
I
CC  
One input at 3.4 V,  
Other inputs at V  
5.5 V  
0.9  
1
1
mA  
I  
CC  
or GND  
CC  
or GND  
C
C
V = V  
5 V  
5 V  
4.5  
16  
pF  
pF  
i
I
CC  
= V or GND  
CC  
V
o
O
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.  
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V  
.
CC  
switching characteristics over recommended operating free-air temperature range,  
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)  
V
CC  
T
A
= 25°C  
TYP  
7.4  
54ACT16827  
74ACT16827  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
ns  
MIN  
3.6  
2.8  
3
MAX  
9.8  
MIN  
3.6  
2.8  
3
MAX  
11  
MIN  
3.6  
2.8  
3
MAX  
11  
t
t
t
t
t
t
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
A
Y
Y
Y
7.4  
9.8  
10.8  
11.7  
14  
10.8  
11.7  
14  
7.9  
10.4  
12.4  
11.3  
10.5  
ns  
OE  
OE  
4
9.6  
4
4
5.8  
5.3  
9.1  
5.8  
5.3  
12.4  
11.5  
5.8  
5.3  
12.4  
11.5  
ns  
8.5  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
= 50 pF, f = 1 MHz  
L
TYP  
41  
UNIT  
Outputs enabled  
Outputs disabled  
C
Power dissipation capacitance  
C
pF  
pd  
10  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
54ACT16827, 74ACT16827  
20-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCAS163A – JUNE 1990 – REVISED APRIL 1996  
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
Open  
GND  
TEST  
S1  
S1  
t
/t  
Open  
PLH PHL  
/t  
500 Ω  
From Output  
Under Test  
t
2 × V  
CC  
GND  
PLZ PZL  
t
/t  
PHZ PZH  
C
= 50 pF  
L
500 Ω  
(see Note A)  
LOAD CIRCUIT  
Output  
Control  
(low-level  
enabling)  
3 V  
0 V  
3 V  
0 V  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Input  
t
PZL  
t
t
PHL  
PLH  
t
PLZ  
Output  
Waveform 1  
V
OH  
V
CC  
In-Phase  
Output  
50% V  
50% V  
CC  
50% V  
50% V  
CC  
V
CC  
20% V  
S1 at 2 × V  
(see Note B)  
CC  
CC  
CC  
V
V
OL  
OL  
t
PHZ  
t
PLH  
t
t
PHL  
PZH  
Output  
Waveform 2  
S1 at GND  
V
OH  
OH  
0 V  
Out-of-Phase  
Output  
80% V  
50% V  
50% V  
CC  
CC  
CC  
V
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
NOTES: A. C includes probe and jig capacitance.  
VOLTAGE WAVEFORMS  
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t = 3 ns, t = 3 ns.  
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
3-May-2005  
PACKAGING INFORMATION  
Orderable Device  
74ACT16827DL  
74ACT16827DLR  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SSOP  
DL  
56  
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SSOP  
DL  
56  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001  
DL (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0.025 (0,635)  
48  
0.0135 (0,343)  
0.008 (0,203)  
0.005 (0,13)  
M
25  
0.010 (0,25)  
0.005 (0,13)  
0.299 (7,59)  
0.291 (7,39)  
0.420 (10,67)  
0.395 (10,03)  
Gage Plane  
0.010 (0,25)  
0°ā8°  
1
24  
0.040 (1,02)  
0.020 (0,51)  
A
Seating Plane  
0.004 (0,10)  
0.008 (0,20) MIN  
PINS **  
0.110 (2,79) MAX  
28  
48  
0.630  
56  
DIM  
0.380  
(9,65)  
0.730  
A MAX  
A MIN  
(16,00) (18,54)  
0.370  
(9,40)  
0.620  
0.720  
(15,75) (18,29)  
4040048/E 12/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).  
D. Falls within JEDEC MO-118  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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74ACT16833

DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
TI

74ACT16833DL

ACT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56
ROCHESTER

74ACT16833DL

Dual 8-Bit To 9-Bit Parity Bus Transceivers 56-SSOP -40 to 85
TI

74ACT16833DLR

暂无描述
TI
ETC

74ACT16834DLR

IC ACT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver
TI

74ACT16841

20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
TI