74ACT715DC_技术文档

March 1995

LM1882 54ACT/74ACT715

#

LM1882-R 54ACT/74ACT715-R

#

Programmable Video Sync Generator

’ACT715-R/LM1882-R is mask programmed to default to a

Clock Enabled state. Bit 10 of the Status Register defaults

to a logic ‘‘1’’. Although completely (re)programmable, the

’ACT715-R/LM1882-R version is better suited for applica-

tions using the default 14.31818 MHz RS-170 register val-

ues. This feature allows power-up directly into operation,

following a single CLEAR pulse.

General Description

The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are

20-pin TTL-input compatible devices capable of generating

Horizontal, Vertical and Composite Sync and Blank signals

for televisions and monitors. All pulse widths are completely

definable by the user. The devices are capable of generat-

ing signals for both interlaced and noninterlaced modes of

operation. Equalization and serration pulses can be intro-

duced into the Composite Sync signal when needed.

Features

Y

l

130 MHz

Maximum Input Clock Frequency

Four additional signals can also be made available when

Composite Sync or Blank are used. These signals can be

used to generate horizontal or vertical gating pulses, cursor

position or vertical Interrupt signal.

Interlaced and non-interlaced formats available

Separate or composite horizontal and vertical Sync and

Blank signals available

Y

Complete control of pulse width via register

programming

These devices make no assumptions concerning the sys-

tem architecture. Line rate and field/frame rate are all a

function of the values programmed into the data registers,

the status register, and the input clock frequency.

Y

All inputs are TTL compatible

8 mA drive on all outputs

Default RS170/NTSC values mask programmed into

registers

The ’ACT715/LM1882 is mask programmed to default to a

Clock Disable state. Bit 10 of the Status Register, Register

0, defaults to a logic ‘‘0’’. This facilitates (re)programming

before operation.

Y

4 KV minimum ESD immunity

’ACT715-R/LM1882-R is mask programmed to default

to a Clock Enable state for easier start-up into

14.31818 MHz RS170 timing

The ’ACT715-R/LM1882-R is the same as the

’ACT715/LM1882 in all respects except that the

Connection Diagrams

Pin Assignment for

DIP and SOIC

Pin Assignment

for LCC

TL/F/10137–1

Order Number LM1882CN or LM1882CM

For Default RS-170, Order Number LM1882-RCN or

LM1882-RCM

TL/F/10137–2

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

FACT^TMis a trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation

TL/F/10137

RRD-B30M105/Printed in U. S. A.

Logic Block Diagram

TL/F/10137–3

Pin Description

There are

’ACT715/LM1882.

a

Total of 13 inputs and

5

outputs on the

ODD/EVEN: Output that identifies if display is in odd (HIGH)

or even (LOW) field of interlace when device is in interlaced

mode of operation. In noninterlaced mode of operation this

output is always HIGH. Data can be serially scanned out on

this pin during Scan Mode.

Data Inputs D0–D7: The Data Input pins connect to the

Address Register and the Data Input Register.

ADDR/DATA: The ADDR/DATA signal is latched into the

device on the falling edge of the LOAD signal. The signal

determines if an address (0) or data (1) is present on the

data bus.

VCSYNC: Outputs Vertical or Composite Sync signal based

on value of the Status Register. Equalization and Serration

pulses will (if enabled) be output on the VCSYNC signal in

composite mode only.

L/HBYTE: The L/HBYTE signal is latched into the device

on the falling edge of the LOAD signal. The signal deter-

mines if data will be read into the 8 LSB’s (0) or the 4 MSB’s

(1) of the Data Registers. A 1 on this pin when an ADDR/

DATA is a 0 enables Auto-Load Mode.

VCBLANK: Outputs Vertical or Composite Blanking signal

based on value of the Status Register.

HBLHDR: Outputs Horizontal Blanking signal, Horizontal

Gating signal or Cursor Position based on value of the

Status Register.

LOAD: The LOAD control pin loads data into the Address or

Data Registers on the rising edge. ADDR/DATA and

L/HBYTE data is loaded into the device on the falling edge

of the LOAD. The LOAD pin has been implemented as a

Schmitt trigger input for better noise immunity.

HSYNVDR: Outputs Horizontal Sync signal, Vertical Gating

signal or Vertical Interrupt signal based on value of Status

Register.

Register Description

CLOCK: System CLOCK input from which all timing is de-

rived. The clock pin has been implemented as a Schmitt

trigger for better noise immunity. The CLOCK and the LOAD

signal are asynchronous and independent. Output state

changes occur on the falling edge of CLOCK.

All of the data registers are 12 bits wide. Width’s of all puls-

es are defined by specifying the start count and end count

of all pulses. Horizontal pulses are specified with-respect-to

the number of clock pulses per line and vertical pulses are

specified with-respect-to the number of lines per frame.

CLR: The CLEAR pin is an asynchronous input that initializ-

es the device when it is HIGH. Initialization consists of set-

ting all registers to their mask programmed values, and ini-

tializing all counters, comparators and registers. The

CLEAR pin has been implemented as a Schmitt trigger for

better noise immunity. A CLEAR pulse should be asserted

by the user immediately after power-up to ensure proper

initialization of the registersÐeven if the user plans to

(re)program the device.

REG0ÐSTATUS REGISTER

The Status Register controls the mode of operation, the

signals that are output and the polarity of these outputs. The

default value for the Status Register is 0 (000 Hex) for the

’ACT715/LM1882 and is ‘‘512’’ (200 Hex) for the ’ACT715-

R/LM1882-R.

Note: A CLEAR pulse will disable the CLOCK on the ’ACT715/LM1882 and

will enable the CLOCK on the ’ACT715-R/LM1882-R.

2

Register Description (Continued)

Bits 0–2

HORIZONTAL INTERVAL REGISTERS

The Horizontal Interval Registers determine the number of

clock cycles per line and the characteristics of the Horizon-

tal Sync and Blank pulses.

B

VCBLANK VCSYNC HBLHDR HSYNVDR

0

2

1

0

CBLANK

CSYNC HGATE

VGATE

(DEFAULT)

REG1Ð Horizontal Front Porch

0

1

0

1

VBLANK

CBLANK

VBLANK

CSYNC HBLANK

VGATE

HSYNC

REG2Ð Horizontal Sync Pulse End Time

REG3Ð Horizontal Blanking Width

VSYNC

HGATE

VSYNC HBLANK

Ý

REG4Ð Horizontal Interval Width

of Clocks per Line

1

0

1

0

1

0

1

CBLANK

VBLANK

CBLANK

VBLANK

CSYNC CURSOR

CSYNC HBLANK

VINT

VERTICAL INTERVAL REGISTERS

The Vertical Interval Registers determine the number of

lines per frame, and the characteristics of the Vertical Blank

and Sync Pulses.

VSYNC CURSOR HSYNC

VSYNC HBLANK

HSYNC

Bits 3–4

REG5Ð Vertical Front Porch

REG6Ð Vertical Sync Pulse End Time

REG7Ð Vertical Blanking Width

B

Mode of Operation

4

3

0

Interlaced Double Serration and

Equalization

Ý

REG8Ð Vertical Interval Width

of Lines per Frame

(DEFAULT)

EQUALIZATION AND SERRATION PULSE

SPECIFICATION REGISTERS

0

1

0

1

Non Interlaced Double Serration

Illegal State

These registers determine the width of equalization and ser-

ration pulses and the vertical interval over which they occur.

Non Interlaced Single Serration

and Equalization

REG 9Ð Equalization Pulse Width End Time

REG10Ð Serration Pulse Width End Time

Double Equalization and Serration mode will output equali-

zation and serration pulses at twice the HSYNC frequency

(i.e., 2 equalization or serration pulses for every HSYNC

pulse). Single Equalization and Serration mode will output

an equalization or serration pulse for every HSYNC pulse. In

Interlaced mode equalization and serration pulses will be

output during the VBLANK period of every odd and even

field. Interlaced Single Equalization and Serration mode is

not possible with this part.

REG11Ð Equalization/Serration Pulse Vertical

Interval Start Time

REG12Ð Equalization/Serration Pulse Vertical

Interval End Time

VERTICAL INTERRUPT SPECIFICATION REGISTERS

These Registers determine the width of the Vertical Inter-

rupt signal if used.

Bits 5–8

REG13Ð Vertical Interrupt Activate Time

REG14Ð Vertical Interrupt Deactivate Time

Bits 5 through 8 control the polarity of the outputs. A value

of zero in these bit locations indicates an output pulse active

LOW. A value of 1 indicates an active HIGH pulse.

CURSOR LOCATION REGISTERS

B5Ð VCBLANK Polarity

B6Ð VCSYNC Polarity

B7Ð HBLHDR Polarity

B8Ð HSYNVDR Polarity

These 4 registers determine the cursor position location, or

they generate separate Horizontal and Vertical Gating sig-

nals.

REG15Ð Horizontal Cursor Position Start Time

REG16Ð Horizontal Cursor Position End Time

REG17Ð Vertical Cursor Position Start Time

REG18Ð Vertical Cursor Position End Time

Bits 9–11

Bits 9 through 11 enable several different features of the

device.

B9Ð Enable Equalization/Serration Pulses (0)

Disable Equalization/Serration Pulses (1)

Signal Specification

HORIZONTAL SYNC AND BLANK

SPECIFICATIONS

B10Ð Disable System Clock (0)

Enable System Clock (1)

Default values for B10 are ‘‘0’’ in the ’ACT715/

LM1882 and ‘‘1’’ in the ’ACT715-R/LM1882-R.

All horizontal signals are defined by a start and end time.

The start and end times are specified in number of clock

cycles per line. The start of the horizontal line is considered

pulse 1 not 0. All values of the horizontal timing registers are

referenced to the falling edge of the Horizontal Blank signal

B11Ð Disable Counter Test Mode (0)

Enable Counter Test Mode (1)

This bit is not intended for the user but is for internal

testing only.

Ý

(see Figure 1 ). Since the first CLOCK edge, CLOCK 1,

causes the first falling edge of the Horizontal Blank refer-

ence pulse, edges referenced to this first Horizontal edge

a

are n

1 CLOCKs away, where ‘‘n’’ is the width of the

timing in question. Registers 1, 2, and 3 are programmed in

this manner. The horizontal counters start at 1 and count

until HMAX. The value of HMAX must be divisible by 2. This

3

Signal Specification (Continued)

TL/F/10137–4

FIGURE 1. Horizontal Waveform Specification

e

c

hper

limitation is imposed because during interlace operation this

value is internally divided by 2 in order to generate serration

Vertical Frame Period (VPER)

Vertical Field Period (VPER/n)

REG(8)

e

c

hper/n

c

]

1 hper/n

c

and equalization pulses at 2

the horizontal frequency.

e

b

[

Vertical Blanking Width

Vertical Syncing Width

REG(7)

Horizontal signals will change on the falling edge of the

CLOCK signal. Signal specifications are shown below.

e

b

c

]

REG(5) hper/n

[

REG(6)

e

b

c

[

]

Vertical Front Porch

REG(5)

1

hper/n

e

c

ckper

Horizontal Period (HPER)

Horizontal Blanking Width

Horizontal Sync Width

Horizontal Front Porch

REG(4)

e

where n

n

1 for noninterlaced

2 for interlaced

b

c

ckper

[

]

REG(3)

REG(2)

REG(1)

1

b

c

ckper

]

REG(1)

COMPOSITE SYNC AND BLANK SPECIFICATION

c

]

1

ckper

Composite Sync and Blank signals are created by logically

ANDing (ORing) the active LOW (HIGH) signals of the cor-

responding vertical and horizontal components of these sig-

nals. The Composite Sync signal may also include serration

and/or equalization pulses. The Serration pulse interval oc-

curs in place of the Vertical Sync interval. Equalization puls-

es occur preceding and/or following the Serration pulses.

The width and location of these pulses can be programmed

through the registers shown below. (See Figure 2B.)

VERTICAL SYNC AND BLANK SPECIFICATION

All vertical signals are defined in terms of number of lines

per frame. This is true in both interlaced and noninterlaced

modes of operation. Care must be taken to not specify the

Vertical Registers in terms of lines per field. Since the first

Ý

CLOCK edge, CLOCK 1, causes the first falling edge of

the Vertical Blank (first Horizontal Blank) reference pulse,

a

edges referenced to this first edge are n

1 lines away,

where ‘‘n’’ is the width of the timing in question. Registers 5,

6, and 7 are programmed in this manner. Also, in the inter-

laced mode, vertical timing is based on half-lines. Therefore

registers 5, 6, and 7 must contain a value twice the total

horizontal (odd and even) plus 1 (as described above). In

non-interlaced mode, all vertical timing is based on whole-

lines. Register 8 is always based on whole-lines and does

not add 1 for the first clock. The vertical counter starts at

the value of 1 and counts until the value of VMAX. No re-

strictions exist on the values placed in the vertical registers.

Vertical Blank will change on the leading edge of HBLANK.

Vertical Sync will change on the leading edge of HSYNC.

(See Figure 2A.)

e

b

e

c

]

REG(1) ckper

[

REG 9

Horizontal Equalization PW

REG(9)

a

(HFP)

(HEQP)

a

1

e

a

ckper

b

[

REG(10)

Horizontal Serration PW

REG(4)/n

]

REG(1)

c

e

(HSERR)

a

1

REG 10

b

(HFP)

a

(HPER/

2)

e

Where n

n

1 for noninterlaced single serration/equalization

2 for noninterlaced double

serration/equalization

e

n

2 for interlaced operation

4

Signal Specification (Continued)

TL/F/10137–5

FIGURE 2A. Vertical Waveform Specification

TL/F/10137–12

FIGURE 2B. Equalization/Serration Interval Programming

HORIZONTAL AND VERTICAL GATING SIGNALS

and Bit 2 of the Status Register is set to the value of 1. The

Cursor Position generates a single pulse of n clocks wide

during every line that the cursor is specified. The signals are

generated by logically ORing (ANDing) the active LOW

(HIGH) signals specified by the registers used for generat-

ing Horizontal and Vertical Gating signals. The Vertical In-

terrupt signal generates a pulse during the vertical interval

specified. The Vertical Interrupt signal will change in the

same manner as that specified for the Vertical Blanking sig-

nal.

Horizontal Drive and Vertical Drive outputs can be utilized

as general purpose Gating Signals. Horizontal and Vertical

Gating Signals are available for use when Composite Sync

and Blank signals are selected and the value of Bit 2 of the

Status Register is 0. The Vertical Gating signal will change

in the same manner as that specified for the Vertical Blank.

e

b

c

[

REG(16)

ckper

]

Horizontal Gating Signal Width

REG(15)

e

b

c

[

REG(18)

hper

]

Vertical Gating Signal Width

REG(17)

e

b

c

]

REG(15)

[

Horizontal Cursor Width

REG(16)

ckper

e

b

c

]

[

Vertical Cursor Width

REG(18)

REG(17)

hper

CURSOR POSITION AND VERTICAL INTERRUPT

e

b

c

]

REG(13) hper

[

Vertical Interrupt Width

REG(14)

The Cursor Position and Vertical Interrupt signal are avail-

able when Composite Sync and Blank signals are selected

5

Addressing Logic

The register addressing logic is composed of two blocks of

logic. The first is the address register and counter

(ADDRCNTR), and the second is the address decode

(ADDRDEC).

time the High Byte is written the address counter is incre-

mented by 1. The counter has been implemented to loop on

the initial value loaded into the address register. For exam-

ple: If a value of 0 was written into the address register then

the counter would count from 0 to 18 before resetting back

to 0. If a value of 15 was written into the address register

then the counter would count from 15 to 18 before looping

back to 15. If a value greater than or equal to 18 is placed

into the address register the counter will continuously loop

on this value. Auto addressing is initiated on the falling edge

of LOAD when ADDRDATA is 0 and LHBYTE is 1. Incre-

menting and loading of data registers will not commence

until the falling edge of LOAD after ADDRDATA goes to 1.

The next rising edge of LOAD will load the first byte of data.

Auto Incrementing is disabled on the falling edge of LOAD

after ADDRDATA and LHBYTE goes low.

ADDRCNTR LOGIC

Addresses for the data registers can be generated by one of

two methods. Manual addressing requires that each byte of

each register that needs to be loaded needs to be ad-

dressed. To load both bytes of all 19 registers would require

a total of 57 load cycles (19 address and 38 data cycles).

Auto Addressing requires that only the initial register value

be specified. The Auto Load sequence would require only

39 load cycles to completely program all registers (1 ad-

dress and 38 data cycles). In the auto load sequence the

low order byte of the data register will be written first fol-

lowed by the high order byte on the next load cycle. At the

Manual Addressing Mode

Load Falling Edge

Ý

Cycle

Load Rising Edge

1

2

3

4

5

6

Enable Manual Addressing

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Manual Addressing

Enable Lbyte Data Load

Enable Hbyte Data Load

Load Address m

Load Lbyte m

Load Hbyte m

Load Address n

Load Lbyte n

Load Hbyte n

TL/F/10137–7

Auto Addressing Mode

Load Falling Edge

Ý

Cycle

Load Rising Edge

1

2

3

4

5

6

Enable Auto Addressing

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Manual Addressing

Load Start Address n

Load Lbyte (n)

Load Hbyte (n); Inc Counter

a

Load Lbyte (n 1)

a

Load Hbyte (n 1); Inc Counter

Load Address

TL/F/10137–8

6

Addressing Logic (Continued)

ADDRDEC LOGIC

The ADDRDEC logic decodes the current address and gen-

erates the enable signal for the appropriate register. The

enable values for the registers and counters change on the

falling edge of LOAD. Two types of ADDRDEC logic is en-

abled by 2 pair of addresses, Addresses 22 or 54 (Vectored

Restart logic) and Addresses 23 or 55 (Vectored Clear log-

ic). Loading these addresses will enable the appropriate log-

ic and put the part into either a Restart (all counter registers

are reinitialized with preprogrammed data) or Clear (all reg-

isters are cleared to zero) state. Reloading the same

ADDRDEC address will not cause any change in the state of

the part. The outputs during these states are frozen and the

internal CLOCK is disabled. Clocking the part during a Vec-

tored Restart or Vectored Clear state will have no effect on

the part. To resume operation in the new state, or disable

the Vectored Restart or Vectored Clear state, another non-

ADDRDEC address must be loaded. Operation will begin in

the new state on the rising edge of the non-ADDRDEC load

pulse. It is recommended that an unused address be loaded

following an ADDRDEC operation to prevent data registers

from accidentally being corrupted. The following Addresses

are used by the device.

TL/F/10137–9

FIGURE 3. ADDRDEC Timing

GEN LOCKING

The ’ACT715/LM1882 and ’ACT715-R/LM1882-R is de-

signed for master SYNC and BLANK signal generation.

However, the devices can be synchronized (slaved) to an

external timing signal in a limited sense. Using Vectored

Restart, the user can reset the counting sequence to a giv-

en location, the beginning, at a given time, the rising edge of

the LOAD that removes Vector Restart. At this time the next

CLOCK pulse will be CLOCK 1 and the count will restart at

the beginning of the first odd line.

Address 0

Status Register REG0

Address 1–18 Data Registers REG1–REG18

Address 19–21 Unused

Address 22/54 Restart Vector (Restarts Device)

Address 23/55 Clear Vector (Zeros All Registers)

Address 24–31 Unused

Preconditioning the part during normal operation, before the

desired synchronizing pulse, is necesasry. However, since

LOAD and CLOCK are asynchronous and independent, this

is possible without interruption or data and performance cor-

ruption. If the defaulted 14.31818 MHz RS-170 values are

being used, preconditioning and restarting can be minimized

by using the CLEAR pulse instead of the Vectored Restart

operation. The ’ACT715-R/LM1882-R is better suited for

this application because it eliminates the need to program a

1 into Bit 10 of the Status Register to enable the CLOCK.

Gen Locking to another count location other than the very

beginning or separate horizontal/vertical resetting is not

possible with the ’ACT715/LM1882 nor the ’ACT715-R/

LM1882-R.

Address 32–50 Register Scan Addresses

Address 51–53 Counter Scan Addresses

Address 56–63 Unused

At any given time only one register at most is selected. It is

possible to have no registers selected.

VECTORED RESTART ADDRESS

The function of addresses 22 (16H) or 54 (36H) are similar

to that of the CLR pin except that the preprogramming of

the registers is not affected. It is recommended but not re-

quired that this address is read after the initial device config-

uration load sequence. A 1 on the ADDRDATA pin (Auto

Addressing Mode) will not cause this address to automati-

cally increment. The address will loop back onto itself re-

gardless of the state of ADDRDATA unless the address on

the Data inputs has been changed with ADDRDATA at 0.

SCAN MODE LOGIC

A scan mode is available in the ACT715/LM1882 that al-

lows the user to non-destructively verify the contents of the

registers. Scan mode is invoked through reading a scan ad-

dress into the address register. The scan address of a given

a

register is defined by the Data register address

32. The

VECTORED CLEAR ADDRESS

internal Clocking signal is disabled when a scan address is

read. Disabling the clock freezes the device in it’s present

state. Data can then be serially scanned out of the data

registers through the ODD/EVEN Pin. The LSB will be

scanned out first. Since each register is 12 bits wide, com-

pletely scanning out data of the addressed register will re-

quire 12 CLOCK pulses. More than 12 CLOCK pulses on the

same register will only cause the MSB to repeat on the out-

put. Re-scanning the same register will require that register

to be reloaded. The value of the two horizontal counters and

1 vertical counter can also be scanned out by using address

numbers 51–53. Note that before the part will scan out the

data, the LOAD signal must be brought back HIGH.

Addresses 23 (17H) or 55 (37H) is used to clear all registers

to zero simultaneously. This function may be desirable to

use prior to loading new data into the Data or Status Regis-

ters. This address is read into the device in a similar fashion

as all of the other registers. A 1 on the ADDRDATA pin

(Auto Addressing Mode) will not cause this address to auto-

matically increment. The address will loop back onto itself

regardless of the state of ADDRDATA unless the address

on the Data inputs has been changed with ADDRDATA at 0.

7

Addressing Logic (Continued)

Normal device operation can be resumed by loading in a

non-scan address. As the scanning of the registers is a non-

destructive scan, the device will resume correct operation

from the point at which it was halted.

Reg

D Value H

Register Description

REG0

0

000 Status Register (715/LM1882)

REG0 1024 400 Status Register (715-R/LM1882-R)

REG1

REG2

REG3

REG4

23

91

017 HFP End Time

RS170 Default Register Values

05B HSYNC Pulse End Time

The tables below show the values programmed for the

RS170 Format (using a 14.31818 MHz clock signal) and

how they compare against the actual EIA RS170 Specifica-

tions. The default signals that will be output are CSYNC,

CBLANK, HDRIVE and VDRIVE. The device initially starts at

the beginning of the odd field of interlace. All signals have

active low pulses and the clock is disabled at power up.

Registers 13 and 14 are not involved in the actual signal

information. If the Vertical Interrupt was selected so that a

pulse indicating the active lines would be output.

157 09D HBLANK Pulse End Time

910 38E Total Horizontal Clocks

REG5

REG6

REG7

REG8

7

007 VFP End Time

13

41

00D VSYNC Pulse End Time

029 VBLANK Pulse End Time

525 20D Total Vertical Lines

REG9

57 039 Equalization Pulse End Time

REG10 410 19A Serration Pulse Start Time

REG11

1

001 Pulse Interval Start Time

013 Pulse Interval End Time

REG12 19

REG13 41

029 Vertical Interrupt Activate Time

REG14 526 20E Vertical Interrupt Deactivate Time

REG15 911 38F Horizontal Drive Start Time

REG16 92

REG17

05C Horizontal Drive End Time

001 Vertical Drive Start Time

015 Vertical Drive End Time

1

REG18 21

Rate

Period

Input Clock

Line Rate

14.31818 MHz

15.73426 kHz

59.94 Hz

69.841 ns

63.556 ms

16.683 ms

33.367 ms

Field Rate

Frame Rate

29.97 Hz

RS170 Horizontal Data

Signal

Width

ms

1.536

%H

Specification (ms)

g

1.5 0.1

HFP

22 Clocks

68 Clocks

156 Clocks

91 Clocks

34 Clocks

68 Clocks

910 Clocks

g

4.7 0.1

HSYNC Width

HBLANK Width

HDRIVE Width

HEQP Width

HSERR Width

HPER iod

4.749

10.895

6.356

7.47

17.15

10.00

3.74

g

10.9 0.2

g

0.1H 0.005H

g

2.3 0.1

2.375

g

4.7 0.1

4.749

7.47

63.556

100

RS170 Vertical Data

VFP

3 Lines

190.67

1271.12

699.12

6 EQP Pulses

VSYNC Width

VBLANK Width

VDRIVE Width

VEQP Intrvl

6 Serration Pulses

g

0.075V 0.005V

20 Lines

11.0 Lines

9 Lines

7.62

4.20

3.63

g

0.04V 0.006V

9 Lines/Field

VPERiod (field)

VPERiod (frame)

262.5 Lines

525 Lines

16.683 ms

33.367 ms

16.683 ms/Field

33.367 ms/Frame

8

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Junction Temperature (T )

J

Ceramic

Plastic

175 C

§

140 C

§

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature and output/input loading variables. National does not recom-

mend operation of FACT^TMcircuits outside databook specifications.

b

a

0.5V to 7.0V

Supply Voltage (V

)

CC

DC Input Diode Current (I

)

IK

e b

e

b

a

V

0.5V

a

20 mA

I

V

0.5V

CC

b

a

0.5V

DC Input Voltage (V )

I

0.5V to V

CC

Recommended Operating

Conditions

DC Output Diode Current (I

)

OK

e b

b

a

V

0.5V

a

20 mA

O

e

V

CC

0.5V

Supply Voltage (V

)

CC

4.5V to 5.5V

a

0.5V

DC Output Voltage (V

DC Output Source

)

O

CC

Input Voltage (V )

I

0V to V

CC

Output Voltage (V

)

O

CC

g

or Sink Current (I

)

O

15 mA

Operating Temperature (T )

A

DC V

or Ground Current

CC

b

a

40 C to 85 C

74ACT

54ACT

§

55 C to 125 C

§

g

per Output Pin (I or I

CC

)

20 mA

GND

)

a

§

b

a

65 C to 150 C

Storage Temperature (T

§

STG

Minimum Input Edge Rate (DV/Dt)

V

from 0.8V to 2.0V

@

IN

4.5V, 5.5V

125 mV/ns

CC

DC Characteristics For ’ACT Family Devices over Operating Temperature Range (unless otherwise specified)

ACT/LM1882 54ACT/LM1882 74ACT/LM1882

e b

T

55 C

§

A

e a

e b

40 C

V

T

25 C

T

A

§

CC

A

a

e

Symbol

Parameter

to 125 C

Units

Conditions

§

50 pF

e

a

to 85 C

(V)

C

50 pF

§

L

C

L

Typ

Guaranteed Limits

e b

OUT

V

Minimum High Level

Output Voltage

4.5

5.5

4.49

5.49

4.4

5.4

4.4

5.4

4.4

5.4

V

I

50 mA

OH

OL

e

4.5

5.5

3.86

4.86

3.7

4.7

3.76

4.76

V

*V

IN

V /V

IL IH

e b

I

8 mA

OH

e

V

Maximum Low Level

Output Voltage

4.5

5.5

0.001

0.1

V

I

50 mA

OUT

e

e a

4.5

5.5

0.36

0.5

0.44

V

*V

IN

V

/V

IL IH

I

8 mA

OH

I

Minimum Dynamic

Output Current

OLD

OHD

IN

e

5.5

32.0

mA

V

1.65V

OLD

Minimum Dynamic

Output Current

b

32.0

V

3.85V

OHD

e

Maximum Input

Leakage Current

V

CC

, GND

I

g

1.0

0.1

1.0

Supply Current

Quiescent

CC

e

5.5

8.0

160

1.6

80

1.5

mA

V

, GND

IN

CC

b

2.1V

Maximum I /Input

CC

0.6

mA

CCT

IN

CC

*All outputs loaded; thresholds on input associated with input under test.

Note 1: Test Load 50 pF, 500X to Ground.

9

AC Electrical Characteristics

ACT/LM1882

54ACT/LM1882

e b

74ACT/LM1882

e b

T

55 C

T

A

40 C

§

to 125 C

§

to 85 C

A

e a

A

V

T

25 C

§

50 pF

CC

a

e

a

e

Symbol

Parameter

Units

§

50 pF

§

50 pF

e

(V)

C

L

C

L

Min

Typ

Max

Min

Max

Min

Max

f

Interlaced f

MAX

MAXI

MAX

5.0

170

190

130

145

3.5

150

MHz

ns

(HMAX/2 is ODD)

Non-Interlaced f

MAX

190

4.0

220

175

3.5

(HMAX/2 is EVEN)

t

Clock to Any Output

PLH1

PHL1

13.0

15.5

19.5

18.5

t

Clock to ODDEVEN

(Scan Mode)

PLH2

PHL2

5.0

4.5

4.0

15.0

11.5

17.0

16.0

3.5

3.0

22.0

20.0

3.5

3.0

20.5

19.5

ns

t

Load to Outputs

PLH3

AC Operating Requirements

ACT/LM1882

e a

54ACT/LM1882

e b

74ACT/LM1882

e b

V

T

55 C

T

A

40 C

§

to 125 C

§

to 85 C

CC

A

Symbol

Parameter

T

25 C

§

Units

A

a

(V)

§

Typ

Guaranteed Minimums

Control Setup Time

b

t

ADDR/DATA to LOAD

b

3.0

4.0

4.5

ns

sc

5.0

L/HBYTE to LOAD

4.0

Data Setup Time

a

t

D7–D0 to LOAD

2.0

4.0

4.5

ns

sd

hc

Control Hold Time

b

LOAD to L/HBYTE

LOAD to ADDR/DATA

0

1.0

ns

Data Hold Time

a

LOAD to D7–D0

t

5.0

1.0

5.5

2.0

7.0

2.0

8.0

2.0

8.0

ns

hd

a

LOAD to CLK (Note 1)

rec

Load Pulse Width

LOW

t

5.0

3.0

5.5

5.0

5.5

7.5

5.5

7.5

ns

b

a

wld

HIGH

t

CLR Pulse Width HIGH

5.0

5.5

2.5

6.5

3.0

9.5

4.0

9.5

3.5

ns

wclr

wck

CLOCK Pulse Width

(HIGH or LOW)

Note 1: Removal of Vectored Reset or Restart to Clock.

Capacitance

Symbol

Parameter

Typ

7.0

Units

Conditions

e

C

Input Capacitance

pF

V

5.0V

IN

CC

Power Dissipation

Capacitance

17.0

PD

CC

10

AC Operating Requirements (Continued)

TL/F/10137–6

FIGURE 4. AC Specifications

Additional Applications Information

POWERING UP

PREPROGRAMMING ‘‘ON-THE-FLY’’

The ’ACT715/LM1882 default value for Bit 10 of the Status

Register is 0. This means that when the CLEAR pulse is

applied and the registers are initialized by loading the de-

fault values the CLOCK is disabled. Before operation can

begin, Bit 10 must be changed to a 1 to enable CLOCK. If

the default values are needed (no other programming is re-

quired) thenFigure 5 illustrates a hardwired solution to facili-

tate the enabling of the CLOCK after power-up. Should con-

trol signals be difficult to obtain, Figure 6 illustrates a possi-

ble solution to automatically enable the CLOCK upon pow-

er-up. Use of the ’ACT715-R/LM1882-R eliminates the

need for most of this circuitry. Modifications of the Figure 6

circuit can be made to obtain the lone CLEAR pulse still

needed upon power-up.

Although the ’ACT715/LM1882 and ’ACT715-R/LM1882-R

are completely programmable, certain limitations must be

set as to when and how the parts can be reprogrammed.

Care must be taken when reprogramming any End Time

registers to a new value that is lower than the current value.

Should the reprogramming occur when the counters are at a

count after the new value but before the old value, then the

counters will continue to count up to 4096 before rolling

over.

For this reason one of the following two precautions are

recommended when reprogramming ‘‘on-the-fly’’. The first

recommendation is to reprogram horizontal values during

the horizontal blank interval only and/or vertical values dur-

ing the vertical blank interval only. Since this would require

delicate timing requirements the second recommendation

may be more appropriate.

Note that, although during a Vectored Restart none of the

preprogrammed registers are affected, some signals are af-

fected for the duration of one frame only. These signals are

the Horizontal and Vertical Drive signals. After a Vectored

Restart the beginning of these signals will occur at the first

CLK. The end of the signals will occur as programmed. At

the completion of the first frame, the signals will resume to

their programmed start and end time.

The second recommendation is to program a Vectored Re-

start as the final step of reprogramming. This will ensure

that all registers are set to the newly programmed values

and that all counters restart at the first CLK position. This

will avoid overrunning the counter end times and will main-

tain the video integrity.

TL/F/10137–10

FIGURE 5. Default RS170 Hardwire Configuration

11

Additional Applications Information (Continued)

TL/F/10137–11

Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND

Components

R1: 4.7k

R2: 10k

C1: 10 mF

C2: 50 pF

FIGURE 6. Circuit for Clear and Load Pulse Generation

Ordering Information

The device number is used to form part of a simplified purchasing code where a package type and temperature range are

defined as follows:

74ACT 715

P

C

QR

Temperature Range Family

Special Variations

e

74ACT

54ACT

Commercial TTL-Compatible

Military TTL-Compatible

X

QR

Devices shipped in 13 reels

×

Commercial grade device with

burn-in

Device Type

e

QB

Military grade device with

environmental and burn-in

processing shipped in tubes.

e

715

715-R

Default: CLOCK Disabled

Default: CLOCK Enabled

Package Code

Temperature Range

e

P

D

L

Plastic DIP

Ceramic DIP

Leadless Chip Carrier (LCC)

Small Outline (SOIC)

e

b a

C

M

Commercial ( 40 C to 85 C)

§

b a

Military ( 55 C to 125 C)

§

S

OR

e

LM1882CM

LM1882CN

Commercial Small Outline (SOIC)

Commercial Plastic DIP

Default:

CLOCK

Disabled

e

LM1882J/883

LM1882E/883

Military Ceramic Dip

Military Leadless Chip Carrier

e

Default

CLOCK

Enabled

LM1882-RCM

LM1882-RCN

Commercial Small Outline (SOIC)

Commercial Plastic DIP

e

LM1882-RJ/883

LM1882-RE/883

Military Ceramic Dip

Military Leadless Chip Carrier

12

13

Physical Dimensions inches (millimeters)

20-Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

14

Physical Dimensions inches (millimeters) (Continued)

20-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J20A

20-Lead Small Outline Integrated Circuit (S)

NS Package Number M20B

15

Physical Dimensions inches (millimeters) (Continued)

20-Lead Plastic Dual-In-Line Package (P)

NS Package Number N20B

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

National Semiconductor

Corporation

National Semiconductor

Europe

National Semiconductor

Hong Kong Ltd.

National Semiconductor

Japan Ltd.

a

1111 West Bardin Road

Arlington, TX 76017

Tel: 1(800) 272-9959

Fax: 1(800) 737-7018

Fax:

(

49) 0-180-530 85 86

@

13th Floor, Straight Block,

Ocean Centre, 5 Canton Rd.

Tsimshatsui, Kowloon

Hong Kong

Tel: (852) 2737-1600

Fax: (852) 2736-9960

Tel: 81-043-299-2309

Fax: 81-043-299-2408

Email: cnjwge tevm2.nsc.com

a

Deutsch Tel:

English Tel:

Fran3ais Tel:

Italiano Tel:

(

49) 0-180-530 85 85

49) 0-180-532 78 32

49) 0-180-532 93 58

49) 0-180-534 16 80

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	74ACT715DC
厂家：	TEXAS INSTRUMENTS
描述：	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20 CD
文件：	总16页 (文件大小：236K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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